gpio-vf610.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Freescale vf610 GPIO support through PORT and GPIO
  4 *
  5 * Copyright (c) 2014 Toradex AG.
  6 *
  7 * Author: Stefan Agner <stefan@agner.ch>.
  8 */
  9#include <linux/bitops.h>
 10#include <linux/clk.h>
 11#include <linux/err.h>
 12#include <linux/gpio/driver.h>
 13#include <linux/gpio/generic.h>
 14#include <linux/init.h>
 15#include <linux/interrupt.h>
 16#include <linux/io.h>
 17#include <linux/ioport.h>
 18#include <linux/irq.h>
 19#include <linux/pinctrl/consumer.h>
 20#include <linux/platform_device.h>
 21#include <linux/property.h>
 22
 23#define VF610_GPIO_PER_PORT		32
 24
 25struct fsl_gpio_soc_data {
 26	/* SoCs has a Port Data Direction Register (PDDR) */
 27	bool have_paddr;
 28	bool have_dual_base;
 29};
 30
 31struct vf610_gpio_port {
 32	struct gpio_generic_chip chip;
 33	void __iomem *base;
 34	void __iomem *gpio_base;
 35	const struct fsl_gpio_soc_data *sdata;
 36	u8 irqc[VF610_GPIO_PER_PORT];
 37	struct clk *clk_port;
 38	struct clk *clk_gpio;
 39	int irq;
 40};
 41
 42#define GPIO_PDOR		0x00
 43#define GPIO_PSOR		0x04
 44#define GPIO_PCOR		0x08
 45#define GPIO_PTOR		0x0c
 46#define GPIO_PDIR		0x10
 47#define GPIO_PDDR		0x14
 48
 49#define PORT_PCR(n)		((n) * 0x4)
 50#define PORT_PCR_IRQC_OFFSET	16
 51
 52#define PORT_ISFR		0xa0
 53#define PORT_DFER		0xc0
 54#define PORT_DFCR		0xc4
 55#define PORT_DFWR		0xc8
 56
 57#define PORT_INT_OFF		0x0
 58#define PORT_INT_LOGIC_ZERO	0x8
 59#define PORT_INT_RISING_EDGE	0x9
 60#define PORT_INT_FALLING_EDGE	0xa
 61#define PORT_INT_EITHER_EDGE	0xb
 62#define PORT_INT_LOGIC_ONE	0xc
 63
 64#define IMX8ULP_GPIO_BASE_OFF	0x40
 65#define IMX8ULP_BASE_OFF	0x80
 66
 67static const struct fsl_gpio_soc_data vf610_data = {
 68	.have_dual_base = true,
 69};
 70
 71static const struct fsl_gpio_soc_data imx_data = {
 72	.have_paddr = true,
 73	.have_dual_base = true,
 74};
 75
 76static const struct fsl_gpio_soc_data imx8ulp_data = {
 77	.have_paddr = true,
 78};
 79
 80static const struct of_device_id vf610_gpio_dt_ids[] = {
 81	{ .compatible = "fsl,vf610-gpio",	.data = &vf610_data },
 82	{ .compatible = "fsl,imx7ulp-gpio",	.data = &imx_data, },
 83	{ .compatible = "fsl,imx8ulp-gpio",	.data = &imx8ulp_data, },
 84	{ /* sentinel */ }
 85};
 86
 87static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
 88{
 89	writel_relaxed(val, reg);
 90}
 91
 92static inline u32 vf610_gpio_readl(void __iomem *reg)
 93{
 94	return readl_relaxed(reg);
 95}
 96
 97static void vf610_gpio_irq_handler(struct irq_desc *desc)
 98{
 99	struct vf610_gpio_port *port =
100		gpiochip_get_data(irq_desc_get_handler_data(desc));
101	struct irq_chip *chip = irq_desc_get_chip(desc);
102	int pin;
103	unsigned long irq_isfr;
104
105	chained_irq_enter(chip, desc);
106
107	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
108
109	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
110		vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
111
112		generic_handle_domain_irq(port->chip.gc.irq.domain, pin);
113	}
114
115	chained_irq_exit(chip, desc);
116}
117
118static void vf610_gpio_irq_ack(struct irq_data *d)
119{
120	struct vf610_gpio_port *port =
121		gpiochip_get_data(irq_data_get_irq_chip_data(d));
122	int gpio = d->hwirq;
123
124	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
125}
126
127static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
128{
129	struct vf610_gpio_port *port =
130		gpiochip_get_data(irq_data_get_irq_chip_data(d));
131	u8 irqc;
132
133	switch (type) {
134	case IRQ_TYPE_EDGE_RISING:
135		irqc = PORT_INT_RISING_EDGE;
136		break;
137	case IRQ_TYPE_EDGE_FALLING:
138		irqc = PORT_INT_FALLING_EDGE;
139		break;
140	case IRQ_TYPE_EDGE_BOTH:
141		irqc = PORT_INT_EITHER_EDGE;
142		break;
143	case IRQ_TYPE_LEVEL_LOW:
144		irqc = PORT_INT_LOGIC_ZERO;
145		break;
146	case IRQ_TYPE_LEVEL_HIGH:
147		irqc = PORT_INT_LOGIC_ONE;
148		break;
149	default:
150		return -EINVAL;
151	}
152
153	port->irqc[d->hwirq] = irqc;
154
155	if (type & IRQ_TYPE_LEVEL_MASK)
156		irq_set_handler_locked(d, handle_level_irq);
157	else
158		irq_set_handler_locked(d, handle_edge_irq);
159
160	return 0;
161}
162
163static void vf610_gpio_irq_mask(struct irq_data *d)
164{
165	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
166	struct vf610_gpio_port *port = gpiochip_get_data(gc);
167	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
168	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
169
170	vf610_gpio_writel(0, pcr_base);
171	gpiochip_disable_irq(gc, gpio_num);
172}
173
174static void vf610_gpio_irq_unmask(struct irq_data *d)
175{
176	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
177	struct vf610_gpio_port *port = gpiochip_get_data(gc);
178	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
179	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
180
181	gpiochip_enable_irq(gc, gpio_num);
182	vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET,
183			  pcr_base);
184}
185
186static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
187{
188	struct vf610_gpio_port *port =
189		gpiochip_get_data(irq_data_get_irq_chip_data(d));
190
191	if (enable)
192		enable_irq_wake(port->irq);
193	else
194		disable_irq_wake(port->irq);
195
196	return 0;
197}
198
199static const struct irq_chip vf610_irqchip = {
200	.name = "gpio-vf610",
201	.irq_ack = vf610_gpio_irq_ack,
202	.irq_mask = vf610_gpio_irq_mask,
203	.irq_unmask = vf610_gpio_irq_unmask,
204	.irq_set_type = vf610_gpio_irq_set_type,
205	.irq_set_wake = vf610_gpio_irq_set_wake,
206	.flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND
207			| IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
208	GPIOCHIP_IRQ_RESOURCE_HELPERS,
209};
210
211static void vf610_gpio_disable_clk(void *data)
212{
213	clk_disable_unprepare(data);
214}
215
216static int vf610_gpio_probe(struct platform_device *pdev)
217{
218	struct gpio_generic_chip_config config;
219	struct device *dev = &pdev->dev;
220	struct vf610_gpio_port *port;
221	struct gpio_chip *gc;
222	struct gpio_irq_chip *girq;
223	unsigned long flags;
224	int i;
225	int ret;
226	bool dual_base;
227
228	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
229	if (!port)
230		return -ENOMEM;
231
232	port->sdata = device_get_match_data(dev);
233
234	dual_base = port->sdata->have_dual_base;
235
236	/*
237	 * Handle legacy compatible combinations which used two reg values
238	 * for the i.MX8ULP and i.MX93.
239	 */
240	if (device_is_compatible(dev, "fsl,imx7ulp-gpio") &&
241	    (device_is_compatible(dev, "fsl,imx93-gpio") ||
242	    (device_is_compatible(dev, "fsl,imx8ulp-gpio"))))
243		dual_base = true;
244
245	if (dual_base) {
246		port->base = devm_platform_ioremap_resource(pdev, 0);
247		if (IS_ERR(port->base))
248			return PTR_ERR(port->base);
249
250		port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
251		if (IS_ERR(port->gpio_base))
252			return PTR_ERR(port->gpio_base);
253	} else {
254		port->base = devm_platform_ioremap_resource(pdev, 0);
255		if (IS_ERR(port->base))
256			return PTR_ERR(port->base);
257
258		port->gpio_base = port->base + IMX8ULP_GPIO_BASE_OFF;
259		port->base = port->base + IMX8ULP_BASE_OFF;
260	}
261
262	port->irq = platform_get_irq(pdev, 0);
263	if (port->irq < 0)
264		return port->irq;
265
266	port->clk_port = devm_clk_get(dev, "port");
267	ret = PTR_ERR_OR_ZERO(port->clk_port);
268	if (!ret) {
269		ret = clk_prepare_enable(port->clk_port);
270		if (ret)
271			return ret;
272		ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
273					       port->clk_port);
274		if (ret)
275			return ret;
276	} else if (ret == -EPROBE_DEFER) {
277		/*
278		 * Percolate deferrals, for anything else,
279		 * just live without the clocking.
280		 */
281		return ret;
282	}
283
284	port->clk_gpio = devm_clk_get(dev, "gpio");
285	ret = PTR_ERR_OR_ZERO(port->clk_gpio);
286	if (!ret) {
287		ret = clk_prepare_enable(port->clk_gpio);
288		if (ret)
289			return ret;
290		ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
291					       port->clk_gpio);
292		if (ret)
293			return ret;
294	} else if (ret == -EPROBE_DEFER) {
295		return ret;
296	}
297
298	gc = &port->chip.gc;
299	flags = GPIO_GENERIC_PINCTRL_BACKEND;
300	/*
301	 * We only read the output register for current value on output
302	 * lines if the direction register is available so we can switch
303	 * direction.
304	 */
305	if (port->sdata->have_paddr)
306		flags |= GPIO_GENERIC_READ_OUTPUT_REG_SET;
307
308	config = (struct gpio_generic_chip_config) {
309		.dev = dev,
310		.sz = 4,
311		.dat = port->gpio_base + GPIO_PDIR,
312		.set = port->gpio_base + GPIO_PDOR,
313		.dirout = port->sdata->have_paddr ?
314				port->gpio_base + GPIO_PDDR : NULL,
315		.flags = flags,
316	};
317
318	ret = gpio_generic_chip_init(&port->chip, &config);
319	if (ret)
320		return dev_err_probe(dev, ret, "unable to init generic GPIO\n");
321	gc->label = dev_name(dev);
322	gc->base = -1;
323
324	/* Mask all GPIO interrupts */
325	for (i = 0; i < gc->ngpio; i++)
326		vf610_gpio_writel(0, port->base + PORT_PCR(i));
327
328	/* Clear the interrupt status register for all GPIO's */
329	vf610_gpio_writel(~0, port->base + PORT_ISFR);
330
331	girq = &gc->irq;
332	gpio_irq_chip_set_chip(girq, &vf610_irqchip);
333	girq->parent_handler = vf610_gpio_irq_handler;
334	girq->num_parents = 1;
335	girq->parents = devm_kcalloc(&pdev->dev, 1,
336				     sizeof(*girq->parents),
337				     GFP_KERNEL);
338	if (!girq->parents)
339		return -ENOMEM;
340	girq->parents[0] = port->irq;
341	girq->default_type = IRQ_TYPE_NONE;
342	girq->handler = handle_edge_irq;
343
344	return devm_gpiochip_add_data(dev, gc, port);
345}
346
347static struct platform_driver vf610_gpio_driver = {
348	.driver		= {
349		.name	= "gpio-vf610",
350		.of_match_table = vf610_gpio_dt_ids,
351	},
352	.probe		= vf610_gpio_probe,
353};
354
355module_platform_driver(vf610_gpio_driver);
356MODULE_DESCRIPTION("VF610 GPIO driver");
357MODULE_LICENSE("GPL");