gpio-uniphier.c

  1// SPDX-License-Identifier: GPL-2.0
  2//
  3// Copyright (C) 2017 Socionext Inc.
  4//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5
  6#include <linux/bits.h>
  7#include <linux/gpio/driver.h>
  8#include <linux/irq.h>
  9#include <linux/irqdomain.h>
 10#include <linux/module.h>
 11#include <linux/of.h>
 12#include <linux/of_irq.h>
 13#include <linux/platform_device.h>
 14#include <linux/property.h>
 15#include <linux/spinlock.h>
 16#include <dt-bindings/gpio/uniphier-gpio.h>
 17
 18#define UNIPHIER_GPIO_IRQ_MAX_NUM	24
 19
 20#define UNIPHIER_GPIO_PORT_DATA		0x0	/* data */
 21#define UNIPHIER_GPIO_PORT_DIR		0x4	/* direction (1:in, 0:out) */
 22#define UNIPHIER_GPIO_IRQ_EN		0x90	/* irq enable */
 23#define UNIPHIER_GPIO_IRQ_MODE		0x94	/* irq mode (1: both edge) */
 24#define UNIPHIER_GPIO_IRQ_FLT_EN	0x98	/* noise filter enable */
 25#define UNIPHIER_GPIO_IRQ_FLT_CYC	0x9c	/* noise filter clock cycle */
 26
 27struct uniphier_gpio_priv {
 28	struct gpio_chip chip;
 29	struct irq_chip irq_chip;
 30	struct irq_domain *domain;
 31	void __iomem *regs;
 32	spinlock_t lock;
 33	u32 saved_vals[];
 34};
 35
 36static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
 37{
 38	unsigned int reg;
 39
 40	reg = (bank + 1) * 8;
 41
 42	/*
 43	 * Unfortunately, the GPIO port registers are not contiguous because
 44	 * offset 0x90-0x9f is used for IRQ.  Add 0x10 when crossing the region.
 45	 */
 46	if (reg >= UNIPHIER_GPIO_IRQ_EN)
 47		reg += 0x10;
 48
 49	return reg;
 50}
 51
 52static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
 53					    unsigned int *bank, u32 *mask)
 54{
 55	*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
 56	*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
 57}
 58
 59static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
 60				     unsigned int reg, u32 mask, u32 val)
 61{
 62	unsigned long flags;
 63	u32 tmp;
 64
 65	spin_lock_irqsave(&priv->lock, flags);
 66	tmp = readl(priv->regs + reg);
 67	tmp &= ~mask;
 68	tmp |= mask & val;
 69	writel(tmp, priv->regs + reg);
 70	spin_unlock_irqrestore(&priv->lock, flags);
 71}
 72
 73static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank,
 74				     unsigned int reg, u32 mask, u32 val)
 75{
 76	struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
 77
 78	if (!mask)
 79		return;
 80
 81	uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
 82				 mask, val);
 83}
 84
 85static void uniphier_gpio_offset_write(struct gpio_chip *chip,
 86				       unsigned int offset, unsigned int reg,
 87				       int val)
 88{
 89	unsigned int bank;
 90	u32 mask;
 91
 92	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
 93
 94	uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);
 95}
 96
 97static int uniphier_gpio_offset_read(struct gpio_chip *chip,
 98				     unsigned int offset, unsigned int reg)
 99{
100	struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
101	unsigned int bank, reg_offset;
102	u32 mask;
103
104	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
105	reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
106
107	return !!(readl(priv->regs + reg_offset) & mask);
108}
109
110static int uniphier_gpio_get_direction(struct gpio_chip *chip,
111				       unsigned int offset)
112{
113	if (uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR))
114		return GPIO_LINE_DIRECTION_IN;
115
116	return GPIO_LINE_DIRECTION_OUT;
117}
118
119static int uniphier_gpio_direction_input(struct gpio_chip *chip,
120					 unsigned int offset)
121{
122	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1);
123
124	return 0;
125}
126
127static int uniphier_gpio_direction_output(struct gpio_chip *chip,
128					  unsigned int offset, int val)
129{
130	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
131	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0);
132
133	return 0;
134}
135
136static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset)
137{
138	return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA);
139}
140
141static int uniphier_gpio_set(struct gpio_chip *chip,
142			     unsigned int offset, int val)
143{
144	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
145
146	return 0;
147}
148
149static int uniphier_gpio_set_multiple(struct gpio_chip *chip,
150				      unsigned long *mask, unsigned long *bits)
151{
152	unsigned long i, bank, bank_mask, bank_bits;
153
154	for_each_set_clump8(i, bank_mask, mask, chip->ngpio) {
155		bank = i / UNIPHIER_GPIO_LINES_PER_BANK;
156		bank_bits = bitmap_get_value8(bits, i);
157
158		uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA,
159					 bank_mask, bank_bits);
160	}
161
162	return 0;
163}
164
165static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
166{
167	struct irq_fwspec fwspec;
168
169	if (offset < UNIPHIER_GPIO_IRQ_OFFSET)
170		return -ENXIO;
171
172	fwspec.fwnode = dev_fwnode(chip->parent);
173	fwspec.param_count = 2;
174	fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET;
175	/*
176	 * IRQ_TYPE_NONE is rejected by the parent irq domain. Set LEVEL_HIGH
177	 * temporarily. Anyway, ->irq_set_type() will override it later.
178	 */
179	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
180
181	return irq_create_fwspec_mapping(&fwspec);
182}
183
184static void uniphier_gpio_irq_mask(struct irq_data *data)
185{
186	struct uniphier_gpio_priv *priv = irq_data_get_irq_chip_data(data);
187	u32 mask = BIT(irqd_to_hwirq(data));
188
189	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0);
190
191	irq_chip_mask_parent(data);
192}
193
194static void uniphier_gpio_irq_unmask(struct irq_data *data)
195{
196	struct uniphier_gpio_priv *priv = irq_data_get_irq_chip_data(data);
197	u32 mask = BIT(irqd_to_hwirq(data));
198
199	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask);
200
201	irq_chip_unmask_parent(data);
202}
203
204static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type)
205{
206	struct uniphier_gpio_priv *priv = irq_data_get_irq_chip_data(data);
207	u32 mask = BIT(irqd_to_hwirq(data));
208	u32 val = 0;
209
210	if (type == IRQ_TYPE_EDGE_BOTH) {
211		val = mask;
212		type = IRQ_TYPE_EDGE_FALLING;
213	}
214
215	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val);
216	/* To enable both edge detection, the noise filter must be enabled. */
217	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val);
218
219	return irq_chip_set_type_parent(data, type);
220}
221
222static int uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv,
223					      unsigned int hwirq)
224{
225	struct device_node *np = priv->chip.parent->of_node;
226	const __be32 *range;
227	u32 base, parent_base, size;
228	int len;
229
230	range = of_get_property(np, "socionext,interrupt-ranges", &len);
231	if (!range)
232		return -EINVAL;
233
234	len /= sizeof(*range);
235
236	for (; len >= 3; len -= 3) {
237		base = be32_to_cpu(*range++);
238		parent_base = be32_to_cpu(*range++);
239		size = be32_to_cpu(*range++);
240
241		if (base <= hwirq && hwirq < base + size)
242			return hwirq - base + parent_base;
243	}
244
245	return -ENOENT;
246}
247
248static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain,
249					      struct irq_fwspec *fwspec,
250					      unsigned long *out_hwirq,
251					      unsigned int *out_type)
252{
253	if (WARN_ON(fwspec->param_count < 2))
254		return -EINVAL;
255
256	*out_hwirq = fwspec->param[0];
257	*out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
258
259	return 0;
260}
261
262static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain,
263					  unsigned int virq,
264					  unsigned int nr_irqs, void *arg)
265{
266	struct uniphier_gpio_priv *priv = domain->host_data;
267	struct irq_fwspec parent_fwspec;
268	irq_hw_number_t hwirq;
269	unsigned int type;
270	int ret;
271
272	if (WARN_ON(nr_irqs != 1))
273		return -EINVAL;
274
275	ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type);
276	if (ret)
277		return ret;
278
279	ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq);
280	if (ret < 0)
281		return ret;
282
283	/* parent is UniPhier AIDET */
284	parent_fwspec.fwnode = domain->parent->fwnode;
285	parent_fwspec.param_count = 2;
286	parent_fwspec.param[0] = ret;
287	parent_fwspec.param[1] = (type == IRQ_TYPE_EDGE_BOTH) ?
288						IRQ_TYPE_EDGE_FALLING : type;
289
290	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
291					    &priv->irq_chip, priv);
292	if (ret)
293		return ret;
294
295	return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
296}
297
298static int uniphier_gpio_irq_domain_activate(struct irq_domain *domain,
299					     struct irq_data *data, bool early)
300{
301	struct uniphier_gpio_priv *priv = domain->host_data;
302	struct gpio_chip *chip = &priv->chip;
303
304	return gpiochip_lock_as_irq(chip,
305			irqd_to_hwirq(data) + UNIPHIER_GPIO_IRQ_OFFSET);
306}
307
308static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain,
309						struct irq_data *data)
310{
311	struct uniphier_gpio_priv *priv = domain->host_data;
312	struct gpio_chip *chip = &priv->chip;
313
314	gpiochip_unlock_as_irq(chip,
315			irqd_to_hwirq(data) + UNIPHIER_GPIO_IRQ_OFFSET);
316}
317
318static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = {
319	.alloc = uniphier_gpio_irq_domain_alloc,
320	.free = irq_domain_free_irqs_common,
321	.activate = uniphier_gpio_irq_domain_activate,
322	.deactivate = uniphier_gpio_irq_domain_deactivate,
323	.translate = uniphier_gpio_irq_domain_translate,
324};
325
326static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv)
327{
328	/*
329	 * Due to the hardware design, the noise filter must be enabled to
330	 * detect both edge interrupts.  This filter is intended to remove the
331	 * noise from the irq lines.  It does not work for GPIO input, so GPIO
332	 * debounce is not supported.  Unfortunately, the filter period is
333	 * shared among all irq lines.  Just choose a sensible period here.
334	 */
335	writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC);
336}
337
338static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio)
339{
340	return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK);
341}
342
343static int uniphier_gpio_probe(struct platform_device *pdev)
344{
345	struct device *dev = &pdev->dev;
346	struct device_node *parent_np;
347	struct irq_domain *parent_domain;
348	struct uniphier_gpio_priv *priv;
349	struct gpio_chip *chip;
350	struct irq_chip *irq_chip;
351	unsigned int nregs;
352	u32 ngpios;
353	int ret;
354
355	parent_np = of_irq_find_parent(dev->of_node);
356	if (!parent_np)
357		return -ENXIO;
358
359	parent_domain = irq_find_host(parent_np);
360	of_node_put(parent_np);
361	if (!parent_domain)
362		return -EPROBE_DEFER;
363
364	ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
365	if (ret)
366		return ret;
367
368	nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3;
369	priv = devm_kzalloc(dev, struct_size(priv, saved_vals, nregs),
370			    GFP_KERNEL);
371	if (!priv)
372		return -ENOMEM;
373
374	priv->regs = devm_platform_ioremap_resource(pdev, 0);
375	if (IS_ERR(priv->regs))
376		return PTR_ERR(priv->regs);
377
378	spin_lock_init(&priv->lock);
379
380	chip = &priv->chip;
381	chip->label = dev_name(dev);
382	chip->parent = dev;
383	chip->request = gpiochip_generic_request;
384	chip->free = gpiochip_generic_free;
385	chip->get_direction = uniphier_gpio_get_direction;
386	chip->direction_input = uniphier_gpio_direction_input;
387	chip->direction_output = uniphier_gpio_direction_output;
388	chip->get = uniphier_gpio_get;
389	chip->set = uniphier_gpio_set;
390	chip->set_multiple = uniphier_gpio_set_multiple;
391	chip->to_irq = uniphier_gpio_to_irq;
392	chip->base = -1;
393	chip->ngpio = ngpios;
394
395	irq_chip = &priv->irq_chip;
396	irq_chip->name = dev_name(dev);
397	irq_chip->irq_mask = uniphier_gpio_irq_mask;
398	irq_chip->irq_unmask = uniphier_gpio_irq_unmask;
399	irq_chip->irq_eoi = irq_chip_eoi_parent;
400	irq_chip->irq_set_affinity = irq_chip_set_affinity_parent;
401	irq_chip->irq_set_type = uniphier_gpio_irq_set_type;
402
403	uniphier_gpio_hw_init(priv);
404
405	ret = devm_gpiochip_add_data(dev, chip, priv);
406	if (ret)
407		return ret;
408
409	priv->domain = irq_domain_create_hierarchy(
410					parent_domain, 0,
411					UNIPHIER_GPIO_IRQ_MAX_NUM,
412					dev_fwnode(dev),
413					&uniphier_gpio_irq_domain_ops, priv);
414	if (!priv->domain)
415		return -ENOMEM;
416
417	platform_set_drvdata(pdev, priv);
418
419	return 0;
420}
421
422static void uniphier_gpio_remove(struct platform_device *pdev)
423{
424	struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev);
425
426	irq_domain_remove(priv->domain);
427}
428
429static int uniphier_gpio_suspend(struct device *dev)
430{
431	struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
432	unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
433	u32 *val = priv->saved_vals;
434	unsigned int reg;
435	int i;
436
437	for (i = 0; i < nbanks; i++) {
438		reg = uniphier_gpio_bank_to_reg(i);
439
440		*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
441		*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
442	}
443
444	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN);
445	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE);
446	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
447
448	return 0;
449}
450
451static int uniphier_gpio_resume(struct device *dev)
452{
453	struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
454	unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
455	const u32 *val = priv->saved_vals;
456	unsigned int reg;
457	int i;
458
459	for (i = 0; i < nbanks; i++) {
460		reg = uniphier_gpio_bank_to_reg(i);
461
462		writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
463		writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
464	}
465
466	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN);
467	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE);
468	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
469
470	uniphier_gpio_hw_init(priv);
471
472	return 0;
473}
474
475static const struct dev_pm_ops uniphier_gpio_pm_ops = {
476	LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend, uniphier_gpio_resume)
477};
478
479static const struct of_device_id uniphier_gpio_match[] = {
480	{ .compatible = "socionext,uniphier-gpio" },
481	{ /* sentinel */ }
482};
483MODULE_DEVICE_TABLE(of, uniphier_gpio_match);
484
485static struct platform_driver uniphier_gpio_driver = {
486	.probe = uniphier_gpio_probe,
487	.remove = uniphier_gpio_remove,
488	.driver = {
489		.name = "uniphier-gpio",
490		.of_match_table = uniphier_gpio_match,
491		.pm = pm_sleep_ptr(&uniphier_gpio_pm_ops),
492	},
493};
494module_platform_driver(uniphier_gpio_driver);
495
496MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
497MODULE_DESCRIPTION("UniPhier GPIO driver");
498MODULE_LICENSE("GPL v2");