gpio-timberdale.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Timberdale FPGA GPIO driver
  4 * Author: Mocean Laboratories
  5 * Copyright (c) 2009 Intel Corporation
  6 */
  7
  8/* Supports:
  9 * Timberdale FPGA GPIO
 10 */
 11
 12#include <linux/init.h>
 13#include <linux/gpio/driver.h>
 14#include <linux/platform_device.h>
 15#include <linux/irq.h>
 16#include <linux/io.h>
 17#include <linux/timb_gpio.h>
 18#include <linux/interrupt.h>
 19#include <linux/slab.h>
 20
 21#define DRIVER_NAME "timb-gpio"
 22
 23#define TGPIOVAL	0x00
 24#define TGPIODIR	0x04
 25#define TGPIO_IER	0x08
 26#define TGPIO_ISR	0x0c
 27#define TGPIO_IPR	0x10
 28#define TGPIO_ICR	0x14
 29#define TGPIO_FLR	0x18
 30#define TGPIO_LVR	0x1c
 31#define TGPIO_VER	0x20
 32#define TGPIO_BFLR	0x24
 33
 34struct timbgpio {
 35	void __iomem		*membase;
 36	spinlock_t		lock; /* mutual exclusion */
 37	struct gpio_chip	gpio;
 38	int			irq_base;
 39	unsigned long		last_ier;
 40};
 41
 42static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
 43	unsigned offset, bool enabled)
 44{
 45	struct timbgpio *tgpio = gpiochip_get_data(gpio);
 46	unsigned long flags;
 47	u32 reg;
 48
 49	spin_lock_irqsave(&tgpio->lock, flags);
 50	reg = ioread32(tgpio->membase + offset);
 51
 52	if (enabled)
 53		reg |= (1 << index);
 54	else
 55		reg &= ~(1 << index);
 56
 57	iowrite32(reg, tgpio->membase + offset);
 58	spin_unlock_irqrestore(&tgpio->lock, flags);
 59
 60	return 0;
 61}
 62
 63static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
 64{
 65	return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
 66}
 67
 68static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
 69{
 70	struct timbgpio *tgpio = gpiochip_get_data(gpio);
 71	u32 value;
 72
 73	value = ioread32(tgpio->membase + TGPIOVAL);
 74	return (value & (1 << nr)) ? 1 : 0;
 75}
 76
 77static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
 78						unsigned nr, int val)
 79{
 80	return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
 81}
 82
 83static int timbgpio_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
 84{
 85	return timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
 86}
 87
 88static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
 89{
 90	struct timbgpio *tgpio = gpiochip_get_data(gpio);
 91
 92	if (tgpio->irq_base <= 0)
 93		return -EINVAL;
 94
 95	return tgpio->irq_base + offset;
 96}
 97
 98/*
 99 * GPIO IRQ
100 */
101static void timbgpio_irq_disable(struct irq_data *d)
102{
103	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
104	int offset = d->irq - tgpio->irq_base;
105	irq_hw_number_t hwirq = irqd_to_hwirq(d);
106	unsigned long flags;
107
108	spin_lock_irqsave(&tgpio->lock, flags);
109	tgpio->last_ier &= ~(1UL << offset);
110	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
111	spin_unlock_irqrestore(&tgpio->lock, flags);
112
113	gpiochip_disable_irq(&tgpio->gpio, hwirq);
114}
115
116static void timbgpio_irq_enable(struct irq_data *d)
117{
118	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
119	int offset = d->irq - tgpio->irq_base;
120	irq_hw_number_t hwirq = irqd_to_hwirq(d);
121	unsigned long flags;
122
123	gpiochip_enable_irq(&tgpio->gpio, hwirq);
124
125	spin_lock_irqsave(&tgpio->lock, flags);
126	tgpio->last_ier |= 1UL << offset;
127	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
128	spin_unlock_irqrestore(&tgpio->lock, flags);
129}
130
131static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
132{
133	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
134	int offset = d->irq - tgpio->irq_base;
135	unsigned long flags;
136	u32 lvr, flr, bflr = 0;
137	u32 ver;
138	int ret = 0;
139
140	if (offset < 0 || offset >= tgpio->gpio.ngpio)
141		return -EINVAL;
142
143	ver = ioread32(tgpio->membase + TGPIO_VER);
144
145	spin_lock_irqsave(&tgpio->lock, flags);
146
147	lvr = ioread32(tgpio->membase + TGPIO_LVR);
148	flr = ioread32(tgpio->membase + TGPIO_FLR);
149	if (ver > 2)
150		bflr = ioread32(tgpio->membase + TGPIO_BFLR);
151
152	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
153		bflr &= ~(1 << offset);
154		flr &= ~(1 << offset);
155		if (trigger & IRQ_TYPE_LEVEL_HIGH)
156			lvr |= 1 << offset;
157		else
158			lvr &= ~(1 << offset);
159	}
160
161	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
162		if (ver < 3) {
163			ret = -EINVAL;
164			goto out;
165		} else {
166			flr |= 1 << offset;
167			bflr |= 1 << offset;
168		}
169	} else {
170		bflr &= ~(1 << offset);
171		flr |= 1 << offset;
172		if (trigger & IRQ_TYPE_EDGE_FALLING)
173			lvr &= ~(1 << offset);
174		else
175			lvr |= 1 << offset;
176	}
177
178	iowrite32(lvr, tgpio->membase + TGPIO_LVR);
179	iowrite32(flr, tgpio->membase + TGPIO_FLR);
180	if (ver > 2)
181		iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
182
183	iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
184
185out:
186	spin_unlock_irqrestore(&tgpio->lock, flags);
187	return ret;
188}
189
190static void timbgpio_irq(struct irq_desc *desc)
191{
192	struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
193	struct irq_data *data = irq_desc_get_irq_data(desc);
194	unsigned long ipr;
195	int offset;
196
197	data->chip->irq_ack(data);
198	ipr = ioread32(tgpio->membase + TGPIO_IPR);
199	iowrite32(ipr, tgpio->membase + TGPIO_ICR);
200
201	/*
202	 * Some versions of the hardware trash the IER register if more than
203	 * one interrupt is received simultaneously.
204	 */
205	iowrite32(0, tgpio->membase + TGPIO_IER);
206
207	for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
208		generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
209
210	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
211}
212
213static const struct irq_chip timbgpio_irqchip = {
214	.name		= "GPIO",
215	.irq_enable	= timbgpio_irq_enable,
216	.irq_disable	= timbgpio_irq_disable,
217	.irq_set_type	= timbgpio_irq_type,
218	.flags = IRQCHIP_IMMUTABLE,
219	GPIOCHIP_IRQ_RESOURCE_HELPERS,
220};
221
222static int timbgpio_probe(struct platform_device *pdev)
223{
224	int err, i;
225	struct device *dev = &pdev->dev;
226	struct gpio_chip *gc;
227	struct timbgpio *tgpio;
228	struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
229	int irq = platform_get_irq(pdev, 0);
230
231	if (!pdata || pdata->nr_pins > 32) {
232		dev_err(dev, "Invalid platform data\n");
233		return -EINVAL;
234	}
235
236	tgpio = devm_kzalloc(dev, sizeof(*tgpio), GFP_KERNEL);
237	if (!tgpio)
238		return -EINVAL;
239
240	tgpio->irq_base = pdata->irq_base;
241
242	spin_lock_init(&tgpio->lock);
243
244	tgpio->membase = devm_platform_ioremap_resource(pdev, 0);
245	if (IS_ERR(tgpio->membase))
246		return PTR_ERR(tgpio->membase);
247
248	gc = &tgpio->gpio;
249
250	gc->label = dev_name(&pdev->dev);
251	gc->owner = THIS_MODULE;
252	gc->parent = &pdev->dev;
253	gc->direction_input = timbgpio_gpio_direction_input;
254	gc->get = timbgpio_gpio_get;
255	gc->direction_output = timbgpio_gpio_direction_output;
256	gc->set = timbgpio_gpio_set;
257	gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
258	gc->dbg_show = NULL;
259	gc->base = pdata->gpio_base;
260	gc->ngpio = pdata->nr_pins;
261	gc->can_sleep = false;
262
263	err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
264	if (err)
265		return err;
266
267	/* make sure to disable interrupts */
268	iowrite32(0x0, tgpio->membase + TGPIO_IER);
269
270	if (irq < 0 || tgpio->irq_base <= 0)
271		return 0;
272
273	for (i = 0; i < pdata->nr_pins; i++) {
274		irq_set_chip_and_handler(tgpio->irq_base + i,
275			&timbgpio_irqchip, handle_simple_irq);
276		irq_set_chip_data(tgpio->irq_base + i, tgpio);
277		irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);
278	}
279
280	irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
281
282	return 0;
283}
284
285static struct platform_driver timbgpio_platform_driver = {
286	.driver = {
287		.name			= DRIVER_NAME,
288		.suppress_bind_attrs	= true,
289	},
290	.probe		= timbgpio_probe,
291};
292
293/*--------------------------------------------------------------------------*/
294
295builtin_platform_driver(timbgpio_platform_driver);