gpio-thunderx.c

  1/*
  2 * This file is subject to the terms and conditions of the GNU General Public
  3 * License.  See the file "COPYING" in the main directory of this archive
  4 * for more details.
  5 *
  6 * Copyright (C) 2016, 2017 Cavium Inc.
  7 */
  8
  9#include <linux/bitops.h>
 10#include <linux/gpio/driver.h>
 11#include <linux/interrupt.h>
 12#include <linux/io.h>
 13#include <linux/irq.h>
 14#include <linux/kernel.h>
 15#include <linux/module.h>
 16#include <linux/pci.h>
 17#include <linux/property.h>
 18#include <linux/spinlock.h>
 19
 20#define GPIO_RX_DAT	0x0
 21#define GPIO_TX_SET	0x8
 22#define GPIO_TX_CLR	0x10
 23#define GPIO_CONST	0x90
 24#define  GPIO_CONST_GPIOS_MASK 0xff
 25#define GPIO_BIT_CFG	0x400
 26#define  GPIO_BIT_CFG_TX_OE		BIT(0)
 27#define  GPIO_BIT_CFG_PIN_XOR		BIT(1)
 28#define  GPIO_BIT_CFG_INT_EN		BIT(2)
 29#define  GPIO_BIT_CFG_INT_TYPE		BIT(3)
 30#define  GPIO_BIT_CFG_FIL_MASK		GENMASK(11, 4)
 31#define  GPIO_BIT_CFG_FIL_CNT_SHIFT	4
 32#define  GPIO_BIT_CFG_FIL_SEL_SHIFT	8
 33#define  GPIO_BIT_CFG_TX_OD		BIT(12)
 34#define  GPIO_BIT_CFG_PIN_SEL_MASK	GENMASK(25, 16)
 35#define GPIO_INTR	0x800
 36#define  GPIO_INTR_INTR			BIT(0)
 37#define  GPIO_INTR_INTR_W1S		BIT(1)
 38#define  GPIO_INTR_ENA_W1C		BIT(2)
 39#define  GPIO_INTR_ENA_W1S		BIT(3)
 40#define GPIO_2ND_BANK	0x1400
 41
 42#define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \
 43			     (9u << GPIO_BIT_CFG_FIL_CNT_SHIFT))
 44
 45struct thunderx_gpio;
 46
 47struct thunderx_line {
 48	struct thunderx_gpio	*txgpio;
 49	unsigned int		line;
 50	unsigned int		fil_bits;
 51};
 52
 53struct thunderx_gpio {
 54	struct gpio_chip	chip;
 55	u8 __iomem		*register_base;
 56	struct msix_entry	*msix_entries;	/* per line MSI-X */
 57	struct thunderx_line	*line_entries;	/* per line irq info */
 58	raw_spinlock_t		lock;
 59	unsigned long		invert_mask[2];
 60	unsigned long		od_mask[2];
 61	int			base_msi;
 62};
 63
 64static unsigned int bit_cfg_reg(unsigned int line)
 65{
 66	return 8 * line + GPIO_BIT_CFG;
 67}
 68
 69static unsigned int intr_reg(unsigned int line)
 70{
 71	return 8 * line + GPIO_INTR;
 72}
 73
 74static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio,
 75					 unsigned int line)
 76{
 77	u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
 78
 79	return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0;
 80}
 81
 82/*
 83 * Check (and WARN) that the pin is available for GPIO.  We will not
 84 * allow modification of the state of non-GPIO pins from this driver.
 85 */
 86static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio,
 87				  unsigned int line)
 88{
 89	bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line);
 90
 91	WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line);
 92
 93	return rv;
 94}
 95
 96static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line)
 97{
 98	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
 99
100	return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO;
101}
102
103static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line)
104{
105	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
106
107	if (!thunderx_gpio_is_gpio(txgpio, line))
108		return -EIO;
109
110	raw_spin_lock(&txgpio->lock);
111	clear_bit(line, txgpio->invert_mask);
112	clear_bit(line, txgpio->od_mask);
113	writeq(txgpio->line_entries[line].fil_bits,
114	       txgpio->register_base + bit_cfg_reg(line));
115	raw_spin_unlock(&txgpio->lock);
116	return 0;
117}
118
119static int thunderx_gpio_set(struct gpio_chip *chip, unsigned int line,
120			     int value)
121{
122	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
123	int bank = line / 64;
124	int bank_bit = line % 64;
125
126	void __iomem *reg = txgpio->register_base +
127		(bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR);
128
129	writeq(BIT_ULL(bank_bit), reg);
130
131	return 0;
132}
133
134static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line,
135				 int value)
136{
137	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
138	u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE;
139
140	if (!thunderx_gpio_is_gpio(txgpio, line))
141		return -EIO;
142
143	raw_spin_lock(&txgpio->lock);
144
145	thunderx_gpio_set(chip, line, value);
146
147	if (test_bit(line, txgpio->invert_mask))
148		bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
149
150	if (test_bit(line, txgpio->od_mask))
151		bit_cfg |= GPIO_BIT_CFG_TX_OD;
152
153	writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
154
155	raw_spin_unlock(&txgpio->lock);
156	return 0;
157}
158
159static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line)
160{
161	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
162	u64 bit_cfg;
163
164	if (!thunderx_gpio_is_gpio_nowarn(txgpio, line))
165		/*
166		 * Say it is input for now to avoid WARNing on
167		 * gpiochip_add_data().  We will WARN if someone
168		 * requests it or tries to use it.
169		 */
170		return 1;
171
172	bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
173
174	if (bit_cfg & GPIO_BIT_CFG_TX_OE)
175		return GPIO_LINE_DIRECTION_OUT;
176
177	return GPIO_LINE_DIRECTION_IN;
178}
179
180static int thunderx_gpio_set_config(struct gpio_chip *chip,
181				    unsigned int line,
182				    unsigned long cfg)
183{
184	bool orig_invert, orig_od, orig_dat, new_invert, new_od;
185	u32 arg, sel;
186	u64 bit_cfg;
187	int bank = line / 64;
188	int bank_bit = line % 64;
189	int ret = -ENOTSUPP;
190	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
191	void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;
192
193	if (!thunderx_gpio_is_gpio(txgpio, line))
194		return -EIO;
195
196	raw_spin_lock(&txgpio->lock);
197	orig_invert = test_bit(line, txgpio->invert_mask);
198	new_invert  = orig_invert;
199	orig_od = test_bit(line, txgpio->od_mask);
200	new_od = orig_od;
201	orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert;
202	bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
203	switch (pinconf_to_config_param(cfg)) {
204	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
205		/*
206		 * Weird, setting open-drain mode causes signal
207		 * inversion.  Note this so we can compensate in the
208		 * dir_out function.
209		 */
210		set_bit(line, txgpio->invert_mask);
211		new_invert  = true;
212		set_bit(line, txgpio->od_mask);
213		new_od = true;
214		ret = 0;
215		break;
216	case PIN_CONFIG_DRIVE_PUSH_PULL:
217		clear_bit(line, txgpio->invert_mask);
218		new_invert  = false;
219		clear_bit(line, txgpio->od_mask);
220		new_od  = false;
221		ret = 0;
222		break;
223	case PIN_CONFIG_INPUT_DEBOUNCE:
224		arg = pinconf_to_config_argument(cfg);
225		if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */
226			ret = -EINVAL;
227			break;
228		}
229		arg *= 400; /* scale to 2.5nS clocks. */
230		sel = 0;
231		while (arg > 15) {
232			sel++;
233			arg++; /* always round up */
234			arg >>= 1;
235		}
236		txgpio->line_entries[line].fil_bits =
237			(sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) |
238			(arg << GPIO_BIT_CFG_FIL_CNT_SHIFT);
239		bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK;
240		bit_cfg |= txgpio->line_entries[line].fil_bits;
241		writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
242		ret = 0;
243		break;
244	default:
245		break;
246	}
247	raw_spin_unlock(&txgpio->lock);
248
249	/*
250	 * If currently output and OPEN_DRAIN changed, install the new
251	 * settings
252	 */
253	if ((new_invert != orig_invert || new_od != orig_od) &&
254	    (bit_cfg & GPIO_BIT_CFG_TX_OE))
255		ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert);
256
257	return ret;
258}
259
260static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line)
261{
262	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
263	int bank = line / 64;
264	int bank_bit = line % 64;
265	u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);
266	u64 masked_bits = read_bits & BIT_ULL(bank_bit);
267
268	if (test_bit(line, txgpio->invert_mask))
269		return masked_bits == 0;
270	else
271		return masked_bits != 0;
272}
273
274static int thunderx_gpio_set_multiple(struct gpio_chip *chip,
275				      unsigned long *mask,
276				      unsigned long *bits)
277{
278	int bank;
279	u64 set_bits, clear_bits;
280	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
281
282	for (bank = 0; bank <= chip->ngpio / 64; bank++) {
283		set_bits = bits[bank] & mask[bank];
284		clear_bits = ~bits[bank] & mask[bank];
285		writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
286		writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);
287	}
288
289	return 0;
290}
291
292static void thunderx_gpio_irq_ack(struct irq_data *d)
293{
294	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
295	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
296
297	writeq(GPIO_INTR_INTR,
298	       txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
299}
300
301static void thunderx_gpio_irq_mask(struct irq_data *d)
302{
303	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
304	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
305
306	writeq(GPIO_INTR_ENA_W1C,
307	       txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
308}
309
310static void thunderx_gpio_irq_mask_ack(struct irq_data *d)
311{
312	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
313	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
314
315	writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR,
316	       txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
317}
318
319static void thunderx_gpio_irq_unmask(struct irq_data *d)
320{
321	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
322	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
323
324	writeq(GPIO_INTR_ENA_W1S,
325	       txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
326}
327
328static int thunderx_gpio_irq_set_type(struct irq_data *d,
329				      unsigned int flow_type)
330{
331	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
332	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
333	struct thunderx_line *txline =
334		&txgpio->line_entries[irqd_to_hwirq(d)];
335	u64 bit_cfg;
336
337	irqd_set_trigger_type(d, flow_type);
338
339	bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN;
340
341	if (flow_type & IRQ_TYPE_EDGE_BOTH) {
342		irq_set_handler_locked(d, handle_fasteoi_ack_irq);
343		bit_cfg |= GPIO_BIT_CFG_INT_TYPE;
344	} else {
345		irq_set_handler_locked(d, handle_fasteoi_mask_irq);
346	}
347
348	raw_spin_lock(&txgpio->lock);
349	if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) {
350		bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
351		set_bit(txline->line, txgpio->invert_mask);
352	} else {
353		clear_bit(txline->line, txgpio->invert_mask);
354	}
355	clear_bit(txline->line, txgpio->od_mask);
356	writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
357	raw_spin_unlock(&txgpio->lock);
358
359	return IRQ_SET_MASK_OK;
360}
361
362static void thunderx_gpio_irq_enable(struct irq_data *d)
363{
364	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
365
366	gpiochip_enable_irq(gc, irqd_to_hwirq(d));
367	irq_chip_enable_parent(d);
368	thunderx_gpio_irq_unmask(d);
369}
370
371static void thunderx_gpio_irq_disable(struct irq_data *d)
372{
373	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
374
375	thunderx_gpio_irq_mask(d);
376	irq_chip_disable_parent(d);
377	gpiochip_disable_irq(gc, irqd_to_hwirq(d));
378}
379
380/*
381 * Interrupts are chained from underlying MSI-X vectors.  We have
382 * these irq_chip functions to be able to handle level triggering
383 * semantics and other acknowledgment tasks associated with the GPIO
384 * mechanism.
385 */
386static const struct irq_chip thunderx_gpio_irq_chip = {
387	.name			= "GPIO",
388	.irq_enable		= thunderx_gpio_irq_enable,
389	.irq_disable		= thunderx_gpio_irq_disable,
390	.irq_ack		= thunderx_gpio_irq_ack,
391	.irq_mask		= thunderx_gpio_irq_mask,
392	.irq_mask_ack		= thunderx_gpio_irq_mask_ack,
393	.irq_unmask		= thunderx_gpio_irq_unmask,
394	.irq_eoi		= irq_chip_eoi_parent,
395	.irq_set_affinity	= irq_chip_set_affinity_parent,
396	.irq_set_type		= thunderx_gpio_irq_set_type,
397	.flags			= IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
398	GPIOCHIP_IRQ_RESOURCE_HELPERS,
399};
400
401static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
402					       unsigned int child,
403					       unsigned int child_type,
404					       unsigned int *parent,
405					       unsigned int *parent_type)
406{
407	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
408	struct irq_data *irqd;
409	unsigned int irq;
410
411	irq = txgpio->msix_entries[child].vector;
412	irqd = irq_domain_get_irq_data(gc->irq.parent_domain, irq);
413	if (!irqd)
414		return -EINVAL;
415	*parent = irqd_to_hwirq(irqd);
416	*parent_type = IRQ_TYPE_LEVEL_HIGH;
417	return 0;
418}
419
420static int thunderx_gpio_populate_parent_alloc_info(struct gpio_chip *chip,
421						    union gpio_irq_fwspec *gfwspec,
422						    unsigned int parent_hwirq,
423						    unsigned int parent_type)
424{
425	msi_alloc_info_t *info = &gfwspec->msiinfo;
426
427	info->hwirq = parent_hwirq;
428	return 0;
429}
430
431static int thunderx_gpio_probe(struct pci_dev *pdev,
432			       const struct pci_device_id *id)
433{
434	void __iomem * const *tbl;
435	struct device *dev = &pdev->dev;
436	struct thunderx_gpio *txgpio;
437	struct gpio_chip *chip;
438	struct gpio_irq_chip *girq;
439	int ngpio, i;
440	int err = 0;
441
442	txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL);
443	if (!txgpio)
444		return -ENOMEM;
445
446	raw_spin_lock_init(&txgpio->lock);
447	chip = &txgpio->chip;
448
449	pci_set_drvdata(pdev, txgpio);
450
451	err = pcim_enable_device(pdev);
452	if (err) {
453		dev_err(dev, "Failed to enable PCI device: err %d\n", err);
454		goto out;
455	}
456
457	err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME);
458	if (err) {
459		dev_err(dev, "Failed to iomap PCI device: err %d\n", err);
460		goto out;
461	}
462
463	tbl = pcim_iomap_table(pdev);
464	txgpio->register_base = tbl[0];
465	if (!txgpio->register_base) {
466		dev_err(dev, "Cannot map PCI resource\n");
467		err = -ENOMEM;
468		goto out;
469	}
470
471	if (pdev->subsystem_device == 0xa10a) {
472		/* CN88XX has no GPIO_CONST register*/
473		ngpio = 50;
474		txgpio->base_msi = 48;
475	} else {
476		u64 c = readq(txgpio->register_base + GPIO_CONST);
477
478		ngpio = c & GPIO_CONST_GPIOS_MASK;
479		txgpio->base_msi = (c >> 8) & 0xff;
480	}
481
482	txgpio->msix_entries = devm_kcalloc(dev,
483					    ngpio, sizeof(struct msix_entry),
484					    GFP_KERNEL);
485	if (!txgpio->msix_entries) {
486		err = -ENOMEM;
487		goto out;
488	}
489
490	txgpio->line_entries = devm_kcalloc(dev,
491					    ngpio,
492					    sizeof(struct thunderx_line),
493					    GFP_KERNEL);
494	if (!txgpio->line_entries) {
495		err = -ENOMEM;
496		goto out;
497	}
498
499	for (i = 0; i < ngpio; i++) {
500		u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));
501
502		txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i);
503		txgpio->line_entries[i].line = i;
504		txgpio->line_entries[i].txgpio = txgpio;
505		/*
506		 * If something has already programmed the pin, use
507		 * the existing glitch filter settings, otherwise go
508		 * to 400nS.
509		 */
510		txgpio->line_entries[i].fil_bits = bit_cfg ?
511			(bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS;
512
513		if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD))
514			set_bit(i, txgpio->od_mask);
515		if (bit_cfg & GPIO_BIT_CFG_PIN_XOR)
516			set_bit(i, txgpio->invert_mask);
517	}
518
519
520	/* Enable all MSI-X for interrupts on all possible lines. */
521	err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio);
522	if (err < 0)
523		goto out;
524
525	chip->label = KBUILD_MODNAME;
526	chip->parent = dev;
527	chip->owner = THIS_MODULE;
528	chip->request = thunderx_gpio_request;
529	chip->base = -1; /* System allocated */
530	chip->can_sleep = false;
531	chip->ngpio = ngpio;
532	chip->get_direction = thunderx_gpio_get_direction;
533	chip->direction_input = thunderx_gpio_dir_in;
534	chip->get = thunderx_gpio_get;
535	chip->direction_output = thunderx_gpio_dir_out;
536	chip->set = thunderx_gpio_set;
537	chip->set_multiple = thunderx_gpio_set_multiple;
538	chip->set_config = thunderx_gpio_set_config;
539	girq = &chip->irq;
540	gpio_irq_chip_set_chip(girq, &thunderx_gpio_irq_chip);
541	girq->fwnode = dev_fwnode(dev);
542	girq->parent_domain =
543		irq_get_irq_data(txgpio->msix_entries[0].vector)->domain;
544	girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq;
545	girq->populate_parent_alloc_arg = thunderx_gpio_populate_parent_alloc_info;
546	girq->handler = handle_bad_irq;
547	girq->default_type = IRQ_TYPE_NONE;
548
549	err = devm_gpiochip_add_data(dev, chip, txgpio);
550	if (err)
551		goto out;
552
553	/* Push on irq_data and the domain for each line. */
554	for (i = 0; i < ngpio; i++) {
555		struct irq_fwspec fwspec;
556
557		fwspec.fwnode = dev_fwnode(dev);
558		fwspec.param_count = 2;
559		fwspec.param[0] = i;
560		fwspec.param[1] = IRQ_TYPE_NONE;
561		err = irq_domain_push_irq(girq->domain,
562					  txgpio->msix_entries[i].vector,
563					  &fwspec);
564		if (err < 0)
565			dev_err(dev, "irq_domain_push_irq: %d\n", err);
566	}
567
568	dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n",
569		 ngpio, chip->base);
570	return 0;
571out:
572	pci_set_drvdata(pdev, NULL);
573	return err;
574}
575
576static void thunderx_gpio_remove(struct pci_dev *pdev)
577{
578	int i;
579	struct thunderx_gpio *txgpio = pci_get_drvdata(pdev);
580
581	for (i = 0; i < txgpio->chip.ngpio; i++)
582		irq_domain_pop_irq(txgpio->chip.irq.domain,
583				   txgpio->msix_entries[i].vector);
584
585	irq_domain_remove(txgpio->chip.irq.domain);
586
587	pci_set_drvdata(pdev, NULL);
588}
589
590static const struct pci_device_id thunderx_gpio_id_table[] = {
591	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) },
592	{ 0, }	/* end of table */
593};
594
595MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table);
596
597static struct pci_driver thunderx_gpio_driver = {
598	.name = KBUILD_MODNAME,
599	.id_table = thunderx_gpio_id_table,
600	.probe = thunderx_gpio_probe,
601	.remove = thunderx_gpio_remove,
602};
603
604module_pci_driver(thunderx_gpio_driver);
605
606MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver");
607MODULE_LICENSE("GPL");