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gpio-tegra186.c
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linux-6.19.14/drivers/gpio/gpio-tegra186.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2016-2025 NVIDIA Corporation 4 * 5 * Author: Thierry Reding <treding@nvidia.com> 6 * Dipen Patel <dpatel@nvidia.com> 7 */ 8 9#include <linux/gpio/driver.h> 10#include <linux/hte.h> 11#include <linux/interrupt.h> 12#include <linux/irq.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/platform_device.h> 16#include <linux/property.h> 17#include <linux/seq_file.h> 18 19#include <dt-bindings/gpio/tegra186-gpio.h> 20#include <dt-bindings/gpio/tegra194-gpio.h> 21#include <dt-bindings/gpio/tegra234-gpio.h> 22#include <dt-bindings/gpio/tegra241-gpio.h> 23#include <dt-bindings/gpio/tegra256-gpio.h> 24 25/* security registers */ 26#define TEGRA186_GPIO_CTL_SCR 0x0c 27#define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28) 28#define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27) 29 30#define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4) 31 32#define TEGRA186_GPIO_VM 0x00 33#define TEGRA186_GPIO_VM_RW_MASK 0x03 34#define TEGRA186_GPIO_SCR 0x04 35#define TEGRA186_GPIO_SCR_PIN_SIZE 0x08 36#define TEGRA186_GPIO_SCR_PORT_SIZE 0x40 37#define TEGRA186_GPIO_SCR_SEC_WEN BIT(28) 38#define TEGRA186_GPIO_SCR_SEC_REN BIT(27) 39#define TEGRA186_GPIO_SCR_SEC_G1W BIT(9) 40#define TEGRA186_GPIO_SCR_SEC_G1R BIT(1) 41 42/* control registers */ 43#define TEGRA186_GPIO_ENABLE_CONFIG 0x00 44#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 45#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 46#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) 47#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) 48#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) 49#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) 50#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) 51#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) 52#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5) 53#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) 54#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7) 55 56#define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 57#define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) 58 59#define TEGRA186_GPIO_INPUT 0x08 60#define TEGRA186_GPIO_INPUT_HIGH BIT(0) 61 62#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 63#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 64 65#define TEGRA186_GPIO_OUTPUT_VALUE 0x10 66#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) 67 68#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 69 70#define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) 71 72/* Tegra410 GPIOs implemented by the COMPUTE GPIO controller */ 73#define TEGRA410_COMPUTE_GPIO_PORT_A 0 74#define TEGRA410_COMPUTE_GPIO_PORT_B 1 75#define TEGRA410_COMPUTE_GPIO_PORT_C 2 76#define TEGRA410_COMPUTE_GPIO_PORT_D 3 77#define TEGRA410_COMPUTE_GPIO_PORT_E 4 78 79/* Tegra410 GPIOs implemented by the SYSTEM GPIO controller */ 80#define TEGRA410_SYSTEM_GPIO_PORT_A 0 81#define TEGRA410_SYSTEM_GPIO_PORT_B 1 82#define TEGRA410_SYSTEM_GPIO_PORT_C 2 83#define TEGRA410_SYSTEM_GPIO_PORT_D 3 84#define TEGRA410_SYSTEM_GPIO_PORT_E 4 85#define TEGRA410_SYSTEM_GPIO_PORT_I 5 86#define TEGRA410_SYSTEM_GPIO_PORT_J 6 87#define TEGRA410_SYSTEM_GPIO_PORT_K 7 88#define TEGRA410_SYSTEM_GPIO_PORT_L 8 89#define TEGRA410_SYSTEM_GPIO_PORT_M 9 90#define TEGRA410_SYSTEM_GPIO_PORT_N 10 91#define TEGRA410_SYSTEM_GPIO_PORT_P 11 92#define TEGRA410_SYSTEM_GPIO_PORT_Q 12 93#define TEGRA410_SYSTEM_GPIO_PORT_R 13 94#define TEGRA410_SYSTEM_GPIO_PORT_V 14 95 96struct tegra_gpio_port { 97 const char *name; 98 unsigned int bank; 99 unsigned int port; 100 unsigned int pins; 101}; 102 103struct tegra186_pin_range { 104 unsigned int offset; 105 const char *group; 106}; 107 108struct tegra_gpio_soc { 109 const struct tegra_gpio_port *ports; 110 unsigned int num_ports; 111 const char *name; 112 const char *prefix; 113 unsigned int instance; 114 115 unsigned int num_irqs_per_bank; 116 117 const struct tegra186_pin_range *pin_ranges; 118 unsigned int num_pin_ranges; 119 const char *pinmux; 120 bool has_gte; 121 bool has_vm_support; 122}; 123 124struct tegra_gpio { 125 struct gpio_chip gpio; 126 unsigned int num_irq; 127 unsigned int *irq; 128 129 const struct tegra_gpio_soc *soc; 130 unsigned int num_irqs_per_bank; 131 unsigned int num_banks; 132 133 void __iomem *secure; 134 void __iomem *base; 135}; 136 137static const struct tegra_gpio_port * 138tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) 139{ 140 unsigned int start = 0, i; 141 142 for (i = 0; i < gpio->soc->num_ports; i++) { 143 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 144 145 if (*pin >= start && *pin < start + port->pins) { 146 *pin -= start; 147 return port; 148 } 149 150 start += port->pins; 151 } 152 153 return NULL; 154} 155 156static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, 157 unsigned int pin) 158{ 159 const struct tegra_gpio_port *port; 160 unsigned int offset; 161 162 port = tegra186_gpio_get_port(gpio, &pin); 163 if (!port) 164 return NULL; 165 166 offset = port->bank * 0x1000 + port->port * 0x200; 167 168 return gpio->base + offset + pin * 0x20; 169} 170 171static void __iomem *tegra186_gpio_get_secure_base(struct tegra_gpio *gpio, 172 unsigned int pin) 173{ 174 const struct tegra_gpio_port *port; 175 unsigned int offset; 176 177 port = tegra186_gpio_get_port(gpio, &pin); 178 if (!port) 179 return NULL; 180 181 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE; 182 183 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE; 184} 185 186static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned int pin) 187{ 188 void __iomem *secure; 189 u32 value; 190 191 secure = tegra186_gpio_get_secure_base(gpio, pin); 192 193 if (gpio->soc->has_vm_support) { 194 value = readl(secure + TEGRA186_GPIO_VM); 195 if ((value & TEGRA186_GPIO_VM_RW_MASK) != TEGRA186_GPIO_VM_RW_MASK) 196 return false; 197 } 198 199 value = __raw_readl(secure + TEGRA186_GPIO_SCR); 200 201 /* 202 * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the 203 * registers for given GPIO pin. 204 * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying 205 * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given 206 * GPIO pin. 207 */ 208 209 if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 || 210 ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) && 211 ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 || 212 ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W)))) 213 return true; 214 215 return false; 216} 217 218static int tegra186_init_valid_mask(struct gpio_chip *chip, 219 unsigned long *valid_mask, unsigned int ngpios) 220{ 221 struct tegra_gpio *gpio = gpiochip_get_data(chip); 222 unsigned int j; 223 224 for (j = 0; j < ngpios; j++) { 225 if (!tegra186_gpio_is_accessible(gpio, j)) 226 clear_bit(j, valid_mask); 227 } 228 return 0; 229} 230 231static int tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, 232 int level) 233{ 234 struct tegra_gpio *gpio = gpiochip_get_data(chip); 235 void __iomem *base; 236 u32 value; 237 238 base = tegra186_gpio_get_base(gpio, offset); 239 if (WARN_ON(base == NULL)) 240 return -ENODEV; 241 242 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 243 if (level == 0) 244 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 245 else 246 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 247 248 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); 249 250 return 0; 251} 252 253static int tegra186_gpio_get_direction(struct gpio_chip *chip, 254 unsigned int offset) 255{ 256 struct tegra_gpio *gpio = gpiochip_get_data(chip); 257 void __iomem *base; 258 u32 value; 259 260 base = tegra186_gpio_get_base(gpio, offset); 261 if (WARN_ON(base == NULL)) 262 return -ENODEV; 263 264 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 265 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 266 return GPIO_LINE_DIRECTION_OUT; 267 268 return GPIO_LINE_DIRECTION_IN; 269} 270 271static int tegra186_gpio_direction_input(struct gpio_chip *chip, 272 unsigned int offset) 273{ 274 struct tegra_gpio *gpio = gpiochip_get_data(chip); 275 void __iomem *base; 276 u32 value; 277 278 base = tegra186_gpio_get_base(gpio, offset); 279 if (WARN_ON(base == NULL)) 280 return -ENODEV; 281 282 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 283 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 284 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 285 286 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 287 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 288 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; 289 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 290 291 return 0; 292} 293 294static int tegra186_gpio_direction_output(struct gpio_chip *chip, 295 unsigned int offset, int level) 296{ 297 struct tegra_gpio *gpio = gpiochip_get_data(chip); 298 void __iomem *base; 299 u32 value; 300 int ret; 301 302 /* configure output level first */ 303 ret = tegra186_gpio_set(chip, offset, level); 304 if (ret) 305 return ret; 306 307 base = tegra186_gpio_get_base(gpio, offset); 308 if (WARN_ON(base == NULL)) 309 return -EINVAL; 310 311 /* set the direction */ 312 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 313 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 314 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 315 316 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 317 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 318 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; 319 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 320 321 return 0; 322} 323 324#define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS) 325 326static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset, 327 unsigned long flags) 328{ 329 struct tegra_gpio *gpio; 330 void __iomem *base; 331 int value; 332 333 if (!gc) 334 return -EINVAL; 335 336 gpio = gpiochip_get_data(gc); 337 if (!gpio) 338 return -ENODEV; 339 340 base = tegra186_gpio_get_base(gpio, offset); 341 if (WARN_ON(base == NULL)) 342 return -EINVAL; 343 344 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 345 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; 346 347 if (flags == HTE_BOTH_EDGES) { 348 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 349 } else if (flags == HTE_RISING_EDGE_TS) { 350 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 351 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 352 } else if (flags == HTE_FALLING_EDGE_TS) { 353 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 354 } 355 356 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 357 358 return 0; 359} 360 361static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset, 362 unsigned long flags) 363{ 364 struct tegra_gpio *gpio; 365 void __iomem *base; 366 int value; 367 368 if (!gc) 369 return -EINVAL; 370 371 gpio = gpiochip_get_data(gc); 372 if (!gpio) 373 return -ENODEV; 374 375 base = tegra186_gpio_get_base(gpio, offset); 376 if (WARN_ON(base == NULL)) 377 return -EINVAL; 378 379 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 380 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; 381 if (flags == HTE_BOTH_EDGES) { 382 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 383 } else if (flags == HTE_RISING_EDGE_TS) { 384 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 385 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 386 } else if (flags == HTE_FALLING_EDGE_TS) { 387 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 388 } 389 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 390 391 return 0; 392} 393 394static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) 395{ 396 struct tegra_gpio *gpio = gpiochip_get_data(chip); 397 void __iomem *base; 398 u32 value; 399 400 base = tegra186_gpio_get_base(gpio, offset); 401 if (WARN_ON(base == NULL)) 402 return -ENODEV; 403 404 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 405 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 406 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 407 else 408 value = readl(base + TEGRA186_GPIO_INPUT); 409 410 return value & BIT(0); 411} 412 413static int tegra186_gpio_set_config(struct gpio_chip *chip, 414 unsigned int offset, 415 unsigned long config) 416{ 417 struct tegra_gpio *gpio = gpiochip_get_data(chip); 418 u32 debounce, value; 419 void __iomem *base; 420 421 base = tegra186_gpio_get_base(gpio, offset); 422 if (base == NULL) 423 return -ENXIO; 424 425 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 426 return -ENOTSUPP; 427 428 debounce = pinconf_to_config_argument(config); 429 430 /* 431 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce 432 * time. 433 */ 434 if (debounce > 255000) 435 return -EINVAL; 436 437 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC); 438 439 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce); 440 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); 441 442 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 443 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE; 444 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 445 446 return 0; 447} 448 449static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip) 450{ 451 struct tegra_gpio *gpio = gpiochip_get_data(chip); 452 struct pinctrl_dev *pctldev; 453 struct device_node *np; 454 unsigned int i, j; 455 int err; 456 457 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) 458 return 0; 459 460 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); 461 if (!np) 462 return -ENODEV; 463 464 pctldev = of_pinctrl_get(np); 465 of_node_put(np); 466 if (!pctldev) 467 return -EPROBE_DEFER; 468 469 for (i = 0; i < gpio->soc->num_pin_ranges; i++) { 470 unsigned int pin = gpio->soc->pin_ranges[i].offset, port; 471 const char *group = gpio->soc->pin_ranges[i].group; 472 473 port = pin / 8; 474 pin = pin % 8; 475 476 if (port >= gpio->soc->num_ports) { 477 dev_warn(chip->parent, "invalid port %u for %s\n", 478 port, group); 479 continue; 480 } 481 482 for (j = 0; j < port; j++) 483 pin += gpio->soc->ports[j].pins; 484 485 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group); 486 if (err < 0) 487 return err; 488 } 489 490 return 0; 491} 492 493static int tegra186_gpio_of_xlate(struct gpio_chip *chip, 494 const struct of_phandle_args *spec, 495 u32 *flags) 496{ 497 struct tegra_gpio *gpio = gpiochip_get_data(chip); 498 unsigned int port, pin, i, offset = 0; 499 500 if (WARN_ON(chip->of_gpio_n_cells < 2)) 501 return -EINVAL; 502 503 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) 504 return -EINVAL; 505 506 port = spec->args[0] / 8; 507 pin = spec->args[0] % 8; 508 509 if (port >= gpio->soc->num_ports) { 510 dev_err(chip->parent, "invalid port number: %u\n", port); 511 return -EINVAL; 512 } 513 514 for (i = 0; i < port; i++) 515 offset += gpio->soc->ports[i].pins; 516 517 if (flags) 518 *flags = spec->args[1]; 519 520 return offset + pin; 521} 522 523#define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio) 524 525static void tegra186_irq_ack(struct irq_data *data) 526{ 527 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 528 struct tegra_gpio *gpio = to_tegra_gpio(gc); 529 void __iomem *base; 530 531 base = tegra186_gpio_get_base(gpio, data->hwirq); 532 if (WARN_ON(base == NULL)) 533 return; 534 535 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); 536} 537 538static void tegra186_irq_mask(struct irq_data *data) 539{ 540 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 541 struct tegra_gpio *gpio = to_tegra_gpio(gc); 542 void __iomem *base; 543 u32 value; 544 545 base = tegra186_gpio_get_base(gpio, data->hwirq); 546 if (WARN_ON(base == NULL)) 547 return; 548 549 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 550 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 551 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 552 553 gpiochip_disable_irq(&gpio->gpio, data->hwirq); 554} 555 556static void tegra186_irq_unmask(struct irq_data *data) 557{ 558 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 559 struct tegra_gpio *gpio = to_tegra_gpio(gc); 560 void __iomem *base; 561 u32 value; 562 563 base = tegra186_gpio_get_base(gpio, data->hwirq); 564 if (WARN_ON(base == NULL)) 565 return; 566 567 gpiochip_enable_irq(&gpio->gpio, data->hwirq); 568 569 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 570 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 571 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 572} 573 574static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) 575{ 576 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 577 struct tegra_gpio *gpio = to_tegra_gpio(gc); 578 void __iomem *base; 579 u32 value; 580 581 base = tegra186_gpio_get_base(gpio, data->hwirq); 582 if (WARN_ON(base == NULL)) 583 return -ENODEV; 584 585 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 586 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; 587 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 588 589 switch (type & IRQ_TYPE_SENSE_MASK) { 590 case IRQ_TYPE_NONE: 591 break; 592 593 case IRQ_TYPE_EDGE_RISING: 594 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 595 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 596 break; 597 598 case IRQ_TYPE_EDGE_FALLING: 599 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 600 break; 601 602 case IRQ_TYPE_EDGE_BOTH: 603 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 604 break; 605 606 case IRQ_TYPE_LEVEL_HIGH: 607 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 608 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 609 break; 610 611 case IRQ_TYPE_LEVEL_LOW: 612 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 613 break; 614 615 default: 616 return -EINVAL; 617 } 618 619 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 620 621 if ((type & IRQ_TYPE_EDGE_BOTH) == 0) 622 irq_set_handler_locked(data, handle_level_irq); 623 else 624 irq_set_handler_locked(data, handle_edge_irq); 625 626 if (data->parent_data) 627 return irq_chip_set_type_parent(data, type); 628 629 return 0; 630} 631 632static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on) 633{ 634 if (data->parent_data) 635 return irq_chip_set_wake_parent(data, on); 636 637 return 0; 638} 639 640static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p) 641{ 642 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 643 644 seq_puts(p, dev_name(gc->parent)); 645} 646 647static const struct irq_chip tegra186_gpio_irq_chip = { 648 .irq_ack = tegra186_irq_ack, 649 .irq_mask = tegra186_irq_mask, 650 .irq_unmask = tegra186_irq_unmask, 651 .irq_set_type = tegra186_irq_set_type, 652 .irq_set_wake = tegra186_irq_set_wake, 653 .irq_print_chip = tegra186_irq_print_chip, 654 .flags = IRQCHIP_IMMUTABLE, 655 GPIOCHIP_IRQ_RESOURCE_HELPERS, 656}; 657 658static void tegra186_gpio_irq(struct irq_desc *desc) 659{ 660 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); 661 struct irq_domain *domain = gpio->gpio.irq.domain; 662 struct irq_chip *chip = irq_desc_get_chip(desc); 663 unsigned int parent = irq_desc_get_irq(desc); 664 unsigned int i, j, offset = 0; 665 666 chained_irq_enter(chip, desc); 667 668 for (i = 0; i < gpio->soc->num_ports; i++) { 669 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 670 unsigned int pin; 671 unsigned long value; 672 void __iomem *base; 673 674 base = gpio->base + port->bank * 0x1000 + port->port * 0x200; 675 676 /* skip ports that are not associated with this bank */ 677 for (j = 0; j < gpio->num_irqs_per_bank; j++) { 678 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j]) 679 break; 680 } 681 682 if (j == gpio->num_irqs_per_bank) 683 goto skip; 684 685 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); 686 687 for_each_set_bit(pin, &value, port->pins) { 688 int ret = generic_handle_domain_irq(domain, offset + pin); 689 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin); 690 } 691 692skip: 693 offset += port->pins; 694 } 695 696 chained_irq_exit(chip, desc); 697} 698 699static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, 700 struct irq_fwspec *fwspec, 701 unsigned long *hwirq, 702 unsigned int *type) 703{ 704 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); 705 unsigned int port, pin, i, offset = 0; 706 707 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) 708 return -EINVAL; 709 710 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) 711 return -EINVAL; 712 713 port = fwspec->param[0] / 8; 714 pin = fwspec->param[0] % 8; 715 716 if (port >= gpio->soc->num_ports) 717 return -EINVAL; 718 719 for (i = 0; i < port; i++) 720 offset += gpio->soc->ports[i].pins; 721 722 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 723 *hwirq = offset + pin; 724 725 return 0; 726} 727 728static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip, 729 union gpio_irq_fwspec *gfwspec, 730 unsigned int parent_hwirq, 731 unsigned int parent_type) 732{ 733 struct tegra_gpio *gpio = gpiochip_get_data(chip); 734 struct irq_fwspec *fwspec = &gfwspec->fwspec; 735 736 fwspec->fwnode = chip->irq.parent_domain->fwnode; 737 fwspec->param_count = 3; 738 fwspec->param[0] = gpio->soc->instance; 739 fwspec->param[1] = parent_hwirq; 740 fwspec->param[2] = parent_type; 741 742 return 0; 743} 744 745static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 746 unsigned int hwirq, 747 unsigned int type, 748 unsigned int *parent_hwirq, 749 unsigned int *parent_type) 750{ 751 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); 752 *parent_type = type; 753 754 return 0; 755} 756 757static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip, 758 unsigned int offset) 759{ 760 struct tegra_gpio *gpio = gpiochip_get_data(chip); 761 unsigned int i; 762 763 for (i = 0; i < gpio->soc->num_ports; i++) { 764 if (offset < gpio->soc->ports[i].pins) 765 break; 766 767 offset -= gpio->soc->ports[i].pins; 768 } 769 770 return offset + i * 8; 771} 772 773static const struct of_device_id tegra186_pmc_of_match[] = { 774 { .compatible = "nvidia,tegra186-pmc" }, 775 { .compatible = "nvidia,tegra194-pmc" }, 776 { .compatible = "nvidia,tegra234-pmc" }, 777 { /* sentinel */ } 778}; 779 780static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) 781{ 782 struct device *dev = gpio->gpio.parent; 783 unsigned int i; 784 u32 value; 785 786 for (i = 0; i < gpio->soc->num_ports; i++) { 787 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 788 unsigned int offset, p = port->port; 789 void __iomem *base; 790 791 base = gpio->secure + port->bank * 0x1000 + 0x800; 792 793 value = readl(base + TEGRA186_GPIO_CTL_SCR); 794 795 /* 796 * For controllers that haven't been locked down yet, make 797 * sure to program the default interrupt route mapping. 798 */ 799 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && 800 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { 801 /* 802 * On Tegra194 and later, each pin can be routed to one or more 803 * interrupts. 804 */ 805 dev_dbg(dev, "programming default interrupt routing for port %s\n", 806 port->name); 807 808 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0); 809 810 /* 811 * By default we only want to route GPIO pins to IRQ 0. This works 812 * only under the assumption that we're running as the host kernel 813 * and hence all GPIO pins are owned by Linux. 814 * 815 * For cases where Linux is the guest OS, the hypervisor will have 816 * to configure the interrupt routing and pass only the valid 817 * interrupts via device tree. 818 */ 819 value = readl(base + offset); 820 value = BIT(port->pins) - 1; 821 writel(value, base + offset); 822 } 823 } 824} 825 826static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio) 827{ 828 struct device *dev = gpio->gpio.parent; 829 830 if (gpio->num_irq > gpio->num_banks) { 831 if (gpio->num_irq % gpio->num_banks != 0) 832 goto error; 833 } 834 835 if (gpio->num_irq < gpio->num_banks) 836 goto error; 837 838 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; 839 840 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank) 841 goto error; 842 843 return 0; 844 845error: 846 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n", 847 gpio->num_irq, gpio->num_banks); 848 return -EINVAL; 849} 850 851static int tegra186_gpio_probe(struct platform_device *pdev) 852{ 853 unsigned int i, j, offset; 854 struct gpio_irq_chip *irq; 855 struct tegra_gpio *gpio; 856 struct device_node *np; 857 struct resource *res; 858 char **names; 859 int err; 860 861 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 862 if (!gpio) 863 return -ENOMEM; 864 865 gpio->soc = device_get_match_data(&pdev->dev); 866 gpio->gpio.label = gpio->soc->name; 867 gpio->gpio.parent = &pdev->dev; 868 869 /* count the number of banks in the controller */ 870 for (i = 0; i < gpio->soc->num_ports; i++) 871 if (gpio->soc->ports[i].bank > gpio->num_banks) 872 gpio->num_banks = gpio->soc->ports[i].bank; 873 874 gpio->num_banks++; 875 876 /* get register apertures */ 877 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "security"); 878 if (!res) 879 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 880 gpio->secure = devm_ioremap_resource(&pdev->dev, res); 881 if (IS_ERR(gpio->secure)) 882 return PTR_ERR(gpio->secure); 883 884 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio"); 885 if (!res) 886 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 887 gpio->base = devm_ioremap_resource(&pdev->dev, res); 888 if (IS_ERR(gpio->base)) 889 return PTR_ERR(gpio->base); 890 891 err = platform_irq_count(pdev); 892 if (err < 0) 893 return err; 894 895 gpio->num_irq = err; 896 897 err = tegra186_gpio_irqs_per_bank(gpio); 898 if (err < 0) 899 return err; 900 901 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), 902 GFP_KERNEL); 903 if (!gpio->irq) 904 return -ENOMEM; 905 906 for (i = 0; i < gpio->num_irq; i++) { 907 err = platform_get_irq(pdev, i); 908 if (err < 0) 909 return err; 910 911 gpio->irq[i] = err; 912 } 913 914 gpio->gpio.request = gpiochip_generic_request; 915 gpio->gpio.free = gpiochip_generic_free; 916 gpio->gpio.get_direction = tegra186_gpio_get_direction; 917 gpio->gpio.direction_input = tegra186_gpio_direction_input; 918 gpio->gpio.direction_output = tegra186_gpio_direction_output; 919 gpio->gpio.get = tegra186_gpio_get; 920 gpio->gpio.set = tegra186_gpio_set; 921 gpio->gpio.set_config = tegra186_gpio_set_config; 922 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; 923 gpio->gpio.init_valid_mask = tegra186_init_valid_mask; 924 if (gpio->soc->has_gte) { 925 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts; 926 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts; 927 } 928 929 gpio->gpio.base = -1; 930 931 for (i = 0; i < gpio->soc->num_ports; i++) 932 gpio->gpio.ngpio += gpio->soc->ports[i].pins; 933 934 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, 935 sizeof(*names), GFP_KERNEL); 936 if (!names) 937 return -ENOMEM; 938 939 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 940 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 941 char *name; 942 943 for (j = 0; j < port->pins; j++) { 944 if (gpio->soc->prefix) 945 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, "%s-P%s.%02x", 946 gpio->soc->prefix, port->name, j); 947 else 948 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, "P%s.%02x", 949 port->name, j); 950 if (!name) 951 return -ENOMEM; 952 953 names[offset + j] = name; 954 } 955 956 offset += port->pins; 957 } 958 959 gpio->gpio.names = (const char * const *)names; 960 961#if defined(CONFIG_OF_GPIO) 962 gpio->gpio.of_gpio_n_cells = 2; 963 gpio->gpio.of_xlate = tegra186_gpio_of_xlate; 964#endif /* CONFIG_OF_GPIO */ 965 966 irq = &gpio->gpio.irq; 967 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip); 968 irq->fwnode = dev_fwnode(&pdev->dev); 969 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; 970 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; 971 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; 972 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; 973 irq->handler = handle_simple_irq; 974 irq->default_type = IRQ_TYPE_NONE; 975 irq->parent_handler = tegra186_gpio_irq; 976 irq->parent_handler_data = gpio; 977 irq->num_parents = gpio->num_irq; 978 979 /* 980 * To simplify things, use a single interrupt per bank for now. Some 981 * chips support up to 8 interrupts per bank, which can be useful to 982 * distribute the load and decrease the processing latency for GPIOs 983 * but it also requires a more complicated interrupt routing than we 984 * currently program. 985 */ 986 if (gpio->num_irqs_per_bank > 1) { 987 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, 988 sizeof(*irq->parents), GFP_KERNEL); 989 if (!irq->parents) 990 return -ENOMEM; 991 992 for (i = 0; i < gpio->num_banks; i++) 993 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank]; 994 995 irq->num_parents = gpio->num_banks; 996 } else { 997 irq->num_parents = gpio->num_irq; 998 irq->parents = gpio->irq; 999 } 1000 1001 if (gpio->soc->num_irqs_per_bank > 1) 1002 tegra186_gpio_init_route_mapping(gpio); 1003 1004 np = of_find_matching_node(NULL, tegra186_pmc_of_match); 1005 if (np) { 1006 if (of_device_is_available(np)) { 1007 irq->parent_domain = irq_find_host(np); 1008 of_node_put(np); 1009 1010 if (!irq->parent_domain) 1011 return -EPROBE_DEFER; 1012 } else { 1013 of_node_put(np); 1014 } 1015 } 1016 1017 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, 1018 sizeof(*irq->map), GFP_KERNEL); 1019 if (!irq->map) 1020 return -ENOMEM; 1021 1022 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 1023 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 1024 1025 for (j = 0; j < port->pins; j++) 1026 irq->map[offset + j] = irq->parents[port->bank]; 1027 1028 offset += port->pins; 1029 } 1030 1031 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); 1032} 1033 1034#define TEGRA_GPIO_PORT(_prefix, _name, _bank, _port, _pins) \ 1035 [_prefix##_GPIO_PORT_##_name] = { \ 1036 .name = #_name, \ 1037 .bank = _bank, \ 1038 .port = _port, \ 1039 .pins = _pins, \ 1040 } 1041 1042#define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1043 TEGRA_GPIO_PORT(TEGRA186_MAIN, _name, _bank, _port, _pins) 1044 1045static const struct tegra_gpio_port tegra186_main_ports[] = { 1046 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7), 1047 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7), 1048 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7), 1049 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6), 1050 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8), 1051 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6), 1052 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6), 1053 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7), 1054 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8), 1055 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8), 1056 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1), 1057 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8), 1058 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6), 1059 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7), 1060 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4), 1061 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7), 1062 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6), 1063 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6), 1064 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4), 1065 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8), 1066 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7), 1067 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2), 1068 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4), 1069}; 1070 1071static const struct tegra_gpio_soc tegra186_main_soc = { 1072 .num_ports = ARRAY_SIZE(tegra186_main_ports), 1073 .ports = tegra186_main_ports, 1074 .name = "tegra186-gpio", 1075 .instance = 0, 1076 .num_irqs_per_bank = 1, 1077 .has_vm_support = false, 1078}; 1079 1080#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1081 TEGRA_GPIO_PORT(TEGRA186_AON, _name, _bank, _port, _pins) 1082 1083static const struct tegra_gpio_port tegra186_aon_ports[] = { 1084 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5), 1085 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6), 1086 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8), 1087 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8), 1088 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4), 1089 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8), 1090 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3), 1091 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5), 1092}; 1093 1094static const struct tegra_gpio_soc tegra186_aon_soc = { 1095 .num_ports = ARRAY_SIZE(tegra186_aon_ports), 1096 .ports = tegra186_aon_ports, 1097 .name = "tegra186-gpio-aon", 1098 .instance = 1, 1099 .num_irqs_per_bank = 1, 1100 .has_vm_support = false, 1101}; 1102 1103#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1104 TEGRA_GPIO_PORT(TEGRA194_MAIN, _name, _bank, _port, _pins) 1105 1106static const struct tegra_gpio_port tegra194_main_ports[] = { 1107 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8), 1108 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2), 1109 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8), 1110 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4), 1111 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8), 1112 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6), 1113 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8), 1114 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8), 1115 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5), 1116 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6), 1117 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8), 1118 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4), 1119 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8), 1120 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3), 1121 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6), 1122 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8), 1123 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8), 1124 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6), 1125 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8), 1126 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8), 1127 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1), 1128 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8), 1129 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2), 1130 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8), 1131 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8), 1132 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8), 1133 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2), 1134 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) 1135}; 1136 1137static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { 1138 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, 1139 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, 1140}; 1141 1142static const struct tegra_gpio_soc tegra194_main_soc = { 1143 .num_ports = ARRAY_SIZE(tegra194_main_ports), 1144 .ports = tegra194_main_ports, 1145 .name = "tegra194-gpio", 1146 .instance = 0, 1147 .num_irqs_per_bank = 8, 1148 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), 1149 .pin_ranges = tegra194_main_pin_ranges, 1150 .pinmux = "nvidia,tegra194-pinmux", 1151 .has_vm_support = true, 1152}; 1153 1154#define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1155 TEGRA_GPIO_PORT(TEGRA194_AON, _name, _bank, _port, _pins) 1156 1157static const struct tegra_gpio_port tegra194_aon_ports[] = { 1158 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8), 1159 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4), 1160 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8), 1161 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3), 1162 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7) 1163}; 1164 1165static const struct tegra_gpio_soc tegra194_aon_soc = { 1166 .num_ports = ARRAY_SIZE(tegra194_aon_ports), 1167 .ports = tegra194_aon_ports, 1168 .name = "tegra194-gpio-aon", 1169 .instance = 1, 1170 .num_irqs_per_bank = 8, 1171 .has_gte = true, 1172 .has_vm_support = false, 1173}; 1174 1175#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1176 TEGRA_GPIO_PORT(TEGRA234_MAIN, _name, _bank, _port, _pins) 1177 1178static const struct tegra_gpio_port tegra234_main_ports[] = { 1179 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8), 1180 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1), 1181 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8), 1182 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4), 1183 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8), 1184 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6), 1185 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8), 1186 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8), 1187 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7), 1188 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6), 1189 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8), 1190 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4), 1191 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8), 1192 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8), 1193 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8), 1194 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8), 1195 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6), 1196 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8), 1197 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8), 1198 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8), 1199 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8), 1200 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4), 1201 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2), 1202 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4), 1203 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8), 1204}; 1205 1206static const struct tegra_gpio_soc tegra234_main_soc = { 1207 .num_ports = ARRAY_SIZE(tegra234_main_ports), 1208 .ports = tegra234_main_ports, 1209 .name = "tegra234-gpio", 1210 .instance = 0, 1211 .num_irqs_per_bank = 8, 1212 .has_vm_support = true, 1213}; 1214 1215#define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1216 TEGRA_GPIO_PORT(TEGRA234_AON, _name, _bank, _port, _pins) 1217 1218static const struct tegra_gpio_port tegra234_aon_ports[] = { 1219 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8), 1220 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4), 1221 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8), 1222 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3), 1223 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8), 1224 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1), 1225}; 1226 1227static const struct tegra_gpio_soc tegra234_aon_soc = { 1228 .num_ports = ARRAY_SIZE(tegra234_aon_ports), 1229 .ports = tegra234_aon_ports, 1230 .name = "tegra234-gpio-aon", 1231 .instance = 1, 1232 .num_irqs_per_bank = 8, 1233 .has_gte = true, 1234 .has_vm_support = false, 1235}; 1236 1237#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1238 TEGRA_GPIO_PORT(TEGRA241_MAIN, _name, _bank, _port, _pins) 1239 1240static const struct tegra_gpio_port tegra241_main_ports[] = { 1241 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8), 1242 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8), 1243 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2), 1244 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6), 1245 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8), 1246 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8), 1247 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8), 1248 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8), 1249 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8), 1250 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4), 1251 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6), 1252}; 1253 1254static const struct tegra_gpio_soc tegra241_main_soc = { 1255 .num_ports = ARRAY_SIZE(tegra241_main_ports), 1256 .ports = tegra241_main_ports, 1257 .name = "tegra241-gpio", 1258 .instance = 0, 1259 .num_irqs_per_bank = 8, 1260 .has_vm_support = false, 1261}; 1262 1263#define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1264 TEGRA_GPIO_PORT(TEGRA241_AON, _name, _bank, _port, _pins) 1265 1266static const struct tegra_gpio_port tegra241_aon_ports[] = { 1267 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8), 1268 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4), 1269}; 1270 1271static const struct tegra_gpio_soc tegra241_aon_soc = { 1272 .num_ports = ARRAY_SIZE(tegra241_aon_ports), 1273 .ports = tegra241_aon_ports, 1274 .name = "tegra241-gpio-aon", 1275 .instance = 1, 1276 .num_irqs_per_bank = 8, 1277 .has_vm_support = false, 1278}; 1279 1280#define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1281 TEGRA_GPIO_PORT(TEGRA256_MAIN, _name, _bank, _port, _pins) 1282 1283static const struct tegra_gpio_port tegra256_main_ports[] = { 1284 TEGRA256_MAIN_GPIO_PORT(A, 0, 0, 8), 1285 TEGRA256_MAIN_GPIO_PORT(B, 0, 1, 8), 1286 TEGRA256_MAIN_GPIO_PORT(C, 0, 2, 8), 1287 TEGRA256_MAIN_GPIO_PORT(D, 0, 3, 8), 1288}; 1289 1290static const struct tegra_gpio_soc tegra256_main_soc = { 1291 .num_ports = ARRAY_SIZE(tegra256_main_ports), 1292 .ports = tegra256_main_ports, 1293 .name = "tegra256-gpio-main", 1294 .instance = 1, 1295 .num_irqs_per_bank = 8, 1296 .has_vm_support = true, 1297}; 1298 1299#define TEGRA410_COMPUTE_GPIO_PORT(_name, _bank, _port, _pins) \ 1300 TEGRA_GPIO_PORT(TEGRA410_COMPUTE, _name, _bank, _port, _pins) 1301 1302static const struct tegra_gpio_port tegra410_compute_ports[] = { 1303 TEGRA410_COMPUTE_GPIO_PORT(A, 0, 0, 3), 1304 TEGRA410_COMPUTE_GPIO_PORT(B, 1, 0, 8), 1305 TEGRA410_COMPUTE_GPIO_PORT(C, 1, 1, 3), 1306 TEGRA410_COMPUTE_GPIO_PORT(D, 2, 0, 8), 1307 TEGRA410_COMPUTE_GPIO_PORT(E, 2, 1, 8), 1308}; 1309 1310static const struct tegra_gpio_soc tegra410_compute_soc = { 1311 .num_ports = ARRAY_SIZE(tegra410_compute_ports), 1312 .ports = tegra410_compute_ports, 1313 .name = "tegra410-gpio-compute", 1314 .prefix = "COMPUTE", 1315 .num_irqs_per_bank = 8, 1316 .instance = 0, 1317}; 1318 1319#define TEGRA410_SYSTEM_GPIO_PORT(_name, _bank, _port, _pins) \ 1320 TEGRA_GPIO_PORT(TEGRA410_SYSTEM, _name, _bank, _port, _pins) 1321 1322static const struct tegra_gpio_port tegra410_system_ports[] = { 1323 TEGRA410_SYSTEM_GPIO_PORT(A, 0, 0, 7), 1324 TEGRA410_SYSTEM_GPIO_PORT(B, 0, 1, 8), 1325 TEGRA410_SYSTEM_GPIO_PORT(C, 0, 2, 8), 1326 TEGRA410_SYSTEM_GPIO_PORT(D, 0, 3, 8), 1327 TEGRA410_SYSTEM_GPIO_PORT(E, 0, 4, 6), 1328 TEGRA410_SYSTEM_GPIO_PORT(I, 1, 0, 8), 1329 TEGRA410_SYSTEM_GPIO_PORT(J, 1, 1, 7), 1330 TEGRA410_SYSTEM_GPIO_PORT(K, 1, 2, 7), 1331 TEGRA410_SYSTEM_GPIO_PORT(L, 1, 3, 7), 1332 TEGRA410_SYSTEM_GPIO_PORT(M, 2, 0, 7), 1333 TEGRA410_SYSTEM_GPIO_PORT(N, 2, 1, 6), 1334 TEGRA410_SYSTEM_GPIO_PORT(P, 2, 2, 8), 1335 TEGRA410_SYSTEM_GPIO_PORT(Q, 2, 3, 3), 1336 TEGRA410_SYSTEM_GPIO_PORT(R, 2, 4, 2), 1337 TEGRA410_SYSTEM_GPIO_PORT(V, 1, 4, 2), 1338}; 1339 1340static const struct tegra_gpio_soc tegra410_system_soc = { 1341 .num_ports = ARRAY_SIZE(tegra410_system_ports), 1342 .ports = tegra410_system_ports, 1343 .name = "tegra410-gpio-system", 1344 .prefix = "SYSTEM", 1345 .num_irqs_per_bank = 8, 1346 .instance = 0, 1347}; 1348 1349static const struct of_device_id tegra186_gpio_of_match[] = { 1350 { 1351 .compatible = "nvidia,tegra186-gpio", 1352 .data = &tegra186_main_soc 1353 }, { 1354 .compatible = "nvidia,tegra186-gpio-aon", 1355 .data = &tegra186_aon_soc 1356 }, { 1357 .compatible = "nvidia,tegra194-gpio", 1358 .data = &tegra194_main_soc 1359 }, { 1360 .compatible = "nvidia,tegra194-gpio-aon", 1361 .data = &tegra194_aon_soc 1362 }, { 1363 .compatible = "nvidia,tegra234-gpio", 1364 .data = &tegra234_main_soc 1365 }, { 1366 .compatible = "nvidia,tegra234-gpio-aon", 1367 .data = &tegra234_aon_soc 1368 }, { 1369 .compatible = "nvidia,tegra256-gpio", 1370 .data = &tegra256_main_soc 1371 }, { 1372 /* sentinel */ 1373 } 1374}; 1375MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match); 1376 1377static const struct acpi_device_id tegra186_gpio_acpi_match[] = { 1378 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc }, 1379 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc }, 1380 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc }, 1381 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc }, 1382 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc }, 1383 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc }, 1384 { .id = "NVDA0708", .driver_data = (kernel_ulong_t)&tegra410_compute_soc }, 1385 { .id = "NVDA0808", .driver_data = (kernel_ulong_t)&tegra410_system_soc }, 1386 {} 1387}; 1388MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match); 1389 1390static struct platform_driver tegra186_gpio_driver = { 1391 .driver = { 1392 .name = "tegra186-gpio", 1393 .of_match_table = tegra186_gpio_of_match, 1394 .acpi_match_table = tegra186_gpio_acpi_match, 1395 }, 1396 .probe = tegra186_gpio_probe, 1397}; 1398module_platform_driver(tegra186_gpio_driver); 1399 1400MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); 1401MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 1402MODULE_LICENSE("GPL v2");
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