gpio-tangier.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Intel Tangier GPIO driver
  4 *
  5 * Copyright (c) 2016, 2021, 2023 Intel Corporation.
  6 *
  7 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  8 *          Pandith N <pandith.n@intel.com>
  9 *          Raag Jadav <raag.jadav@intel.com>
 10 */
 11
 12#include <linux/bitops.h>
 13#include <linux/cleanup.h>
 14#include <linux/device.h>
 15#include <linux/errno.h>
 16#include <linux/export.h>
 17#include <linux/interrupt.h>
 18#include <linux/io.h>
 19#include <linux/irq.h>
 20#include <linux/math.h>
 21#include <linux/module.h>
 22#include <linux/pinctrl/pinconf-generic.h>
 23#include <linux/pm.h>
 24#include <linux/spinlock.h>
 25#include <linux/string_helpers.h>
 26#include <linux/types.h>
 27
 28#include <linux/gpio/driver.h>
 29
 30#include "gpio-tangier.h"
 31
 32#define GCCR		0x000	/* Controller configuration */
 33#define GPLR		0x004	/* Pin level r/o */
 34#define GPDR		0x01c	/* Pin direction */
 35#define GPSR		0x034	/* Pin set w/o */
 36#define GPCR		0x04c	/* Pin clear w/o */
 37#define GRER		0x064	/* Rising edge detect */
 38#define GFER		0x07c	/* Falling edge detect */
 39#define GFBR		0x094	/* Glitch filter bypass */
 40#define GIMR		0x0ac	/* Interrupt mask */
 41#define GISR		0x0c4	/* Interrupt source */
 42#define GITR		0x300	/* Input type */
 43#define GLPR		0x318	/* Level input polarity */
 44
 45/**
 46 * struct tng_gpio_context - Context to be saved during suspend-resume
 47 * @level: Pin level
 48 * @gpdr: Pin direction
 49 * @grer: Rising edge detect enable
 50 * @gfer: Falling edge detect enable
 51 * @gimr: Interrupt mask
 52 * @gwmr: Wake mask
 53 */
 54struct tng_gpio_context {
 55	u32 level;
 56	u32 gpdr;
 57	u32 grer;
 58	u32 gfer;
 59	u32 gimr;
 60	u32 gwmr;
 61};
 62
 63static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
 64			      unsigned int reg)
 65{
 66	struct tng_gpio *priv = gpiochip_get_data(chip);
 67	u8 reg_offset = offset / 32;
 68
 69	return priv->reg_base + reg + reg_offset * 4;
 70}
 71
 72static void __iomem *gpio_reg_and_bit(struct gpio_chip *chip, unsigned int offset,
 73				      unsigned int reg, u8 *bit)
 74{
 75	struct tng_gpio *priv = gpiochip_get_data(chip);
 76	u8 reg_offset = offset / 32;
 77	u8 shift = offset % 32;
 78
 79	*bit = shift;
 80	return priv->reg_base + reg + reg_offset * 4;
 81}
 82
 83static int tng_gpio_get(struct gpio_chip *chip, unsigned int offset)
 84{
 85	void __iomem *gplr;
 86	u8 shift;
 87
 88	gplr = gpio_reg_and_bit(chip, offset, GPLR, &shift);
 89
 90	return !!(readl(gplr) & BIT(shift));
 91}
 92
 93static int tng_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
 94{
 95	struct tng_gpio *priv = gpiochip_get_data(chip);
 96	void __iomem *reg;
 97	u8 shift;
 98
 99	reg = gpio_reg_and_bit(chip, offset, value ? GPSR : GPCR, &shift);
100
101	guard(raw_spinlock_irqsave)(&priv->lock);
102
103	writel(BIT(shift), reg);
104
105	return 0;
106}
107
108static int tng_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
109{
110	struct tng_gpio *priv = gpiochip_get_data(chip);
111	void __iomem *gpdr;
112	u32 value;
113	u8 shift;
114
115	gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
116
117	guard(raw_spinlock_irqsave)(&priv->lock);
118
119	value = readl(gpdr);
120	value &= ~BIT(shift);
121	writel(value, gpdr);
122
123	return 0;
124}
125
126static int tng_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
127				     int value)
128{
129	struct tng_gpio *priv = gpiochip_get_data(chip);
130	void __iomem *gpdr;
131	u8 shift;
132
133	gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
134	tng_gpio_set(chip, offset, value);
135
136	guard(raw_spinlock_irqsave)(&priv->lock);
137
138	value = readl(gpdr);
139	value |= BIT(shift);
140	writel(value, gpdr);
141
142	return 0;
143}
144
145static int tng_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
146{
147	void __iomem *gpdr;
148	u8 shift;
149
150	gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift);
151
152	if (readl(gpdr) & BIT(shift))
153		return GPIO_LINE_DIRECTION_OUT;
154
155	return GPIO_LINE_DIRECTION_IN;
156}
157
158static int tng_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
159				 unsigned int debounce)
160{
161	struct tng_gpio *priv = gpiochip_get_data(chip);
162	void __iomem *gfbr;
163	u32 value;
164	u8 shift;
165
166	gfbr = gpio_reg_and_bit(chip, offset, GFBR, &shift);
167
168	guard(raw_spinlock_irqsave)(&priv->lock);
169
170	value = readl(gfbr);
171	if (debounce)
172		value &= ~BIT(shift);
173	else
174		value |= BIT(shift);
175	writel(value, gfbr);
176
177	return 0;
178}
179
180static int tng_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
181			       unsigned long config)
182{
183	u32 debounce;
184
185	switch (pinconf_to_config_param(config)) {
186	case PIN_CONFIG_BIAS_DISABLE:
187	case PIN_CONFIG_BIAS_PULL_UP:
188	case PIN_CONFIG_BIAS_PULL_DOWN:
189		return gpiochip_generic_config(chip, offset, config);
190	case PIN_CONFIG_INPUT_DEBOUNCE:
191		debounce = pinconf_to_config_argument(config);
192		return tng_gpio_set_debounce(chip, offset, debounce);
193	default:
194		return -ENOTSUPP;
195	}
196}
197
198static void tng_irq_ack(struct irq_data *d)
199{
200	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
201	struct tng_gpio *priv = gpiochip_get_data(gc);
202	irq_hw_number_t gpio = irqd_to_hwirq(d);
203	void __iomem *gisr;
204	u8 shift;
205
206	gisr = gpio_reg_and_bit(&priv->chip, gpio, GISR, &shift);
207
208	guard(raw_spinlock_irqsave)(&priv->lock);
209
210	writel(BIT(shift), gisr);
211}
212
213static void tng_irq_unmask_mask(struct tng_gpio *priv, u32 gpio, bool unmask)
214{
215	void __iomem *gimr;
216	u32 value;
217	u8 shift;
218
219	gimr = gpio_reg_and_bit(&priv->chip, gpio, GIMR, &shift);
220
221	guard(raw_spinlock_irqsave)(&priv->lock);
222
223	value = readl(gimr);
224	if (unmask)
225		value |= BIT(shift);
226	else
227		value &= ~BIT(shift);
228	writel(value, gimr);
229}
230
231static void tng_irq_mask(struct irq_data *d)
232{
233	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
234	struct tng_gpio *priv = gpiochip_get_data(gc);
235	irq_hw_number_t gpio = irqd_to_hwirq(d);
236
237	tng_irq_unmask_mask(priv, gpio, false);
238	gpiochip_disable_irq(&priv->chip, gpio);
239}
240
241static void tng_irq_unmask(struct irq_data *d)
242{
243	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
244	struct tng_gpio *priv = gpiochip_get_data(gc);
245	irq_hw_number_t gpio = irqd_to_hwirq(d);
246
247	gpiochip_enable_irq(&priv->chip, gpio);
248	tng_irq_unmask_mask(priv, gpio, true);
249}
250
251static int tng_irq_set_type(struct irq_data *d, unsigned int type)
252{
253	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
254	struct tng_gpio *priv = gpiochip_get_data(gc);
255	irq_hw_number_t gpio = irqd_to_hwirq(d);
256	void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
257	void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
258	void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
259	void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
260	u8 shift = gpio % 32;
261	u32 value;
262
263	guard(raw_spinlock_irqsave)(&priv->lock);
264
265	value = readl(grer);
266	if (type & IRQ_TYPE_EDGE_RISING)
267		value |= BIT(shift);
268	else
269		value &= ~BIT(shift);
270	writel(value, grer);
271
272	value = readl(gfer);
273	if (type & IRQ_TYPE_EDGE_FALLING)
274		value |= BIT(shift);
275	else
276		value &= ~BIT(shift);
277	writel(value, gfer);
278
279	/*
280	 * To prevent glitches from triggering an unintended level interrupt,
281	 * configure GLPR register first and then configure GITR.
282	 */
283	value = readl(glpr);
284	if (type & IRQ_TYPE_LEVEL_LOW)
285		value |= BIT(shift);
286	else
287		value &= ~BIT(shift);
288	writel(value, glpr);
289
290	if (type & IRQ_TYPE_LEVEL_MASK) {
291		value = readl(gitr);
292		value |= BIT(shift);
293		writel(value, gitr);
294
295		irq_set_handler_locked(d, handle_level_irq);
296	} else if (type & IRQ_TYPE_EDGE_BOTH) {
297		value = readl(gitr);
298		value &= ~BIT(shift);
299		writel(value, gitr);
300
301		irq_set_handler_locked(d, handle_edge_irq);
302	}
303
304	return 0;
305}
306
307static int tng_irq_set_wake(struct irq_data *d, unsigned int on)
308{
309	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
310	struct tng_gpio *priv = gpiochip_get_data(gc);
311	irq_hw_number_t gpio = irqd_to_hwirq(d);
312	void __iomem *gwmr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwmr);
313	void __iomem *gwsr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwsr);
314	u8 shift = gpio % 32;
315	u32 value;
316
317	dev_dbg(priv->dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio);
318
319	guard(raw_spinlock_irqsave)(&priv->lock);
320
321	/* Clear the existing wake status */
322	writel(BIT(shift), gwsr);
323
324	value = readl(gwmr);
325	if (on)
326		value |= BIT(shift);
327	else
328		value &= ~BIT(shift);
329	writel(value, gwmr);
330
331	return 0;
332}
333
334static const struct irq_chip tng_irqchip = {
335	.name		= "gpio-tangier",
336	.irq_ack	= tng_irq_ack,
337	.irq_mask	= tng_irq_mask,
338	.irq_unmask	= tng_irq_unmask,
339	.irq_set_type	= tng_irq_set_type,
340	.irq_set_wake	= tng_irq_set_wake,
341	.flags          = IRQCHIP_IMMUTABLE,
342	GPIOCHIP_IRQ_RESOURCE_HELPERS,
343};
344
345static void tng_irq_handler(struct irq_desc *desc)
346{
347	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
348	struct tng_gpio *priv = gpiochip_get_data(gc);
349	struct irq_chip *irqchip = irq_desc_get_chip(desc);
350	unsigned long base, gpio;
351
352	chained_irq_enter(irqchip, desc);
353
354	/* Check GPIO controller to check which pin triggered the interrupt */
355	for (base = 0; base < priv->chip.ngpio; base += 32) {
356		void __iomem *gisr = gpio_reg(&priv->chip, base, GISR);
357		void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR);
358		unsigned long pending, enabled;
359
360		pending = readl(gisr);
361		enabled = readl(gimr);
362
363		/* Only interrupts that are enabled */
364		pending &= enabled;
365
366		for_each_set_bit(gpio, &pending, 32)
367			generic_handle_domain_irq(gc->irq.domain, base + gpio);
368	}
369
370	chained_irq_exit(irqchip, desc);
371}
372
373static int tng_irq_init_hw(struct gpio_chip *chip)
374{
375	struct tng_gpio *priv = gpiochip_get_data(chip);
376	void __iomem *reg;
377	unsigned int base;
378
379	for (base = 0; base < priv->chip.ngpio; base += 32) {
380		/* Clear the rising-edge detect register */
381		reg = gpio_reg(&priv->chip, base, GRER);
382		writel(0, reg);
383
384		/* Clear the falling-edge detect register */
385		reg = gpio_reg(&priv->chip, base, GFER);
386		writel(0, reg);
387	}
388
389	return 0;
390}
391
392static int tng_gpio_add_pin_ranges(struct gpio_chip *chip)
393{
394	struct tng_gpio *priv = gpiochip_get_data(chip);
395	const struct tng_gpio_pinrange *range;
396	unsigned int i;
397	int ret;
398
399	for (i = 0; i < priv->pin_info.nranges; i++) {
400		range = &priv->pin_info.pin_ranges[i];
401		ret = gpiochip_add_pin_range(&priv->chip,
402					     priv->pin_info.name,
403					     range->gpio_base,
404					     range->pin_base,
405					     range->npins);
406		if (ret) {
407			dev_err(priv->dev, "failed to add GPIO pin range\n");
408			return ret;
409		}
410	}
411
412	return 0;
413}
414
415int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio)
416{
417	const struct tng_gpio_info *info = &gpio->info;
418	size_t nctx = DIV_ROUND_UP(info->ngpio, 32);
419	struct gpio_irq_chip *girq;
420	int ret;
421
422	gpio->ctx = devm_kcalloc(dev, nctx, sizeof(*gpio->ctx), GFP_KERNEL);
423	if (!gpio->ctx)
424		return -ENOMEM;
425
426	gpio->chip.label = dev_name(dev);
427	gpio->chip.parent = dev;
428	gpio->chip.request = gpiochip_generic_request;
429	gpio->chip.free = gpiochip_generic_free;
430	gpio->chip.direction_input = tng_gpio_direction_input;
431	gpio->chip.direction_output = tng_gpio_direction_output;
432	gpio->chip.get = tng_gpio_get;
433	gpio->chip.set = tng_gpio_set;
434	gpio->chip.get_direction = tng_gpio_get_direction;
435	gpio->chip.set_config = tng_gpio_set_config;
436	gpio->chip.base = info->base;
437	gpio->chip.ngpio = info->ngpio;
438	gpio->chip.can_sleep = false;
439	gpio->chip.add_pin_ranges = tng_gpio_add_pin_ranges;
440
441	raw_spin_lock_init(&gpio->lock);
442
443	girq = &gpio->chip.irq;
444	gpio_irq_chip_set_chip(girq, &tng_irqchip);
445	girq->init_hw = tng_irq_init_hw;
446	girq->parent_handler = tng_irq_handler;
447	girq->num_parents = 1;
448	girq->parents = devm_kcalloc(dev, girq->num_parents,
449				     sizeof(*girq->parents), GFP_KERNEL);
450	if (!girq->parents)
451		return -ENOMEM;
452
453	girq->parents[0] = gpio->irq;
454	girq->first = info->first;
455	girq->default_type = IRQ_TYPE_NONE;
456	girq->handler = handle_bad_irq;
457
458	ret = devm_gpiochip_add_data(dev, &gpio->chip, gpio);
459	if (ret)
460		return dev_err_probe(dev, ret, "gpiochip_add error\n");
461
462	return 0;
463}
464EXPORT_SYMBOL_NS_GPL(devm_tng_gpio_probe, "GPIO_TANGIER");
465
466static int tng_gpio_suspend(struct device *dev)
467{
468	struct tng_gpio *priv = dev_get_drvdata(dev);
469	struct tng_gpio_context *ctx = priv->ctx;
470	unsigned int base;
471
472	guard(raw_spinlock_irqsave)(&priv->lock);
473
474	for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) {
475		/* GPLR is RO, values read will be restored using GPSR */
476		ctx->level = readl(gpio_reg(&priv->chip, base, GPLR));
477
478		ctx->gpdr = readl(gpio_reg(&priv->chip, base, GPDR));
479		ctx->grer = readl(gpio_reg(&priv->chip, base, GRER));
480		ctx->gfer = readl(gpio_reg(&priv->chip, base, GFER));
481		ctx->gimr = readl(gpio_reg(&priv->chip, base, GIMR));
482
483		ctx->gwmr = readl(gpio_reg(&priv->chip, base, priv->wake_regs.gwmr));
484	}
485
486	return 0;
487}
488
489static int tng_gpio_resume(struct device *dev)
490{
491	struct tng_gpio *priv = dev_get_drvdata(dev);
492	struct tng_gpio_context *ctx = priv->ctx;
493	unsigned int base;
494
495	guard(raw_spinlock_irqsave)(&priv->lock);
496
497	for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) {
498		/* GPLR is RO, values read will be restored using GPSR */
499		writel(ctx->level, gpio_reg(&priv->chip, base, GPSR));
500
501		writel(ctx->gpdr, gpio_reg(&priv->chip, base, GPDR));
502		writel(ctx->grer, gpio_reg(&priv->chip, base, GRER));
503		writel(ctx->gfer, gpio_reg(&priv->chip, base, GFER));
504		writel(ctx->gimr, gpio_reg(&priv->chip, base, GIMR));
505
506		writel(ctx->gwmr, gpio_reg(&priv->chip, base, priv->wake_regs.gwmr));
507	}
508
509	return 0;
510}
511
512EXPORT_NS_GPL_SIMPLE_DEV_PM_OPS(tng_gpio_pm_ops, tng_gpio_suspend, tng_gpio_resume, GPIO_TANGIER);
513
514MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
515MODULE_AUTHOR("Pandith N <pandith.n@intel.com>");
516MODULE_AUTHOR("Raag Jadav <raag.jadav@intel.com>");
517MODULE_DESCRIPTION("Intel Tangier GPIO driver");
518MODULE_LICENSE("GPL");