gpio-stmpe.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) ST-Ericsson SA 2010
  4 *
  5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  6 */
  7
  8#include <linux/bitops.h>
  9#include <linux/cleanup.h>
 10#include <linux/gpio/driver.h>
 11#include <linux/init.h>
 12#include <linux/interrupt.h>
 13#include <linux/mfd/stmpe.h>
 14#include <linux/property.h>
 15#include <linux/platform_device.h>
 16#include <linux/seq_file.h>
 17#include <linux/slab.h>
 18#include <linux/string_choices.h>
 19
 20/*
 21 * These registers are modified under the irq bus lock and cached to avoid
 22 * unnecessary writes in bus_sync_unlock.
 23 */
 24enum { REG_RE, REG_FE, REG_IE };
 25
 26enum { LSB, CSB, MSB };
 27
 28#define CACHE_NR_REGS	3
 29/* No variant has more than 24 GPIOs */
 30#define CACHE_NR_BANKS	(24 / 8)
 31
 32struct stmpe_gpio {
 33	struct gpio_chip chip;
 34	struct stmpe *stmpe;
 35	struct mutex irq_lock;
 36	u32 norequest_mask;
 37	/* Caches of interrupt control registers for bus_lock */
 38	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
 39	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
 40};
 41
 42static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
 43{
 44	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
 45	struct stmpe *stmpe = stmpe_gpio->stmpe;
 46	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
 47	u8 mask = BIT(offset % 8);
 48	int ret;
 49
 50	ret = stmpe_reg_read(stmpe, reg);
 51	if (ret < 0)
 52		return ret;
 53
 54	return !!(ret & mask);
 55}
 56
 57static int stmpe_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
 58{
 59	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
 60	struct stmpe *stmpe = stmpe_gpio->stmpe;
 61	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
 62	u8 reg = stmpe->regs[which + (offset / 8)];
 63	u8 mask = BIT(offset % 8);
 64
 65	/*
 66	 * Some variants have single register for gpio set/clear functionality.
 67	 * For them we need to write 0 to clear and 1 to set.
 68	 */
 69	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
 70		return stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
 71
 72	return stmpe_reg_write(stmpe, reg, mask);
 73}
 74
 75static int stmpe_gpio_get_direction(struct gpio_chip *chip,
 76				    unsigned offset)
 77{
 78	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
 79	struct stmpe *stmpe = stmpe_gpio->stmpe;
 80	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
 81	u8 mask = BIT(offset % 8);
 82	int ret;
 83
 84	ret = stmpe_reg_read(stmpe, reg);
 85	if (ret < 0)
 86		return ret;
 87
 88	if (ret & mask)
 89		return GPIO_LINE_DIRECTION_OUT;
 90
 91	return GPIO_LINE_DIRECTION_IN;
 92}
 93
 94static int stmpe_gpio_direction_output(struct gpio_chip *chip,
 95					 unsigned offset, int val)
 96{
 97	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
 98	struct stmpe *stmpe = stmpe_gpio->stmpe;
 99	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
100	u8 mask = BIT(offset % 8);
101	int ret;
102
103	ret = stmpe_gpio_set(chip, offset, val);
104	if (ret)
105		return ret;
106
107	return stmpe_set_bits(stmpe, reg, mask, mask);
108}
109
110static int stmpe_gpio_direction_input(struct gpio_chip *chip,
111					unsigned offset)
112{
113	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
114	struct stmpe *stmpe = stmpe_gpio->stmpe;
115	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
116	u8 mask = BIT(offset % 8);
117
118	return stmpe_set_bits(stmpe, reg, mask, 0);
119}
120
121static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
122{
123	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
124	struct stmpe *stmpe = stmpe_gpio->stmpe;
125
126	if (stmpe_gpio->norequest_mask & BIT(offset))
127		return -EINVAL;
128
129	return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
130}
131
132static const struct gpio_chip template_chip = {
133	.label			= "stmpe",
134	.owner			= THIS_MODULE,
135	.get_direction		= stmpe_gpio_get_direction,
136	.direction_input	= stmpe_gpio_direction_input,
137	.get			= stmpe_gpio_get,
138	.direction_output	= stmpe_gpio_direction_output,
139	.set			= stmpe_gpio_set,
140	.request		= stmpe_gpio_request,
141	.can_sleep		= true,
142};
143
144static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
145{
146	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
147	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
148	int offset = d->hwirq;
149	int regoffset = offset / 8;
150	int mask = BIT(offset % 8);
151
152	if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
153		return -EINVAL;
154
155	/* STMPE801 and STMPE 1600 don't have RE and FE registers */
156	if (stmpe_gpio->stmpe->partnum == STMPE801 ||
157	    stmpe_gpio->stmpe->partnum == STMPE1600)
158		return 0;
159
160	if (type & IRQ_TYPE_EDGE_RISING)
161		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
162	else
163		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
164
165	if (type & IRQ_TYPE_EDGE_FALLING)
166		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
167	else
168		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
169
170	return 0;
171}
172
173static void stmpe_gpio_irq_lock(struct irq_data *d)
174{
175	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
176	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
177
178	mutex_lock(&stmpe_gpio->irq_lock);
179}
180
181static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
182{
183	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
184	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
185	struct stmpe *stmpe = stmpe_gpio->stmpe;
186	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
187	static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
188		[REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
189		[REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
190		[REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
191		[REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
192		[REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
193		[REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
194		[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
195		[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
196		[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
197	};
198	int ret, i, j;
199
200	/*
201	 * STMPE1600: to be able to get IRQ from pins,
202	 * a read must be done on GPMR register, or a write in
203	 * GPSR or GPCR registers
204	 */
205	if (stmpe->partnum == STMPE1600) {
206		ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
207		if (ret < 0) {
208			dev_err(stmpe->dev, "Failed to read GPMR_LSB: %d\n", ret);
209			goto err;
210		}
211		ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
212		if (ret < 0) {
213			dev_err(stmpe->dev, "Failed to read GPMR_CSB: %d\n", ret);
214			goto err;
215		}
216	}
217
218	for (i = 0; i < CACHE_NR_REGS; i++) {
219		/* STMPE801 and STMPE1600 don't have RE and FE registers */
220		if ((stmpe->partnum == STMPE801 ||
221		     stmpe->partnum == STMPE1600) &&
222		     (i != REG_IE))
223			continue;
224
225		for (j = 0; j < num_banks; j++) {
226			u8 old = stmpe_gpio->oldregs[i][j];
227			u8 new = stmpe_gpio->regs[i][j];
228
229			if (new == old)
230				continue;
231
232			stmpe_gpio->oldregs[i][j] = new;
233			stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
234		}
235	}
236
237err:
238	mutex_unlock(&stmpe_gpio->irq_lock);
239}
240
241static void stmpe_gpio_irq_mask(struct irq_data *d)
242{
243	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
244	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
245	int offset = d->hwirq;
246	int regoffset = offset / 8;
247	int mask = BIT(offset % 8);
248
249	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
250	gpiochip_disable_irq(gc, offset);
251}
252
253static void stmpe_gpio_irq_unmask(struct irq_data *d)
254{
255	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
256	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
257	int offset = d->hwirq;
258	int regoffset = offset / 8;
259	int mask = BIT(offset % 8);
260
261	gpiochip_enable_irq(gc, offset);
262	stmpe_gpio->regs[REG_IE][regoffset] |= mask;
263}
264
265static void stmpe_dbg_show_one(struct seq_file *s, struct gpio_chip *gc,
266			       unsigned int offset)
267{
268	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
269	struct stmpe *stmpe = stmpe_gpio->stmpe;
270	bool val = !!stmpe_gpio_get(gc, offset);
271	u8 bank = offset / 8;
272	u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
273	u8 mask = BIT(offset % 8);
274	int ret;
275	u8 dir;
276
277	char *label __free(kfree) = gpiochip_dup_line_label(gc, offset);
278	if (IS_ERR(label))
279		return;
280
281	ret = stmpe_reg_read(stmpe, dir_reg);
282	if (ret < 0)
283		return;
284	dir = !!(ret & mask);
285
286	if (dir) {
287		seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
288			   offset, label ?: "(none)", str_hi_lo(val));
289	} else {
290		u8 edge_det_reg;
291		u8 rise_reg;
292		u8 fall_reg;
293		u8 irqen_reg;
294
295		static const char * const edge_det_values[] = {
296			"edge-inactive",
297			"edge-asserted",
298			"not-supported"
299		};
300		static const char * const rise_values[] = {
301			"no-rising-edge-detection",
302			"rising-edge-detection",
303			"not-supported"
304		};
305		static const char * const fall_values[] = {
306			"no-falling-edge-detection",
307			"falling-edge-detection",
308			"not-supported"
309		};
310		#define NOT_SUPPORTED_IDX 2
311		u8 edge_det = NOT_SUPPORTED_IDX;
312		u8 rise = NOT_SUPPORTED_IDX;
313		u8 fall = NOT_SUPPORTED_IDX;
314		bool irqen;
315
316		switch (stmpe->partnum) {
317		case STMPE610:
318		case STMPE811:
319		case STMPE1601:
320		case STMPE2401:
321		case STMPE2403:
322			edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
323			ret = stmpe_reg_read(stmpe, edge_det_reg);
324			if (ret < 0)
325				return;
326			edge_det = !!(ret & mask);
327			fallthrough;
328		case STMPE1801:
329			rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
330			fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
331
332			ret = stmpe_reg_read(stmpe, rise_reg);
333			if (ret < 0)
334				return;
335			rise = !!(ret & mask);
336			ret = stmpe_reg_read(stmpe, fall_reg);
337			if (ret < 0)
338				return;
339			fall = !!(ret & mask);
340			fallthrough;
341		case STMPE801:
342		case STMPE1600:
343			irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
344			break;
345
346		default:
347			return;
348		}
349
350		ret = stmpe_reg_read(stmpe, irqen_reg);
351		if (ret < 0)
352			return;
353		irqen = !!(ret & mask);
354
355		seq_printf(s, " gpio-%-3d (%-20.20s) in  %s %13s %13s %25s %25s",
356			   offset, label ?: "(none)",
357			   str_hi_lo(val),
358			   edge_det_values[edge_det],
359			   irqen ? "IRQ-enabled" : "IRQ-disabled",
360			   rise_values[rise],
361			   fall_values[fall]);
362	}
363}
364
365static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
366{
367	unsigned i;
368
369	for (i = 0; i < gc->ngpio; i++) {
370		stmpe_dbg_show_one(s, gc, i);
371		seq_putc(s, '\n');
372	}
373}
374
375static const struct irq_chip stmpe_gpio_irq_chip = {
376	.name			= "stmpe-gpio",
377	.irq_bus_lock		= stmpe_gpio_irq_lock,
378	.irq_bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
379	.irq_mask		= stmpe_gpio_irq_mask,
380	.irq_unmask		= stmpe_gpio_irq_unmask,
381	.irq_set_type		= stmpe_gpio_irq_set_type,
382	.flags			= IRQCHIP_IMMUTABLE,
383	GPIOCHIP_IRQ_RESOURCE_HELPERS,
384};
385
386#define MAX_GPIOS 24
387
388static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
389{
390	struct stmpe_gpio *stmpe_gpio = dev;
391	struct stmpe *stmpe = stmpe_gpio->stmpe;
392	u8 statmsbreg;
393	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
394	u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
395	int ret;
396	int i;
397
398	/*
399	 * the stmpe_block_read() call below, imposes to set statmsbreg
400	 * with the register located at the lowest address. As STMPE1600
401	 * variant is the only one which respect registers address's order
402	 * (LSB regs located at lowest address than MSB ones) whereas all
403	 * the others have a registers layout with MSB located before the
404	 * LSB regs.
405	 */
406	if (stmpe->partnum == STMPE1600)
407		statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
408	else
409		statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
410
411	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
412	if (ret < 0)
413		return IRQ_NONE;
414
415	for (i = 0; i < num_banks; i++) {
416		int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
417			   num_banks - i - 1;
418		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
419		unsigned int stat = status[i];
420
421		stat &= enabled;
422		if (!stat)
423			continue;
424
425		while (stat) {
426			int bit = __ffs(stat);
427			int line = bank * 8 + bit;
428			int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
429							 line);
430
431			handle_nested_irq(child_irq);
432			stat &= ~BIT(bit);
433		}
434
435		/*
436		 * interrupt status register write has no effect on
437		 * 801/1801/1600, bits are cleared when read.
438		 * Edge detect register is not present on 801/1600/1801
439		 */
440		if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
441		    stmpe->partnum != STMPE1801) {
442			stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
443			stmpe_reg_write(stmpe,
444					stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
445					status[i]);
446		}
447	}
448
449	return IRQ_HANDLED;
450}
451
452static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
453				      unsigned long *valid_mask,
454				      unsigned int ngpios)
455{
456	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
457	int i;
458
459	if (!stmpe_gpio->norequest_mask)
460		return;
461
462	/* Forbid unused lines to be mapped as IRQs */
463	for (i = 0; i < sizeof(u32); i++) {
464		if (stmpe_gpio->norequest_mask & BIT(i))
465			clear_bit(i, valid_mask);
466	}
467}
468
469static void stmpe_gpio_disable(void *stmpe)
470{
471	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
472}
473
474static int stmpe_gpio_probe(struct platform_device *pdev)
475{
476	struct device *dev = &pdev->dev;
477	struct stmpe *stmpe = dev_get_drvdata(dev->parent);
478	struct stmpe_gpio *stmpe_gpio;
479	int ret, irq;
480
481	if (stmpe->num_gpios > MAX_GPIOS) {
482		dev_err(dev, "Need to increase maximum GPIO number\n");
483		return -EINVAL;
484	}
485
486	stmpe_gpio = devm_kzalloc(dev, sizeof(*stmpe_gpio), GFP_KERNEL);
487	if (!stmpe_gpio)
488		return -ENOMEM;
489
490	mutex_init(&stmpe_gpio->irq_lock);
491
492	stmpe_gpio->stmpe = stmpe;
493	stmpe_gpio->chip = template_chip;
494	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
495	stmpe_gpio->chip.parent = dev;
496	stmpe_gpio->chip.base = -1;
497
498	if (IS_ENABLED(CONFIG_DEBUG_FS))
499                stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
500
501	device_property_read_u32(dev, "st,norequest-mask", &stmpe_gpio->norequest_mask);
502
503	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
504	if (ret)
505		return ret;
506
507	ret = devm_add_action_or_reset(dev, stmpe_gpio_disable, stmpe);
508	if (ret)
509		return ret;
510
511	irq = platform_get_irq(pdev, 0);
512	if (irq > 0) {
513		struct gpio_irq_chip *girq;
514
515		ret = devm_request_threaded_irq(dev, irq, NULL, stmpe_gpio_irq,
516						IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
517		if (ret)
518			return dev_err_probe(dev, ret, "unable to register IRQ handler\n");
519
520		girq = &stmpe_gpio->chip.irq;
521		gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);
522		/* This will let us handle the parent IRQ in the driver */
523		girq->parent_handler = NULL;
524		girq->num_parents = 0;
525		girq->parents = NULL;
526		girq->default_type = IRQ_TYPE_NONE;
527		girq->handler = handle_simple_irq;
528		girq->threaded = true;
529		girq->init_valid_mask = stmpe_init_irq_valid_mask;
530	}
531
532	return devm_gpiochip_add_data(dev, &stmpe_gpio->chip, stmpe_gpio);
533}
534
535static const struct of_device_id stmpe_gpio_of_matches[] = {
536	{ .compatible = "st,stmpe-gpio", },
537	{ /* sentinel */ }
538};
539MODULE_DEVICE_TABLE(of, stmpe_gpio_of_matches);
540
541static struct platform_driver stmpe_gpio_driver = {
542	.driver = {
543		.name = "stmpe-gpio",
544		.of_match_table = stmpe_gpio_of_matches,
545	},
546	.probe		= stmpe_gpio_probe,
547};
548
549static int __init stmpe_gpio_init(void)
550{
551	return platform_driver_register(&stmpe_gpio_driver);
552}
553subsys_initcall(stmpe_gpio_init);
554
555static void __exit stmpe_gpio_exit(void)
556{
557	platform_driver_unregister(&stmpe_gpio_driver);
558}
559module_exit(stmpe_gpio_exit);
560
561MODULE_DESCRIPTION("STMPE expander GPIO");
562MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
563MODULE_LICENSE("GPL");