gpio-sifive.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2019 SiFive
  4 */
  5
  6#include <linux/bitops.h>
  7#include <linux/device.h>
  8#include <linux/errno.h>
  9#include <linux/gpio/driver.h>
 10#include <linux/gpio/generic.h>
 11#include <linux/init.h>
 12#include <linux/platform_device.h>
 13#include <linux/property.h>
 14#include <linux/slab.h>
 15#include <linux/spinlock.h>
 16#include <linux/regmap.h>
 17
 18#define SIFIVE_GPIO_INPUT_VAL	0x00
 19#define SIFIVE_GPIO_INPUT_EN	0x04
 20#define SIFIVE_GPIO_OUTPUT_EN	0x08
 21#define SIFIVE_GPIO_OUTPUT_VAL	0x0C
 22#define SIFIVE_GPIO_RISE_IE	0x18
 23#define SIFIVE_GPIO_RISE_IP	0x1C
 24#define SIFIVE_GPIO_FALL_IE	0x20
 25#define SIFIVE_GPIO_FALL_IP	0x24
 26#define SIFIVE_GPIO_HIGH_IE	0x28
 27#define SIFIVE_GPIO_HIGH_IP	0x2C
 28#define SIFIVE_GPIO_LOW_IE	0x30
 29#define SIFIVE_GPIO_LOW_IP	0x34
 30#define SIFIVE_GPIO_OUTPUT_XOR	0x40
 31
 32#define SIFIVE_GPIO_MAX		32
 33
 34struct sifive_gpio {
 35	void __iomem		*base;
 36	struct gpio_generic_chip gen_gc;
 37	struct regmap		*regs;
 38	unsigned long		irq_state;
 39	unsigned int		trigger[SIFIVE_GPIO_MAX];
 40	unsigned int		irq_number[SIFIVE_GPIO_MAX];
 41};
 42
 43static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
 44{
 45	unsigned int trigger;
 46
 47	guard(gpio_generic_lock_irqsave)(&chip->gen_gc);
 48
 49	trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0;
 50	regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset),
 51			   (trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0);
 52	regmap_update_bits(chip->regs, SIFIVE_GPIO_FALL_IE, BIT(offset),
 53			   (trigger & IRQ_TYPE_EDGE_FALLING) ? BIT(offset) : 0);
 54	regmap_update_bits(chip->regs, SIFIVE_GPIO_HIGH_IE, BIT(offset),
 55			   (trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0);
 56	regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset),
 57			   (trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0);
 58}
 59
 60static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger)
 61{
 62	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 63	struct sifive_gpio *chip = gpiochip_get_data(gc);
 64	int offset = irqd_to_hwirq(d);
 65
 66	if (offset < 0 || offset >= gc->ngpio)
 67		return -EINVAL;
 68
 69	chip->trigger[offset] = trigger;
 70	sifive_gpio_set_ie(chip, offset);
 71	return 0;
 72}
 73
 74static void sifive_gpio_irq_enable(struct irq_data *d)
 75	{
 76	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 77	struct sifive_gpio *chip = gpiochip_get_data(gc);
 78	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 79	int offset = hwirq % SIFIVE_GPIO_MAX;
 80	u32 bit = BIT(offset);
 81
 82	gpiochip_enable_irq(gc, hwirq);
 83	irq_chip_enable_parent(d);
 84
 85	/* Switch to input */
 86	gc->direction_input(gc, offset);
 87
 88	scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) {
 89		/* Clear any sticky pending interrupts */
 90		regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
 91		regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
 92		regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
 93		regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
 94	}
 95
 96	/* Enable interrupts */
 97	assign_bit(offset, &chip->irq_state, 1);
 98	sifive_gpio_set_ie(chip, offset);
 99}
100
101static void sifive_gpio_irq_disable(struct irq_data *d)
102{
103	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
104	struct sifive_gpio *chip = gpiochip_get_data(gc);
105	irq_hw_number_t hwirq = irqd_to_hwirq(d);
106	int offset = hwirq % SIFIVE_GPIO_MAX;
107
108	assign_bit(offset, &chip->irq_state, 0);
109	sifive_gpio_set_ie(chip, offset);
110	irq_chip_disable_parent(d);
111	gpiochip_disable_irq(gc, hwirq);
112}
113
114static void sifive_gpio_irq_eoi(struct irq_data *d)
115{
116	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
117	struct sifive_gpio *chip = gpiochip_get_data(gc);
118	int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
119	u32 bit = BIT(offset);
120
121	scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) {
122		/* Clear all pending interrupts */
123		regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
124		regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
125		regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
126		regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
127	}
128
129	irq_chip_eoi_parent(d);
130}
131
132static int sifive_gpio_irq_set_affinity(struct irq_data *data,
133					const struct cpumask *dest,
134					bool force)
135{
136	if (data->parent_data)
137		return irq_chip_set_affinity_parent(data, dest, force);
138
139	return -EINVAL;
140}
141
142static const struct irq_chip sifive_gpio_irqchip = {
143	.name		= "sifive-gpio",
144	.irq_set_type	= sifive_gpio_irq_set_type,
145	.irq_mask	= irq_chip_mask_parent,
146	.irq_unmask	= irq_chip_unmask_parent,
147	.irq_enable	= sifive_gpio_irq_enable,
148	.irq_disable	= sifive_gpio_irq_disable,
149	.irq_eoi	= sifive_gpio_irq_eoi,
150	.irq_set_affinity = sifive_gpio_irq_set_affinity,
151	.irq_set_wake	= irq_chip_set_wake_parent,
152	.flags		= IRQCHIP_IMMUTABLE,
153	GPIOCHIP_IRQ_RESOURCE_HELPERS,
154};
155
156static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
157					     unsigned int child,
158					     unsigned int child_type,
159					     unsigned int *parent,
160					     unsigned int *parent_type)
161{
162	struct sifive_gpio *chip = gpiochip_get_data(gc);
163	struct irq_data *d = irq_get_irq_data(chip->irq_number[child]);
164
165	*parent_type = IRQ_TYPE_NONE;
166	*parent = irqd_to_hwirq(d);
167
168	return 0;
169}
170
171static const struct regmap_config sifive_gpio_regmap_config = {
172	.reg_bits = 32,
173	.reg_stride = 4,
174	.val_bits = 32,
175	.disable_locking = true,
176};
177
178static int sifive_gpio_probe(struct platform_device *pdev)
179{
180	struct gpio_generic_chip_config config;
181	struct device *dev = &pdev->dev;
182	struct irq_domain *parent;
183	struct gpio_irq_chip *girq;
184	struct sifive_gpio *chip;
185	int ret, ngpio;
186
187	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
188	if (!chip)
189		return -ENOMEM;
190
191	chip->base = devm_platform_ioremap_resource(pdev, 0);
192	if (IS_ERR(chip->base)) {
193		dev_err(dev, "failed to allocate device memory\n");
194		return PTR_ERR(chip->base);
195	}
196
197	chip->regs = devm_regmap_init_mmio(dev, chip->base,
198					   &sifive_gpio_regmap_config);
199	if (IS_ERR(chip->regs))
200		return PTR_ERR(chip->regs);
201
202	for (ngpio = 0; ngpio < SIFIVE_GPIO_MAX; ngpio++) {
203		ret = platform_get_irq_optional(pdev, ngpio);
204		if (ret < 0)
205			break;
206		chip->irq_number[ngpio] = ret;
207	}
208	if (!ngpio) {
209		dev_err(dev, "no IRQ found\n");
210		return -ENODEV;
211	}
212
213	/*
214	 * The check above ensures at least one parent IRQ is valid.
215	 * Assume all parent IRQs belong to the same domain.
216	 */
217	parent = irq_get_irq_data(chip->irq_number[0])->domain;
218
219	config = (struct gpio_generic_chip_config) {
220		.dev = dev,
221		.sz = 4,
222		.dat = chip->base + SIFIVE_GPIO_INPUT_VAL,
223		.set = chip->base + SIFIVE_GPIO_OUTPUT_VAL,
224		.dirout = chip->base + SIFIVE_GPIO_OUTPUT_EN,
225		.dirin = chip->base + SIFIVE_GPIO_INPUT_EN,
226		.flags = GPIO_GENERIC_READ_OUTPUT_REG_SET,
227	};
228
229	ret = gpio_generic_chip_init(&chip->gen_gc, &config);
230	if (ret) {
231		dev_err(dev, "unable to init generic GPIO\n");
232		return ret;
233	}
234
235	/* Disable all GPIO interrupts before enabling parent interrupts */
236	regmap_write(chip->regs, SIFIVE_GPIO_RISE_IE, 0);
237	regmap_write(chip->regs, SIFIVE_GPIO_FALL_IE, 0);
238	regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IE, 0);
239	regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0);
240	chip->irq_state = 0;
241
242	chip->gen_gc.gc.base = -1;
243	chip->gen_gc.gc.ngpio = ngpio;
244	chip->gen_gc.gc.label = dev_name(dev);
245	chip->gen_gc.gc.parent = dev;
246	chip->gen_gc.gc.owner = THIS_MODULE;
247	girq = &chip->gen_gc.gc.irq;
248	gpio_irq_chip_set_chip(girq, &sifive_gpio_irqchip);
249	girq->fwnode = dev_fwnode(dev);
250	girq->parent_domain = parent;
251	girq->child_to_parent_hwirq = sifive_gpio_child_to_parent_hwirq;
252	girq->handler = handle_bad_irq;
253	girq->default_type = IRQ_TYPE_NONE;
254
255	return gpiochip_add_data(&chip->gen_gc.gc, chip);
256}
257
258static const struct of_device_id sifive_gpio_match[] = {
259	{ .compatible = "sifive,gpio0" },
260	{ .compatible = "sifive,fu540-c000-gpio" },
261	{ },
262};
263
264static struct platform_driver sifive_gpio_driver = {
265	.probe		= sifive_gpio_probe,
266	.driver = {
267		.name	= "sifive_gpio",
268		.of_match_table = sifive_gpio_match,
269	},
270};
271module_platform_driver(sifive_gpio_driver)
272
273MODULE_AUTHOR("Yash Shah <yash.shah@sifive.com>");
274MODULE_DESCRIPTION("SiFive GPIO driver");
275MODULE_LICENSE("GPL");