gpio-rockchip.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2013 MundoReader S.L.
  4 * Author: Heiko Stuebner <heiko@sntech.de>
  5 *
  6 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
  7 */
  8
  9#include <linux/bitops.h>
 10#include <linux/clk.h>
 11#include <linux/device.h>
 12#include <linux/err.h>
 13#include <linux/gpio/driver.h>
 14#include <linux/init.h>
 15#include <linux/interrupt.h>
 16#include <linux/io.h>
 17#include <linux/module.h>
 18#include <linux/of.h>
 19#include <linux/of_address.h>
 20#include <linux/of_irq.h>
 21#include <linux/pinctrl/pinconf-generic.h>
 22#include <linux/platform_device.h>
 23#include <linux/regmap.h>
 24
 25#include "../pinctrl/core.h"
 26#include "../pinctrl/pinctrl-rockchip.h"
 27
 28/*
 29 * Version ID Register
 30 * Bits [31:24] - Major Version
 31 * Bits [23:16] - Minor Version
 32 * Bits [15:0]  - Revision Number
 33 */
 34#define GPIO_TYPE_V1		(0)           /* GPIO Version ID reserved */
 35#define GPIO_TYPE_V2		(0x01000C2B)
 36#define GPIO_TYPE_V2_1		(0x0101157C)
 37#define GPIO_TYPE_V2_2		(0x010219C8)
 38
 39static const struct rockchip_gpio_regs gpio_regs_v1 = {
 40	.port_dr = 0x00,
 41	.port_ddr = 0x04,
 42	.int_en = 0x30,
 43	.int_mask = 0x34,
 44	.int_type = 0x38,
 45	.int_polarity = 0x3c,
 46	.int_status = 0x40,
 47	.int_rawstatus = 0x44,
 48	.debounce = 0x48,
 49	.port_eoi = 0x4c,
 50	.ext_port = 0x50,
 51};
 52
 53static const struct rockchip_gpio_regs gpio_regs_v2 = {
 54	.port_dr = 0x00,
 55	.port_ddr = 0x08,
 56	.int_en = 0x10,
 57	.int_mask = 0x18,
 58	.int_type = 0x20,
 59	.int_polarity = 0x28,
 60	.int_bothedge = 0x30,
 61	.int_status = 0x50,
 62	.int_rawstatus = 0x58,
 63	.debounce = 0x38,
 64	.dbclk_div_en = 0x40,
 65	.dbclk_div_con = 0x48,
 66	.port_eoi = 0x60,
 67	.ext_port = 0x70,
 68	.version_id = 0x78,
 69};
 70
 71static inline void gpio_writel_v2(u32 val, void __iomem *reg)
 72{
 73	writel((val & 0xffff) | 0xffff0000, reg);
 74	writel((val >> 16) | 0xffff0000, reg + 0x4);
 75}
 76
 77static inline u32 gpio_readl_v2(void __iomem *reg)
 78{
 79	return readl(reg + 0x4) << 16 | readl(reg);
 80}
 81
 82static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
 83					u32 value, unsigned int offset)
 84{
 85	void __iomem *reg = bank->reg_base + offset;
 86
 87	if (bank->gpio_type == GPIO_TYPE_V2)
 88		gpio_writel_v2(value, reg);
 89	else
 90		writel(value, reg);
 91}
 92
 93static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
 94				      unsigned int offset)
 95{
 96	void __iomem *reg = bank->reg_base + offset;
 97	u32 value;
 98
 99	if (bank->gpio_type == GPIO_TYPE_V2)
100		value = gpio_readl_v2(reg);
101	else
102		value = readl(reg);
103
104	return value;
105}
106
107static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
108					    u32 bit, u32 value,
109					    unsigned int offset)
110{
111	void __iomem *reg = bank->reg_base + offset;
112	u32 data;
113
114	if (bank->gpio_type == GPIO_TYPE_V2) {
115		if (value)
116			data = BIT(bit % 16) | BIT(bit % 16 + 16);
117		else
118			data = BIT(bit % 16 + 16);
119		writel(data, bit >= 16 ? reg + 0x4 : reg);
120	} else {
121		data = readl(reg);
122		data &= ~BIT(bit);
123		if (value)
124			data |= BIT(bit);
125		writel(data, reg);
126	}
127}
128
129static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
130					  u32 bit, unsigned int offset)
131{
132	void __iomem *reg = bank->reg_base + offset;
133	u32 data;
134
135	if (bank->gpio_type == GPIO_TYPE_V2) {
136		data = readl(bit >= 16 ? reg + 0x4 : reg);
137		data >>= bit % 16;
138	} else {
139		data = readl(reg);
140		data >>= bit;
141	}
142
143	return data & (0x1);
144}
145
146static int rockchip_gpio_get_direction(struct gpio_chip *chip,
147				       unsigned int offset)
148{
149	struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
150	u32 data;
151
152	data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
153	if (data)
154		return GPIO_LINE_DIRECTION_OUT;
155
156	return GPIO_LINE_DIRECTION_IN;
157}
158
159static int rockchip_gpio_set_direction(struct gpio_chip *chip,
160				       unsigned int offset, bool input)
161{
162	struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
163	unsigned long flags;
164	u32 data = input ? 0 : 1;
165
166	raw_spin_lock_irqsave(&bank->slock, flags);
167	rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
168	raw_spin_unlock_irqrestore(&bank->slock, flags);
169
170	return 0;
171}
172
173static int rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
174			     int value)
175{
176	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
177	unsigned long flags;
178
179	raw_spin_lock_irqsave(&bank->slock, flags);
180	rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
181	raw_spin_unlock_irqrestore(&bank->slock, flags);
182
183	return 0;
184}
185
186static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
187{
188	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
189	u32 data;
190
191	data = readl(bank->reg_base + bank->gpio_regs->ext_port);
192	data >>= offset;
193	data &= 1;
194
195	return data;
196}
197
198static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
199				      unsigned int offset,
200				      unsigned int debounce)
201{
202	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
203	const struct rockchip_gpio_regs	*reg = bank->gpio_regs;
204	unsigned long flags, div_reg, freq, max_debounce;
205	bool div_debounce_support;
206	unsigned int cur_div_reg;
207	u64 div;
208
209	if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
210		div_debounce_support = true;
211		freq = clk_get_rate(bank->db_clk);
212		max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
213		if (debounce > max_debounce)
214			return -EINVAL;
215
216		div = debounce * freq;
217		div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
218	} else {
219		div_debounce_support = false;
220	}
221
222	raw_spin_lock_irqsave(&bank->slock, flags);
223
224	/* Only the v1 needs to configure div_en and div_con for dbclk */
225	if (debounce) {
226		if (div_debounce_support) {
227			/* Configure the max debounce from consumers */
228			cur_div_reg = readl(bank->reg_base +
229					    reg->dbclk_div_con);
230			if (cur_div_reg < div_reg)
231				writel(div_reg, bank->reg_base +
232				       reg->dbclk_div_con);
233			rockchip_gpio_writel_bit(bank, offset, 1,
234						 reg->dbclk_div_en);
235		}
236
237		rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
238	} else {
239		if (div_debounce_support)
240			rockchip_gpio_writel_bit(bank, offset, 0,
241						 reg->dbclk_div_en);
242
243		rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
244	}
245
246	raw_spin_unlock_irqrestore(&bank->slock, flags);
247
248	/* Enable or disable dbclk at last */
249	if (div_debounce_support) {
250		if (debounce)
251			clk_prepare_enable(bank->db_clk);
252		else
253			clk_disable_unprepare(bank->db_clk);
254	}
255
256	return 0;
257}
258
259static int rockchip_gpio_direction_input(struct gpio_chip *gc,
260					 unsigned int offset)
261{
262	return rockchip_gpio_set_direction(gc, offset, true);
263}
264
265static int rockchip_gpio_direction_output(struct gpio_chip *gc,
266					  unsigned int offset, int value)
267{
268	rockchip_gpio_set(gc, offset, value);
269
270	return rockchip_gpio_set_direction(gc, offset, false);
271}
272
273/*
274 * gpiolib set_config callback function. The setting of the pin
275 * mux function as 'gpio output' will be handled by the pinctrl subsystem
276 * interface.
277 */
278static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
279				  unsigned long config)
280{
281	enum pin_config_param param = pinconf_to_config_param(config);
282
283	switch (param) {
284	case PIN_CONFIG_INPUT_DEBOUNCE:
285		rockchip_gpio_set_debounce(gc, offset, true);
286		/*
287		 * Rockchip's gpio could only support up to one period
288		 * of the debounce clock(pclk), which is far away from
289		 * satisftying the requirement, as pclk is usually near
290		 * 100MHz shared by all peripherals. So the fact is it
291		 * has crippled debounce capability could only be useful
292		 * to prevent any spurious glitches from waking up the system
293		 * if the gpio is conguired as wakeup interrupt source. Let's
294		 * still return -ENOTSUPP as before, to make sure the caller
295		 * of gpiod_set_debounce won't change its behaviour.
296		 */
297		return -ENOTSUPP;
298	default:
299		return -ENOTSUPP;
300	}
301}
302
303/*
304 * gpiod_to_irq() callback function. Creates a mapping between a GPIO pin
305 * and a virtual IRQ, if not already present.
306 */
307static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
308{
309	struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
310	unsigned int virq;
311
312	if (!bank->domain)
313		return -ENXIO;
314
315	virq = irq_create_mapping(bank->domain, offset);
316
317	return (virq) ? : -ENXIO;
318}
319
320static const struct gpio_chip rockchip_gpiolib_chip = {
321	.request = gpiochip_generic_request,
322	.free = gpiochip_generic_free,
323	.set = rockchip_gpio_set,
324	.get = rockchip_gpio_get,
325	.get_direction	= rockchip_gpio_get_direction,
326	.direction_input = rockchip_gpio_direction_input,
327	.direction_output = rockchip_gpio_direction_output,
328	.set_config = rockchip_gpio_set_config,
329	.to_irq = rockchip_gpio_to_irq,
330	.owner = THIS_MODULE,
331};
332
333static void rockchip_irq_demux(struct irq_desc *desc)
334{
335	struct irq_chip *chip = irq_desc_get_chip(desc);
336	struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
337	unsigned long pending;
338	unsigned int irq;
339
340	dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
341
342	chained_irq_enter(chip, desc);
343
344	pending = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
345	for_each_set_bit(irq, &pending, 32) {
346		dev_dbg(bank->dev, "handling irq %d\n", irq);
347
348		/*
349		 * Triggering IRQ on both rising and falling edge
350		 * needs manual intervention.
351		 */
352		if (bank->toggle_edge_mode & BIT(irq)) {
353			u32 data, data_old, polarity;
354			unsigned long flags;
355
356			data = readl_relaxed(bank->reg_base +
357					     bank->gpio_regs->ext_port);
358			do {
359				raw_spin_lock_irqsave(&bank->slock, flags);
360
361				polarity = readl_relaxed(bank->reg_base +
362							 bank->gpio_regs->int_polarity);
363				if (data & BIT(irq))
364					polarity &= ~BIT(irq);
365				else
366					polarity |= BIT(irq);
367				writel(polarity,
368				       bank->reg_base +
369				       bank->gpio_regs->int_polarity);
370
371				raw_spin_unlock_irqrestore(&bank->slock, flags);
372
373				data_old = data;
374				data = readl_relaxed(bank->reg_base +
375						     bank->gpio_regs->ext_port);
376			} while ((data & BIT(irq)) != (data_old & BIT(irq)));
377		}
378
379		generic_handle_domain_irq(bank->domain, irq);
380	}
381
382	chained_irq_exit(chip, desc);
383}
384
385static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
386{
387	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
388	struct rockchip_pin_bank *bank = gc->private;
389	u32 mask = BIT(d->hwirq);
390	u32 polarity;
391	u32 level;
392	u32 data;
393	unsigned long flags;
394	int ret = 0;
395
396	raw_spin_lock_irqsave(&bank->slock, flags);
397
398	rockchip_gpio_writel_bit(bank, d->hwirq, 0,
399				 bank->gpio_regs->port_ddr);
400
401	raw_spin_unlock_irqrestore(&bank->slock, flags);
402
403	if (type & IRQ_TYPE_EDGE_BOTH)
404		irq_set_handler_locked(d, handle_edge_irq);
405	else
406		irq_set_handler_locked(d, handle_level_irq);
407
408	raw_spin_lock_irqsave(&bank->slock, flags);
409
410	level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
411	polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
412
413	if (type == IRQ_TYPE_EDGE_BOTH) {
414		if (bank->gpio_type == GPIO_TYPE_V2) {
415			rockchip_gpio_writel_bit(bank, d->hwirq, 1,
416						 bank->gpio_regs->int_bothedge);
417			goto out;
418		} else {
419			bank->toggle_edge_mode |= mask;
420			level &= ~mask;
421
422			/*
423			 * Determine gpio state. If 1 next interrupt should be
424			 * low otherwise high.
425			 */
426			data = readl(bank->reg_base + bank->gpio_regs->ext_port);
427			if (data & mask)
428				polarity &= ~mask;
429			else
430				polarity |= mask;
431		}
432	} else {
433		if (bank->gpio_type == GPIO_TYPE_V2) {
434			rockchip_gpio_writel_bit(bank, d->hwirq, 0,
435						 bank->gpio_regs->int_bothedge);
436		} else {
437			bank->toggle_edge_mode &= ~mask;
438		}
439		switch (type) {
440		case IRQ_TYPE_EDGE_RISING:
441			level |= mask;
442			polarity |= mask;
443			break;
444		case IRQ_TYPE_EDGE_FALLING:
445			level |= mask;
446			polarity &= ~mask;
447			break;
448		case IRQ_TYPE_LEVEL_HIGH:
449			level &= ~mask;
450			polarity |= mask;
451			break;
452		case IRQ_TYPE_LEVEL_LOW:
453			level &= ~mask;
454			polarity &= ~mask;
455			break;
456		default:
457			ret = -EINVAL;
458			goto out;
459		}
460	}
461
462	rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
463	rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
464out:
465	raw_spin_unlock_irqrestore(&bank->slock, flags);
466
467	return ret;
468}
469
470static int rockchip_irq_reqres(struct irq_data *d)
471{
472	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
473	struct rockchip_pin_bank *bank = gc->private;
474
475	return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq);
476}
477
478static void rockchip_irq_relres(struct irq_data *d)
479{
480	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
481	struct rockchip_pin_bank *bank = gc->private;
482
483	gpiochip_relres_irq(&bank->gpio_chip, d->hwirq);
484}
485
486static void rockchip_irq_suspend(struct irq_data *d)
487{
488	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
489	struct rockchip_pin_bank *bank = gc->private;
490
491	bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
492	irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
493}
494
495static void rockchip_irq_resume(struct irq_data *d)
496{
497	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
498	struct rockchip_pin_bank *bank = gc->private;
499
500	irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
501}
502
503static void rockchip_irq_enable(struct irq_data *d)
504{
505	irq_gc_mask_clr_bit(d);
506}
507
508static void rockchip_irq_disable(struct irq_data *d)
509{
510	irq_gc_mask_set_bit(d);
511}
512
513static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
514{
515	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
516	struct irq_chip_generic *gc;
517	int ret;
518
519	bank->domain = irq_domain_create_linear(dev_fwnode(bank->dev), 32, &irq_generic_chip_ops,
520						NULL);
521	if (!bank->domain) {
522		dev_warn(bank->dev, "could not init irq domain for bank %s\n",
523			 bank->name);
524		return -EINVAL;
525	}
526
527	ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
528					     "rockchip_gpio_irq",
529					     handle_level_irq,
530					     clr, 0, 0);
531	if (ret) {
532		dev_err(bank->dev, "could not alloc generic chips for bank %s\n",
533			bank->name);
534		irq_domain_remove(bank->domain);
535		return -EINVAL;
536	}
537
538	gc = irq_get_domain_generic_chip(bank->domain, 0);
539	if (bank->gpio_type == GPIO_TYPE_V2) {
540		gc->reg_writel = gpio_writel_v2;
541		gc->reg_readl = gpio_readl_v2;
542	}
543
544	gc->reg_base = bank->reg_base;
545	gc->private = bank;
546	gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
547	gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
548	gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
549	gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
550	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
551	gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
552	gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
553	gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
554	gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
555	gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
556	gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
557	gc->chip_types[0].chip.irq_request_resources = rockchip_irq_reqres;
558	gc->chip_types[0].chip.irq_release_resources = rockchip_irq_relres;
559	gc->wake_enabled = IRQ_MSK(bank->nr_pins);
560
561	/*
562	 * Linux assumes that all interrupts start out disabled/masked.
563	 * Our driver only uses the concept of masked and always keeps
564	 * things enabled, so for us that's all masked and all enabled.
565	 */
566	rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
567	rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
568	rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
569	gc->mask_cache = 0xffffffff;
570
571	irq_set_chained_handler_and_data(bank->irq,
572					 rockchip_irq_demux, bank);
573
574	return 0;
575}
576
577static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
578{
579	struct gpio_chip *gc;
580	int ret;
581
582	bank->gpio_chip = rockchip_gpiolib_chip;
583
584	gc = &bank->gpio_chip;
585	gc->base = bank->pin_base;
586	gc->ngpio = bank->nr_pins;
587	gc->label = bank->name;
588	gc->parent = bank->dev;
589
590	ret = gpiochip_add_data(gc, bank);
591	if (ret) {
592		dev_err(bank->dev, "failed to add gpiochip %s, %d\n",
593			gc->label, ret);
594		return ret;
595	}
596
597	/*
598	 * For DeviceTree-supported systems, the gpio core checks the
599	 * pinctrl's device node for the "gpio-ranges" property.
600	 * If it is present, it takes care of adding the pin ranges
601	 * for the driver. In this case the driver can skip ahead.
602	 *
603	 * In order to remain compatible with older, existing DeviceTree
604	 * files which don't set the "gpio-ranges" property or systems that
605	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
606	 */
607	if (!of_property_present(bank->of_node, "gpio-ranges")) {
608		struct device_node *pctlnp = of_get_parent(bank->of_node);
609		struct pinctrl_dev *pctldev = NULL;
610
611		if (!pctlnp)
612			return -ENODATA;
613
614		pctldev = of_pinctrl_get(pctlnp);
615		of_node_put(pctlnp);
616		if (!pctldev)
617			return -ENODEV;
618
619		ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0,
620					     gc->base, gc->ngpio);
621		if (ret) {
622			dev_err(bank->dev, "Failed to add pin range\n");
623			goto fail;
624		}
625	}
626
627	ret = rockchip_interrupts_register(bank);
628	if (ret) {
629		dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
630		goto fail;
631	}
632
633	return 0;
634
635fail:
636	gpiochip_remove(&bank->gpio_chip);
637
638	return ret;
639}
640
641static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
642{
643	struct resource res;
644	int id = 0;
645
646	if (of_address_to_resource(bank->of_node, 0, &res)) {
647		dev_err(bank->dev, "cannot find IO resource for bank\n");
648		return -ENOENT;
649	}
650
651	bank->reg_base = devm_ioremap_resource(bank->dev, &res);
652	if (IS_ERR(bank->reg_base))
653		return PTR_ERR(bank->reg_base);
654
655	bank->irq = irq_of_parse_and_map(bank->of_node, 0);
656	if (!bank->irq)
657		return -EINVAL;
658
659	bank->clk = of_clk_get(bank->of_node, 0);
660	if (IS_ERR(bank->clk))
661		return PTR_ERR(bank->clk);
662
663	clk_prepare_enable(bank->clk);
664	id = readl(bank->reg_base + gpio_regs_v2.version_id);
665
666	switch (id) {
667	case GPIO_TYPE_V2:
668	case GPIO_TYPE_V2_1:
669	case GPIO_TYPE_V2_2:
670		bank->gpio_regs = &gpio_regs_v2;
671		bank->gpio_type = GPIO_TYPE_V2;
672		bank->db_clk = of_clk_get(bank->of_node, 1);
673		if (IS_ERR(bank->db_clk)) {
674			dev_err(bank->dev, "cannot find debounce clk\n");
675			clk_disable_unprepare(bank->clk);
676			return -EINVAL;
677		}
678		break;
679	case GPIO_TYPE_V1:
680		bank->gpio_regs = &gpio_regs_v1;
681		bank->gpio_type = GPIO_TYPE_V1;
682		break;
683	default:
684		dev_err(bank->dev, "unsupported version ID: 0x%08x\n", id);
685		return -ENODEV;
686	}
687
688	return 0;
689}
690
691static struct rockchip_pin_bank *
692rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id)
693{
694	struct rockchip_pinctrl *info;
695	struct rockchip_pin_bank *bank;
696	int i, found = 0;
697
698	info = pinctrl_dev_get_drvdata(pctldev);
699	bank = info->ctrl->pin_banks;
700	for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {
701		if (bank->bank_num == id) {
702			found = 1;
703			break;
704		}
705	}
706
707	return found ? bank : NULL;
708}
709
710static int rockchip_gpio_probe(struct platform_device *pdev)
711{
712	struct device *dev = &pdev->dev;
713	struct device_node *np = dev->of_node;
714	struct device_node *pctlnp = of_get_parent(np);
715	struct pinctrl_dev *pctldev = NULL;
716	struct rockchip_pin_bank *bank = NULL;
717	struct rockchip_pin_deferred *cfg;
718	static int gpio;
719	int id, ret;
720
721	if (!np || !pctlnp)
722		return -ENODEV;
723
724	pctldev = of_pinctrl_get(pctlnp);
725	of_node_put(pctlnp);
726	if (!pctldev)
727		return -EPROBE_DEFER;
728
729	id = of_alias_get_id(np, "gpio");
730	if (id < 0)
731		id = gpio++;
732
733	bank = rockchip_gpio_find_bank(pctldev, id);
734	if (!bank)
735		return -EINVAL;
736
737	bank->dev = dev;
738	bank->of_node = np;
739
740	raw_spin_lock_init(&bank->slock);
741
742	ret = rockchip_get_bank_data(bank);
743	if (ret)
744		return ret;
745
746	/*
747	 * Prevent clashes with a deferred output setting
748	 * being added right at this moment.
749	 */
750	mutex_lock(&bank->deferred_lock);
751
752	ret = rockchip_gpiolib_register(bank);
753	if (ret) {
754		clk_disable_unprepare(bank->clk);
755		mutex_unlock(&bank->deferred_lock);
756		return ret;
757	}
758
759	while (!list_empty(&bank->deferred_pins)) {
760		cfg = list_first_entry(&bank->deferred_pins,
761				       struct rockchip_pin_deferred, head);
762		list_del(&cfg->head);
763
764		switch (cfg->param) {
765		case PIN_CONFIG_LEVEL:
766			ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
767			if (ret)
768				dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin,
769					 cfg->arg);
770			break;
771		case PIN_CONFIG_INPUT_ENABLE:
772			ret = rockchip_gpio_direction_input(&bank->gpio_chip, cfg->pin);
773			if (ret)
774				dev_warn(dev, "setting input pin %u failed\n", cfg->pin);
775			break;
776		default:
777			dev_warn(dev, "unknown deferred config param %d\n", cfg->param);
778			break;
779		}
780		kfree(cfg);
781	}
782
783	mutex_unlock(&bank->deferred_lock);
784
785	platform_set_drvdata(pdev, bank);
786	dev_info(dev, "probed %pOF\n", np);
787
788	return 0;
789}
790
791static void rockchip_gpio_remove(struct platform_device *pdev)
792{
793	struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
794
795	clk_disable_unprepare(bank->clk);
796	gpiochip_remove(&bank->gpio_chip);
797}
798
799static const struct of_device_id rockchip_gpio_match[] = {
800	{ .compatible = "rockchip,gpio-bank", },
801	{ .compatible = "rockchip,rk3188-gpio-bank0" },
802	{ },
803};
804
805static struct platform_driver rockchip_gpio_driver = {
806	.probe		= rockchip_gpio_probe,
807	.remove		= rockchip_gpio_remove,
808	.driver		= {
809		.name	= "rockchip-gpio",
810		.of_match_table = rockchip_gpio_match,
811	},
812};
813
814static int __init rockchip_gpio_init(void)
815{
816	return platform_driver_register(&rockchip_gpio_driver);
817}
818postcore_initcall(rockchip_gpio_init);
819
820static void __exit rockchip_gpio_exit(void)
821{
822	platform_driver_unregister(&rockchip_gpio_driver);
823}
824module_exit(rockchip_gpio_exit);
825
826MODULE_DESCRIPTION("Rockchip gpio driver");
827MODULE_ALIAS("platform:rockchip-gpio");
828MODULE_LICENSE("GPL v2");
829MODULE_DEVICE_TABLE(of, rockchip_gpio_match);