gpio-rcar.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Renesas R-Car GPIO Support
  4 *
  5 *  Copyright (C) 2014 Renesas Electronics Corporation
  6 *  Copyright (C) 2013 Magnus Damm
  7 */
  8
  9#include <linux/err.h>
 10#include <linux/gpio/driver.h>
 11#include <linux/init.h>
 12#include <linux/interrupt.h>
 13#include <linux/io.h>
 14#include <linux/ioport.h>
 15#include <linux/irq.h>
 16#include <linux/module.h>
 17#include <linux/of.h>
 18#include <linux/pinctrl/consumer.h>
 19#include <linux/platform_device.h>
 20#include <linux/pm_runtime.h>
 21#include <linux/spinlock.h>
 22#include <linux/slab.h>
 23
 24struct gpio_rcar_bank_info {
 25	u32 iointsel;
 26	u32 inoutsel;
 27	u32 outdt;
 28	u32 posneg;
 29	u32 edglevel;
 30	u32 bothedge;
 31	u32 intmsk;
 32};
 33
 34struct gpio_rcar_info {
 35	bool has_outdtsel;
 36	bool has_both_edge_trigger;
 37	bool has_always_in;
 38	bool has_inen;
 39};
 40
 41struct gpio_rcar_priv {
 42	void __iomem *base;
 43	raw_spinlock_t lock;
 44	struct device *dev;
 45	struct gpio_chip gpio_chip;
 46	unsigned int irq_parent;
 47	atomic_t wakeup_path;
 48	struct gpio_rcar_info info;
 49	struct gpio_rcar_bank_info bank_info;
 50};
 51
 52#define IOINTSEL	0x00	/* General IO/Interrupt Switching Register */
 53#define INOUTSEL	0x04	/* General Input/Output Switching Register */
 54#define OUTDT		0x08	/* General Output Register */
 55#define INDT		0x0c	/* General Input Register */
 56#define INTDT		0x10	/* Interrupt Display Register */
 57#define INTCLR		0x14	/* Interrupt Clear Register */
 58#define INTMSK		0x18	/* Interrupt Mask Register */
 59#define MSKCLR		0x1c	/* Interrupt Mask Clear Register */
 60#define POSNEG		0x20	/* Positive/Negative Logic Select Register */
 61#define EDGLEVEL	0x24	/* Edge/level Select Register */
 62#define FILONOFF	0x28	/* Chattering Prevention On/Off Register */
 63#define OUTDTSEL	0x40	/* Output Data Select Register */
 64#define BOTHEDGE	0x4c	/* One Edge/Both Edge Select Register */
 65#define INEN		0x50	/* General Input Enable Register */
 66
 67#define RCAR_MAX_GPIO_PER_BANK		32
 68
 69static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
 70{
 71	return ioread32(p->base + offs);
 72}
 73
 74static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
 75				   u32 value)
 76{
 77	iowrite32(value, p->base + offs);
 78}
 79
 80static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
 81				 int bit, bool value)
 82{
 83	u32 tmp = gpio_rcar_read(p, offs);
 84
 85	if (value)
 86		tmp |= BIT(bit);
 87	else
 88		tmp &= ~BIT(bit);
 89
 90	gpio_rcar_write(p, offs, tmp);
 91}
 92
 93static void gpio_rcar_irq_disable(struct irq_data *d)
 94{
 95	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 96	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
 97	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 98
 99	gpio_rcar_write(p, INTMSK, ~BIT(hwirq));
100	gpiochip_disable_irq(gc, hwirq);
101}
102
103static void gpio_rcar_irq_enable(struct irq_data *d)
104{
105	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
106	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
107	irq_hw_number_t hwirq = irqd_to_hwirq(d);
108
109	gpiochip_enable_irq(gc, hwirq);
110	gpio_rcar_write(p, MSKCLR, BIT(hwirq));
111}
112
113static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
114						  unsigned int hwirq,
115						  bool active_high_rising_edge,
116						  bool level_trigger,
117						  bool both)
118{
119	unsigned long flags;
120
121	/* follow steps in the GPIO documentation for
122	 * "Setting Edge-Sensitive Interrupt Input Mode" and
123	 * "Setting Level-Sensitive Interrupt Input Mode"
124	 */
125
126	raw_spin_lock_irqsave(&p->lock, flags);
127
128	/* Configure positive or negative logic in POSNEG */
129	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
130
131	/* Configure edge or level trigger in EDGLEVEL */
132	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
133
134	/* Select one edge or both edges in BOTHEDGE */
135	if (p->info.has_both_edge_trigger)
136		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
137
138	/* Select "Interrupt Input Mode" in IOINTSEL */
139	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
140
141	/* Write INTCLR in case of edge trigger */
142	if (!level_trigger)
143		gpio_rcar_write(p, INTCLR, BIT(hwirq));
144
145	raw_spin_unlock_irqrestore(&p->lock, flags);
146}
147
148static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
149{
150	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
151	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
152	unsigned int hwirq = irqd_to_hwirq(d);
153
154	dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
155
156	switch (type & IRQ_TYPE_SENSE_MASK) {
157	case IRQ_TYPE_LEVEL_HIGH:
158		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
159						      false);
160		break;
161	case IRQ_TYPE_LEVEL_LOW:
162		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
163						      false);
164		break;
165	case IRQ_TYPE_EDGE_RISING:
166		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
167						      false);
168		break;
169	case IRQ_TYPE_EDGE_FALLING:
170		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
171						      false);
172		break;
173	case IRQ_TYPE_EDGE_BOTH:
174		if (!p->info.has_both_edge_trigger)
175			return -EINVAL;
176		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
177						      true);
178		break;
179	default:
180		return -EINVAL;
181	}
182	return 0;
183}
184
185static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
186{
187	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
188	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
189	int error;
190
191	if (p->irq_parent) {
192		error = irq_set_irq_wake(p->irq_parent, on);
193		if (error) {
194			dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
195				p->irq_parent);
196			p->irq_parent = 0;
197		}
198	}
199
200	if (on)
201		atomic_inc(&p->wakeup_path);
202	else
203		atomic_dec(&p->wakeup_path);
204
205	return 0;
206}
207
208static const struct irq_chip gpio_rcar_irq_chip = {
209	.name		= "gpio-rcar",
210	.irq_mask	= gpio_rcar_irq_disable,
211	.irq_unmask	= gpio_rcar_irq_enable,
212	.irq_set_type	= gpio_rcar_irq_set_type,
213	.irq_set_wake	= gpio_rcar_irq_set_wake,
214	.flags		= IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED |
215			  IRQCHIP_MASK_ON_SUSPEND,
216	GPIOCHIP_IRQ_RESOURCE_HELPERS,
217};
218
219static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
220{
221	struct gpio_rcar_priv *p = dev_id;
222	u32 pending;
223	unsigned int offset, irqs_handled = 0;
224
225	while ((pending = gpio_rcar_read(p, INTDT) &
226			  gpio_rcar_read(p, INTMSK))) {
227		offset = __ffs(pending);
228		gpio_rcar_write(p, INTCLR, BIT(offset));
229		generic_handle_domain_irq(p->gpio_chip.irq.domain,
230					  offset);
231		irqs_handled++;
232	}
233
234	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
235}
236
237static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
238						       unsigned int gpio,
239						       bool output)
240{
241	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
242	unsigned long flags;
243
244	/* follow steps in the GPIO documentation for
245	 * "Setting General Output Mode" and
246	 * "Setting General Input Mode"
247	 */
248
249	raw_spin_lock_irqsave(&p->lock, flags);
250
251	/* Configure positive logic in POSNEG */
252	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
253
254	/* Select "General Input/Output Mode" in IOINTSEL */
255	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
256
257	/* Select Input Mode or Output Mode in INOUTSEL */
258	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
259
260	/* Select General Output Register to output data in OUTDTSEL */
261	if (p->info.has_outdtsel && output)
262		gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
263
264	raw_spin_unlock_irqrestore(&p->lock, flags);
265}
266
267static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
268{
269	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
270	int error;
271
272	error = pm_runtime_get_sync(p->dev);
273	if (error < 0) {
274		pm_runtime_put(p->dev);
275		return error;
276	}
277
278	error = pinctrl_gpio_request(chip, offset);
279	if (error)
280		pm_runtime_put(p->dev);
281
282	return error;
283}
284
285static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
286{
287	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
288
289	pinctrl_gpio_free(chip, offset);
290
291	/*
292	 * Set the GPIO as an input to ensure that the next GPIO request won't
293	 * drive the GPIO pin as an output.
294	 */
295	gpio_rcar_config_general_input_output_mode(chip, offset, false);
296
297	pm_runtime_put(p->dev);
298}
299
300static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
301{
302	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
303
304	if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))
305		return GPIO_LINE_DIRECTION_OUT;
306
307	return GPIO_LINE_DIRECTION_IN;
308}
309
310static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
311{
312	gpio_rcar_config_general_input_output_mode(chip, offset, false);
313	return 0;
314}
315
316static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
317{
318	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
319	u32 bit = BIT(offset);
320
321	/*
322	 * Before R-Car Gen3, INDT does not show correct pin state when
323	 * configured as output, so use OUTDT in case of output pins
324	 */
325	if (!p->info.has_always_in && (gpio_rcar_read(p, INOUTSEL) & bit))
326		return !!(gpio_rcar_read(p, OUTDT) & bit);
327	else
328		return !!(gpio_rcar_read(p, INDT) & bit);
329}
330
331static int gpio_rcar_get_multiple(struct gpio_chip *chip, unsigned long *mask,
332				  unsigned long *bits)
333{
334	u32 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
335	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
336	u32 outputs, m, val = 0;
337	unsigned long flags;
338
339	if (p->info.has_always_in) {
340		bits[0] = gpio_rcar_read(p, INDT) & bankmask;
341		return 0;
342	}
343
344	raw_spin_lock_irqsave(&p->lock, flags);
345	outputs = gpio_rcar_read(p, INOUTSEL);
346	m = outputs & bankmask;
347	if (m)
348		val |= gpio_rcar_read(p, OUTDT) & m;
349
350	m = ~outputs & bankmask;
351	if (m)
352		val |= gpio_rcar_read(p, INDT) & m;
353	raw_spin_unlock_irqrestore(&p->lock, flags);
354
355	bits[0] = val;
356	return 0;
357}
358
359static int gpio_rcar_set(struct gpio_chip *chip, unsigned int offset, int value)
360{
361	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
362	unsigned long flags;
363
364	raw_spin_lock_irqsave(&p->lock, flags);
365	gpio_rcar_modify_bit(p, OUTDT, offset, value);
366	raw_spin_unlock_irqrestore(&p->lock, flags);
367
368	return 0;
369}
370
371static int gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
372				  unsigned long *bits)
373{
374	u32 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
375	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
376	unsigned long flags;
377	u32 val;
378
379	raw_spin_lock_irqsave(&p->lock, flags);
380	val = gpio_rcar_read(p, OUTDT);
381	val &= ~bankmask;
382	val |= (bankmask & bits[0]);
383	gpio_rcar_write(p, OUTDT, val);
384	raw_spin_unlock_irqrestore(&p->lock, flags);
385
386	return 0;
387}
388
389static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
390				      int value)
391{
392	/* write GPIO value to output before selecting output mode of pin */
393	gpio_rcar_set(chip, offset, value);
394	gpio_rcar_config_general_input_output_mode(chip, offset, true);
395	return 0;
396}
397
398static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
399	.has_outdtsel = false,
400	.has_both_edge_trigger = false,
401	.has_always_in = false,
402	.has_inen = false,
403};
404
405static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
406	.has_outdtsel = true,
407	.has_both_edge_trigger = true,
408	.has_always_in = false,
409	.has_inen = false,
410};
411
412static const struct gpio_rcar_info gpio_rcar_info_gen3 = {
413	.has_outdtsel = true,
414	.has_both_edge_trigger = true,
415	.has_always_in = true,
416	.has_inen = false,
417};
418
419static const struct gpio_rcar_info gpio_rcar_info_gen4 = {
420	.has_outdtsel = true,
421	.has_both_edge_trigger = true,
422	.has_always_in = true,
423	.has_inen = true,
424};
425
426static const struct of_device_id gpio_rcar_of_table[] = {
427	{
428		.compatible = "renesas,gpio-r8a779a0",
429		.data = &gpio_rcar_info_gen4,
430	}, {
431		.compatible = "renesas,rcar-gen1-gpio",
432		.data = &gpio_rcar_info_gen1,
433	}, {
434		.compatible = "renesas,rcar-gen2-gpio",
435		.data = &gpio_rcar_info_gen2,
436	}, {
437		.compatible = "renesas,rcar-gen3-gpio",
438		.data = &gpio_rcar_info_gen3,
439	}, {
440		.compatible = "renesas,rcar-gen4-gpio",
441		.data = &gpio_rcar_info_gen4,
442	}, {
443		.compatible = "renesas,gpio-rcar",
444		.data = &gpio_rcar_info_gen1,
445	}, {
446		/* Terminator */
447	},
448};
449
450MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
451
452static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
453{
454	struct device_node *np = p->dev->of_node;
455	const struct gpio_rcar_info *info;
456	struct of_phandle_args args;
457	int ret;
458
459	info = of_device_get_match_data(p->dev);
460	p->info = *info;
461
462	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
463	if (ret) {
464		*npins = RCAR_MAX_GPIO_PER_BANK;
465	} else {
466		*npins = args.args[2];
467		of_node_put(args.np);
468	}
469
470	if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
471		dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
472			 *npins, RCAR_MAX_GPIO_PER_BANK);
473		*npins = RCAR_MAX_GPIO_PER_BANK;
474	}
475
476	return 0;
477}
478
479static void gpio_rcar_enable_inputs(struct gpio_rcar_priv *p)
480{
481	u32 mask = GENMASK(p->gpio_chip.ngpio - 1, 0);
482	const unsigned long *valid_mask;
483
484	valid_mask = gpiochip_query_valid_mask(&p->gpio_chip);
485
486	/* Select "Input Enable" in INEN */
487	if (valid_mask)
488		mask &= valid_mask[0];
489	if (mask)
490		gpio_rcar_write(p, INEN, gpio_rcar_read(p, INEN) | mask);
491}
492
493static int gpio_rcar_probe(struct platform_device *pdev)
494{
495	struct gpio_rcar_priv *p;
496	struct gpio_chip *gpio_chip;
497	struct gpio_irq_chip *girq;
498	struct device *dev = &pdev->dev;
499	const char *name = dev_name(dev);
500	unsigned int npins;
501	int ret;
502
503	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
504	if (!p)
505		return -ENOMEM;
506
507	p->dev = dev;
508	raw_spin_lock_init(&p->lock);
509
510	/* Get device configuration from DT node */
511	ret = gpio_rcar_parse_dt(p, &npins);
512	if (ret < 0)
513		return ret;
514
515	platform_set_drvdata(pdev, p);
516
517	pm_runtime_enable(dev);
518
519	ret = platform_get_irq(pdev, 0);
520	if (ret < 0)
521		goto err0;
522	p->irq_parent = ret;
523
524	p->base = devm_platform_ioremap_resource(pdev, 0);
525	if (IS_ERR(p->base)) {
526		ret = PTR_ERR(p->base);
527		goto err0;
528	}
529
530	gpio_chip = &p->gpio_chip;
531	gpio_chip->request = gpio_rcar_request;
532	gpio_chip->free = gpio_rcar_free;
533	gpio_chip->get_direction = gpio_rcar_get_direction;
534	gpio_chip->direction_input = gpio_rcar_direction_input;
535	gpio_chip->get = gpio_rcar_get;
536	gpio_chip->get_multiple = gpio_rcar_get_multiple;
537	gpio_chip->direction_output = gpio_rcar_direction_output;
538	gpio_chip->set = gpio_rcar_set;
539	gpio_chip->set_multiple = gpio_rcar_set_multiple;
540	gpio_chip->label = name;
541	gpio_chip->parent = dev;
542	gpio_chip->owner = THIS_MODULE;
543	gpio_chip->base = -1;
544	gpio_chip->ngpio = npins;
545
546	girq = &gpio_chip->irq;
547	gpio_irq_chip_set_chip(girq, &gpio_rcar_irq_chip);
548	/* This will let us handle the parent IRQ in the driver */
549	girq->parent_handler = NULL;
550	girq->num_parents = 0;
551	girq->parents = NULL;
552	girq->default_type = IRQ_TYPE_NONE;
553	girq->handler = handle_level_irq;
554
555	ret = gpiochip_add_data(gpio_chip, p);
556	if (ret) {
557		dev_err(dev, "failed to add GPIO controller\n");
558		goto err0;
559	}
560
561	irq_domain_set_pm_device(gpio_chip->irq.domain, dev);
562	ret = devm_request_irq(dev, p->irq_parent, gpio_rcar_irq_handler,
563			       IRQF_SHARED, name, p);
564	if (ret) {
565		dev_err(dev, "failed to request IRQ\n");
566		goto err1;
567	}
568
569	if (p->info.has_inen) {
570		pm_runtime_get_sync(dev);
571		gpio_rcar_enable_inputs(p);
572		pm_runtime_put(dev);
573	}
574
575	dev_info(dev, "driving %d GPIOs\n", npins);
576
577	return 0;
578
579err1:
580	gpiochip_remove(gpio_chip);
581err0:
582	pm_runtime_disable(dev);
583	return ret;
584}
585
586static void gpio_rcar_remove(struct platform_device *pdev)
587{
588	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
589
590	gpiochip_remove(&p->gpio_chip);
591
592	pm_runtime_disable(&pdev->dev);
593}
594
595static int gpio_rcar_suspend(struct device *dev)
596{
597	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
598
599	p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
600	p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
601	p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
602	p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
603	p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
604	p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
605	if (p->info.has_both_edge_trigger)
606		p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
607
608	if (atomic_read(&p->wakeup_path))
609		device_set_wakeup_path(dev);
610
611	return 0;
612}
613
614static int gpio_rcar_resume(struct device *dev)
615{
616	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
617	unsigned int offset;
618	u32 mask;
619
620	for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
621		if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
622			continue;
623
624		mask = BIT(offset);
625		/* I/O pin */
626		if (!(p->bank_info.iointsel & mask)) {
627			if (p->bank_info.inoutsel & mask)
628				gpio_rcar_direction_output(
629					&p->gpio_chip, offset,
630					!!(p->bank_info.outdt & mask));
631			else
632				gpio_rcar_direction_input(&p->gpio_chip,
633							  offset);
634		} else {
635			/* Interrupt pin */
636			gpio_rcar_config_interrupt_input_mode(
637				p,
638				offset,
639				!(p->bank_info.posneg & mask),
640				!(p->bank_info.edglevel & mask),
641				!!(p->bank_info.bothedge & mask));
642
643			if (p->bank_info.intmsk & mask)
644				gpio_rcar_write(p, MSKCLR, mask);
645		}
646	}
647
648	if (p->info.has_inen)
649		gpio_rcar_enable_inputs(p);
650
651	return 0;
652}
653
654static DEFINE_SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend,
655				gpio_rcar_resume);
656
657static struct platform_driver gpio_rcar_device_driver = {
658	.probe		= gpio_rcar_probe,
659	.remove		= gpio_rcar_remove,
660	.driver		= {
661		.name	= "gpio_rcar",
662		.pm     = pm_sleep_ptr(&gpio_rcar_pm_ops),
663		.of_match_table = gpio_rcar_of_table,
664	}
665};
666
667module_platform_driver(gpio_rcar_device_driver);
668
669MODULE_AUTHOR("Magnus Damm");
670MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
671MODULE_LICENSE("GPL v2");