gpio-pcf857x.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders
  4 *
  5 * Copyright (C) 2007 David Brownell
  6 */
  7
  8#include <linux/delay.h>
  9#include <linux/gpio/consumer.h>
 10#include <linux/gpio/driver.h>
 11#include <linux/i2c.h>
 12#include <linux/interrupt.h>
 13#include <linux/irq.h>
 14#include <linux/irqdomain.h>
 15#include <linux/kernel.h>
 16#include <linux/mod_devicetable.h>
 17#include <linux/module.h>
 18#include <linux/property.h>
 19#include <linux/slab.h>
 20#include <linux/spinlock.h>
 21
 22static const struct i2c_device_id pcf857x_id[] = {
 23	{ "pcf8574", 8 },
 24	{ "pcf8574a", 8 },
 25	{ "pca8574", 8 },
 26	{ "pca9670", 8 },
 27	{ "pca9672", 8 },
 28	{ "pca9674", 8 },
 29	{ "pcf8575", 16 },
 30	{ "pca8575", 16 },
 31	{ "pca9671", 16 },
 32	{ "pca9673", 16 },
 33	{ "pca9675", 16 },
 34	{ "max7328", 8 },
 35	{ "max7329", 8 },
 36	{ }
 37};
 38MODULE_DEVICE_TABLE(i2c, pcf857x_id);
 39
 40static const struct of_device_id pcf857x_of_table[] = {
 41	{ .compatible = "nxp,pcf8574", (void *)8 },
 42	{ .compatible = "nxp,pcf8574a", (void *)8 },
 43	{ .compatible = "nxp,pca8574", (void *)8 },
 44	{ .compatible = "nxp,pca9670", (void *)8 },
 45	{ .compatible = "nxp,pca9672", (void *)8 },
 46	{ .compatible = "nxp,pca9674", (void *)8 },
 47	{ .compatible = "nxp,pcf8575", (void *)16 },
 48	{ .compatible = "nxp,pca8575", (void *)16 },
 49	{ .compatible = "nxp,pca9671", (void *)16 },
 50	{ .compatible = "nxp,pca9673", (void *)16 },
 51	{ .compatible = "nxp,pca9675", (void *)16 },
 52	{ .compatible = "maxim,max7328", (void *)8 },
 53	{ .compatible = "maxim,max7329", (void *)8 },
 54	{ }
 55};
 56MODULE_DEVICE_TABLE(of, pcf857x_of_table);
 57
 58/*
 59 * The pcf857x, pca857x, and pca967x chips only expose one read and one
 60 * write register.  Writing a "one" bit (to match the reset state) lets
 61 * that pin be used as an input; it's not an open-drain model, but acts
 62 * a bit like one.  This is described as "quasi-bidirectional"; read the
 63 * chip documentation for details.
 64 *
 65 * Many other I2C GPIO expander chips (like the pca953x models) have
 66 * more complex register models and more conventional circuitry using
 67 * push/pull drivers.  They often use the same 0x20..0x27 addresses as
 68 * pcf857x parts, making the "legacy" I2C driver model problematic.
 69 */
 70struct pcf857x {
 71	struct gpio_chip	chip;
 72	struct i2c_client	*client;
 73	struct mutex		lock;		/* protect 'out' */
 74	unsigned int		out;		/* software latch */
 75	unsigned int		status;		/* current status */
 76	unsigned int		irq_enabled;	/* enabled irqs */
 77
 78	int (*write)(struct i2c_client *client, unsigned int data);
 79	int (*read)(struct i2c_client *client);
 80};
 81
 82/*-------------------------------------------------------------------------*/
 83
 84/* Talk to 8-bit I/O expander */
 85
 86static int i2c_write_le8(struct i2c_client *client, unsigned int data)
 87{
 88	return i2c_smbus_write_byte(client, data);
 89}
 90
 91static int i2c_read_le8(struct i2c_client *client)
 92{
 93	return i2c_smbus_read_byte(client);
 94}
 95
 96/* Talk to 16-bit I/O expander */
 97
 98static int i2c_write_le16(struct i2c_client *client, unsigned int word)
 99{
100	u8 buf[2] = { word & 0xff, word >> 8, };
101	int status;
102
103	status = i2c_master_send(client, buf, 2);
104	return (status < 0) ? status : 0;
105}
106
107static int i2c_read_le16(struct i2c_client *client)
108{
109	u8 buf[2];
110	int status;
111
112	status = i2c_master_recv(client, buf, 2);
113	if (status < 0)
114		return status;
115	return (buf[1] << 8) | buf[0];
116}
117
118/*-------------------------------------------------------------------------*/
119
120static int pcf857x_input(struct gpio_chip *chip, unsigned int offset)
121{
122	struct pcf857x *gpio = gpiochip_get_data(chip);
123	int status;
124
125	mutex_lock(&gpio->lock);
126	gpio->out |= (1 << offset);
127	status = gpio->write(gpio->client, gpio->out);
128	mutex_unlock(&gpio->lock);
129
130	return status;
131}
132
133static int pcf857x_get(struct gpio_chip *chip, unsigned int offset)
134{
135	struct pcf857x *gpio = gpiochip_get_data(chip);
136	int value;
137
138	value = gpio->read(gpio->client);
139	return (value < 0) ? value : !!(value & (1 << offset));
140}
141
142static int pcf857x_get_multiple(struct gpio_chip *chip, unsigned long *mask,
143				unsigned long *bits)
144{
145	struct pcf857x *gpio = gpiochip_get_data(chip);
146	int value = gpio->read(gpio->client);
147
148	if (value < 0)
149		return value;
150
151	*bits &= ~*mask;
152	*bits |= value & *mask;
153
154	return 0;
155}
156
157static int pcf857x_output(struct gpio_chip *chip, unsigned int offset, int value)
158{
159	struct pcf857x *gpio = gpiochip_get_data(chip);
160	unsigned int bit = 1 << offset;
161	int status;
162
163	mutex_lock(&gpio->lock);
164	if (value)
165		gpio->out |= bit;
166	else
167		gpio->out &= ~bit;
168	status = gpio->write(gpio->client, gpio->out);
169	mutex_unlock(&gpio->lock);
170
171	return status;
172}
173
174static int pcf857x_set(struct gpio_chip *chip, unsigned int offset, int value)
175{
176	return pcf857x_output(chip, offset, value);
177}
178
179static int pcf857x_set_multiple(struct gpio_chip *chip, unsigned long *mask,
180				unsigned long *bits)
181{
182	struct pcf857x *gpio = gpiochip_get_data(chip);
183	int status;
184
185	mutex_lock(&gpio->lock);
186	gpio->out &= ~*mask;
187	gpio->out |= *bits & *mask;
188	status = gpio->write(gpio->client, gpio->out);
189	mutex_unlock(&gpio->lock);
190
191	return status;
192}
193
194/*-------------------------------------------------------------------------*/
195
196static irqreturn_t pcf857x_irq(int irq, void *data)
197{
198	struct pcf857x *gpio = data;
199	unsigned long change, i, status;
200
201	status = gpio->read(gpio->client);
202
203	/*
204	 * call the interrupt handler iff gpio is used as
205	 * interrupt source, just to avoid bad irqs
206	 */
207	mutex_lock(&gpio->lock);
208	change = (gpio->status ^ status) & gpio->irq_enabled;
209	gpio->status = status;
210	mutex_unlock(&gpio->lock);
211
212	for_each_set_bit(i, &change, gpio->chip.ngpio)
213		handle_nested_irq(irq_find_mapping(gpio->chip.irq.domain, i));
214
215	return IRQ_HANDLED;
216}
217
218/*
219 * NOP functions
220 */
221static void noop(struct irq_data *data) { }
222
223static int pcf857x_irq_set_wake(struct irq_data *data, unsigned int on)
224{
225	struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
226
227	return irq_set_irq_wake(gpio->client->irq, on);
228}
229
230static void pcf857x_irq_enable(struct irq_data *data)
231{
232	struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
233	irq_hw_number_t hwirq = irqd_to_hwirq(data);
234
235	gpiochip_enable_irq(&gpio->chip, hwirq);
236	gpio->irq_enabled |= (1 << hwirq);
237}
238
239static void pcf857x_irq_disable(struct irq_data *data)
240{
241	struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
242	irq_hw_number_t hwirq = irqd_to_hwirq(data);
243
244	gpio->irq_enabled &= ~(1 << hwirq);
245	gpiochip_disable_irq(&gpio->chip, hwirq);
246}
247
248static void pcf857x_irq_bus_lock(struct irq_data *data)
249{
250	struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
251
252	mutex_lock(&gpio->lock);
253}
254
255static void pcf857x_irq_bus_sync_unlock(struct irq_data *data)
256{
257	struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
258
259	mutex_unlock(&gpio->lock);
260}
261
262static const struct irq_chip pcf857x_irq_chip = {
263	.name			= "pcf857x",
264	.irq_enable		= pcf857x_irq_enable,
265	.irq_disable		= pcf857x_irq_disable,
266	.irq_ack		= noop,
267	.irq_mask		= noop,
268	.irq_unmask		= noop,
269	.irq_set_wake		= pcf857x_irq_set_wake,
270	.irq_bus_lock		= pcf857x_irq_bus_lock,
271	.irq_bus_sync_unlock	= pcf857x_irq_bus_sync_unlock,
272	.flags			= IRQCHIP_IMMUTABLE,
273	GPIOCHIP_IRQ_RESOURCE_HELPERS,
274};
275
276/*-------------------------------------------------------------------------*/
277
278static int pcf857x_probe(struct i2c_client *client)
279{
280	struct gpio_desc *reset_gpio;
281	struct pcf857x *gpio;
282	unsigned int n_latch = 0;
283	int status;
284
285	/* Allocate, initialize, and register this gpio_chip. */
286	gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL);
287	if (!gpio)
288		return -ENOMEM;
289
290	mutex_init(&gpio->lock);
291
292	gpio->chip.base			= -1;
293	gpio->chip.can_sleep		= true;
294	gpio->chip.parent		= &client->dev;
295	gpio->chip.owner		= THIS_MODULE;
296	gpio->chip.get			= pcf857x_get;
297	gpio->chip.get_multiple		= pcf857x_get_multiple;
298	gpio->chip.set			= pcf857x_set;
299	gpio->chip.set_multiple		= pcf857x_set_multiple;
300	gpio->chip.direction_input	= pcf857x_input;
301	gpio->chip.direction_output	= pcf857x_output;
302	gpio->chip.ngpio		= (uintptr_t)i2c_get_match_data(client);
303
304	reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH);
305	if (IS_ERR(reset_gpio))
306		return dev_err_probe(&client->dev, PTR_ERR(reset_gpio),
307				     "failed to get reset GPIO\n");
308
309	if (reset_gpio) {
310		/* Reset already held with devm_gpiod_get_optional with GPIOD_OUT_HIGH */
311		fsleep(4); /* tw(rst) > 4us */
312		gpiod_set_value_cansleep(reset_gpio, 0);
313		fsleep(100); /* trst > 100uS */
314
315		/*
316		 * Performing a reset means "The PCA9670 registers and I2C-bus
317		 * state machine will be held in their default state until the
318		 * RESET input is once again HIGH".
319		 *
320		 * This is the same as writing 1 for all pins, which is the same
321		 * as n_latch=0, the default value of the variable.
322		 */
323	} else {
324		device_property_read_u32(&client->dev, "lines-initial-states",
325					 &n_latch);
326	}
327
328	/* NOTE:  the OnSemi jlc1562b is also largely compatible with
329	 * these parts, notably for output.  It has a low-resolution
330	 * DAC instead of pin change IRQs; and its inputs can be the
331	 * result of comparators.
332	 */
333
334	/* 8574 addresses are 0x20..0x27; 8574a uses 0x38..0x3f;
335	 * 9670, 9672, 9764, and 9764a use quite a variety.
336	 *
337	 * NOTE: we don't distinguish here between *4 and *4a parts.
338	 */
339	if (gpio->chip.ngpio == 8) {
340		gpio->write	= i2c_write_le8;
341		gpio->read	= i2c_read_le8;
342
343		if (!i2c_check_functionality(client->adapter,
344				I2C_FUNC_SMBUS_BYTE))
345			status = -EIO;
346
347		/* fail if there's no chip present */
348		else
349			status = i2c_smbus_read_byte(client);
350
351	/* '75/'75c addresses are 0x20..0x27, just like the '74;
352	 * the '75c doesn't have a current source pulling high.
353	 * 9671, 9673, and 9765 use quite a variety of addresses.
354	 *
355	 * NOTE: we don't distinguish here between '75 and '75c parts.
356	 */
357	} else if (gpio->chip.ngpio == 16) {
358		gpio->write	= i2c_write_le16;
359		gpio->read	= i2c_read_le16;
360
361		if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
362			status = -EIO;
363
364		/* fail if there's no chip present */
365		else
366			status = i2c_read_le16(client);
367
368	} else {
369		dev_dbg(&client->dev, "unsupported number of gpios\n");
370		status = -EINVAL;
371	}
372
373	if (status < 0)
374		goto fail;
375
376	gpio->chip.label = client->name;
377
378	gpio->client = client;
379	i2c_set_clientdata(client, gpio);
380
381	/* NOTE:  these chips have strange "quasi-bidirectional" I/O pins.
382	 * We can't actually know whether a pin is configured (a) as output
383	 * and driving the signal low, or (b) as input and reporting a low
384	 * value ... without knowing the last value written since the chip
385	 * came out of reset (if any).  We can't read the latched output.
386	 *
387	 * In short, the only reliable solution for setting up pin direction
388	 * is to do it explicitly.  The setup() method can do that, but it
389	 * may cause transient glitching since it can't know the last value
390	 * written (some pins may need to be driven low).
391	 *
392	 * Using n_latch avoids that trouble.  When left initialized to zero,
393	 * our software copy of the "latch" then matches the chip's all-ones
394	 * reset state.  Otherwise it flags pins to be driven low.
395	 */
396	gpio->out = ~n_latch;
397	gpio->status = gpio->read(gpio->client);
398
399	/* Enable irqchip if we have an interrupt */
400	if (client->irq) {
401		struct gpio_irq_chip *girq;
402
403		status = devm_request_threaded_irq(&client->dev, client->irq,
404					NULL, pcf857x_irq, IRQF_ONESHOT |
405					IRQF_TRIGGER_FALLING | IRQF_SHARED,
406					dev_name(&client->dev), gpio);
407		if (status)
408			goto fail;
409
410		girq = &gpio->chip.irq;
411		gpio_irq_chip_set_chip(girq, &pcf857x_irq_chip);
412		/* This will let us handle the parent IRQ in the driver */
413		girq->parent_handler = NULL;
414		girq->num_parents = 0;
415		girq->parents = NULL;
416		girq->default_type = IRQ_TYPE_NONE;
417		girq->handler = handle_level_irq;
418		girq->threaded = true;
419	}
420
421	status = devm_gpiochip_add_data(&client->dev, &gpio->chip, gpio);
422	if (status < 0)
423		goto fail;
424
425	dev_info(&client->dev, "probed\n");
426
427	return 0;
428
429fail:
430	dev_dbg(&client->dev, "probe error %d for '%s'\n", status,
431		client->name);
432
433	return status;
434}
435
436static void pcf857x_shutdown(struct i2c_client *client)
437{
438	struct pcf857x *gpio = i2c_get_clientdata(client);
439
440	/* Drive all the I/O lines high */
441	gpio->write(gpio->client, BIT(gpio->chip.ngpio) - 1);
442}
443
444static struct i2c_driver pcf857x_driver = {
445	.driver = {
446		.name	= "pcf857x",
447		.of_match_table = pcf857x_of_table,
448	},
449	.probe = pcf857x_probe,
450	.shutdown = pcf857x_shutdown,
451	.id_table = pcf857x_id,
452};
453
454static int __init pcf857x_init(void)
455{
456	return i2c_add_driver(&pcf857x_driver);
457}
458/* register after i2c postcore initcall and before
459 * subsys initcalls that may rely on these GPIOs
460 */
461subsys_initcall(pcf857x_init);
462
463static void __exit pcf857x_exit(void)
464{
465	i2c_del_driver(&pcf857x_driver);
466}
467module_exit(pcf857x_exit);
468
469MODULE_DESCRIPTION("Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders");
470MODULE_LICENSE("GPL");
471MODULE_AUTHOR("David Brownell");