gpio-omap.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Support functions for OMAP GPIO
   4 *
   5 * Copyright (C) 2003-2005 Nokia Corporation
   6 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
   7 *
   8 * Copyright (C) 2009 Texas Instruments
   9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10 */
  11
  12#include <linux/init.h>
  13#include <linux/module.h>
  14#include <linux/interrupt.h>
  15#include <linux/seq_file.h>
  16#include <linux/syscore_ops.h>
  17#include <linux/err.h>
  18#include <linux/clk.h>
  19#include <linux/io.h>
  20#include <linux/cpu_pm.h>
  21#include <linux/device.h>
  22#include <linux/pm_runtime.h>
  23#include <linux/pm.h>
  24#include <linux/of.h>
  25#include <linux/gpio/driver.h>
  26#include <linux/bitops.h>
  27#include <linux/platform_data/gpio-omap.h>
  28
  29#define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
  30
  31struct gpio_regs {
  32	u32 sysconfig;
  33	u32 irqenable1;
  34	u32 irqenable2;
  35	u32 wake_en;
  36	u32 ctrl;
  37	u32 oe;
  38	u32 leveldetect0;
  39	u32 leveldetect1;
  40	u32 risingdetect;
  41	u32 fallingdetect;
  42	u32 dataout;
  43	u32 debounce;
  44	u32 debounce_en;
  45};
  46
  47struct gpio_bank {
  48	void __iomem *base;
  49	const struct omap_gpio_reg_offs *regs;
  50	struct device *dev;
  51
  52	int irq;
  53	u32 non_wakeup_gpios;
  54	u32 enabled_non_wakeup_gpios;
  55	struct gpio_regs context;
  56	u32 saved_datain;
  57	u32 level_mask;
  58	u32 toggle_mask;
  59	raw_spinlock_t lock;
  60	raw_spinlock_t wa_lock;
  61	struct gpio_chip chip;
  62	struct clk *dbck;
  63	struct notifier_block nb;
  64	unsigned int is_suspended:1;
  65	unsigned int needs_resume:1;
  66	u32 mod_usage;
  67	u32 irq_usage;
  68	u32 dbck_enable_mask;
  69	bool dbck_enabled;
  70	bool is_mpuio;
  71	bool dbck_flag;
  72	bool loses_context;
  73	bool context_valid;
  74	int stride;
  75	u32 width;
  76	int context_loss_count;
  77
  78	void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
  79	int (*get_context_loss_count)(struct device *dev);
  80};
  81
  82#define GPIO_MOD_CTRL_BIT	BIT(0)
  83
  84#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
  85#define LINE_USED(line, offset) (line & (BIT(offset)))
  86
  87static void omap_gpio_unmask_irq(struct irq_data *d);
  88
  89static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
  90{
  91	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  92	return gpiochip_get_data(chip);
  93}
  94
  95static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set)
  96{
  97	u32 val = readl_relaxed(reg);
  98
  99	if (set)
 100		val |= mask;
 101	else
 102		val &= ~mask;
 103
 104	writel_relaxed(val, reg);
 105
 106	return val;
 107}
 108
 109static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
 110				    int is_input)
 111{
 112	bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
 113					 BIT(gpio), is_input);
 114}
 115
 116
 117/* set data out value using dedicate set/clear register */
 118static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
 119				      int enable)
 120{
 121	void __iomem *reg = bank->base;
 122	u32 l = BIT(offset);
 123
 124	if (enable) {
 125		reg += bank->regs->set_dataout;
 126		bank->context.dataout |= l;
 127	} else {
 128		reg += bank->regs->clr_dataout;
 129		bank->context.dataout &= ~l;
 130	}
 131
 132	writel_relaxed(l, reg);
 133}
 134
 135/* set data out value using mask register */
 136static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
 137				       int enable)
 138{
 139	bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
 140					      BIT(offset), enable);
 141}
 142
 143static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
 144{
 145	if (bank->dbck_enable_mask && !bank->dbck_enabled) {
 146		clk_enable(bank->dbck);
 147		bank->dbck_enabled = true;
 148
 149		writel_relaxed(bank->dbck_enable_mask,
 150			     bank->base + bank->regs->debounce_en);
 151	}
 152}
 153
 154static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
 155{
 156	if (bank->dbck_enable_mask && bank->dbck_enabled) {
 157		/*
 158		 * Disable debounce before cutting it's clock. If debounce is
 159		 * enabled but the clock is not, GPIO module seems to be unable
 160		 * to detect events and generate interrupts at least on OMAP3.
 161		 */
 162		writel_relaxed(0, bank->base + bank->regs->debounce_en);
 163
 164		clk_disable(bank->dbck);
 165		bank->dbck_enabled = false;
 166	}
 167}
 168
 169/**
 170 * omap2_set_gpio_debounce - low level gpio debounce time
 171 * @bank: the gpio bank we're acting upon
 172 * @offset: the gpio number on this @bank
 173 * @debounce: debounce time to use
 174 *
 175 * OMAP's debounce time is in 31us steps
 176 *   <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
 177 * so we need to convert and round up to the closest unit.
 178 *
 179 * Return: 0 on success, negative error otherwise.
 180 */
 181static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
 182				   unsigned debounce)
 183{
 184	u32			val;
 185	u32			l;
 186	bool			enable = !!debounce;
 187
 188	if (!bank->dbck_flag)
 189		return -ENOTSUPP;
 190
 191	if (enable) {
 192		debounce = DIV_ROUND_UP(debounce, 31) - 1;
 193		if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
 194			return -EINVAL;
 195	}
 196
 197	l = BIT(offset);
 198
 199	clk_enable(bank->dbck);
 200	writel_relaxed(debounce, bank->base + bank->regs->debounce);
 201
 202	val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
 203	bank->dbck_enable_mask = val;
 204
 205	clk_disable(bank->dbck);
 206	/*
 207	 * Enable debounce clock per module.
 208	 * This call is mandatory because in omap_gpio_request() when
 209	 * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
 210	 * runtime callbck fails to turn on dbck because dbck_enable_mask
 211	 * used within _gpio_dbck_enable() is still not initialized at
 212	 * that point. Therefore we have to enable dbck here.
 213	 */
 214	omap_gpio_dbck_enable(bank);
 215	if (bank->dbck_enable_mask) {
 216		bank->context.debounce = debounce;
 217		bank->context.debounce_en = val;
 218	}
 219
 220	return 0;
 221}
 222
 223/**
 224 * omap_clear_gpio_debounce - clear debounce settings for a gpio
 225 * @bank: the gpio bank we're acting upon
 226 * @offset: the gpio number on this @bank
 227 *
 228 * If a gpio is using debounce, then clear the debounce enable bit and if
 229 * this is the only gpio in this bank using debounce, then clear the debounce
 230 * time too. The debounce clock will also be disabled when calling this function
 231 * if this is the only gpio in the bank using debounce.
 232 */
 233static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
 234{
 235	u32 gpio_bit = BIT(offset);
 236
 237	if (!bank->dbck_flag)
 238		return;
 239
 240	if (!(bank->dbck_enable_mask & gpio_bit))
 241		return;
 242
 243	bank->dbck_enable_mask &= ~gpio_bit;
 244	bank->context.debounce_en &= ~gpio_bit;
 245        writel_relaxed(bank->context.debounce_en,
 246		     bank->base + bank->regs->debounce_en);
 247
 248	if (!bank->dbck_enable_mask) {
 249		bank->context.debounce = 0;
 250		writel_relaxed(bank->context.debounce, bank->base +
 251			     bank->regs->debounce);
 252		clk_disable(bank->dbck);
 253		bank->dbck_enabled = false;
 254	}
 255}
 256
 257/*
 258 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
 259 * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
 260 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
 261 * are capable waking up the system from off mode.
 262 */
 263static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
 264{
 265	u32 no_wake = bank->non_wakeup_gpios;
 266
 267	if (no_wake)
 268		return !!(~no_wake & gpio_mask);
 269
 270	return false;
 271}
 272
 273static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
 274						unsigned trigger)
 275{
 276	void __iomem *base = bank->base;
 277	u32 gpio_bit = BIT(gpio);
 278
 279	omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
 280		      trigger & IRQ_TYPE_LEVEL_LOW);
 281	omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
 282		      trigger & IRQ_TYPE_LEVEL_HIGH);
 283
 284	/*
 285	 * We need the edge detection enabled for to allow the GPIO block
 286	 * to be woken from idle state.  Set the appropriate edge detection
 287	 * in addition to the level detection.
 288	 */
 289	omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
 290		      trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH));
 291	omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
 292		      trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW));
 293
 294	bank->context.leveldetect0 =
 295			readl_relaxed(bank->base + bank->regs->leveldetect0);
 296	bank->context.leveldetect1 =
 297			readl_relaxed(bank->base + bank->regs->leveldetect1);
 298	bank->context.risingdetect =
 299			readl_relaxed(bank->base + bank->regs->risingdetect);
 300	bank->context.fallingdetect =
 301			readl_relaxed(bank->base + bank->regs->fallingdetect);
 302
 303	bank->level_mask = bank->context.leveldetect0 |
 304			   bank->context.leveldetect1;
 305
 306	/* This part needs to be executed always for OMAP{34xx, 44xx} */
 307	if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
 308		/*
 309		 * Log the edge gpio and manually trigger the IRQ
 310		 * after resume if the input level changes
 311		 * to avoid irq lost during PER RET/OFF mode
 312		 * Applies for omap2 non-wakeup gpio and all omap3 gpios
 313		 */
 314		if (trigger & IRQ_TYPE_EDGE_BOTH)
 315			bank->enabled_non_wakeup_gpios |= gpio_bit;
 316		else
 317			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
 318	}
 319}
 320
 321/*
 322 * This only applies to chips that can't do both rising and falling edge
 323 * detection at once.  For all other chips, this function is a noop.
 324 */
 325static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 326{
 327	if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {
 328		void __iomem *reg = bank->base + bank->regs->irqctrl;
 329
 330		writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg);
 331	}
 332}
 333
 334static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
 335				    unsigned trigger)
 336{
 337	void __iomem *reg = bank->base;
 338	u32 l = 0;
 339
 340	if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
 341		omap_set_gpio_trigger(bank, gpio, trigger);
 342	} else if (bank->regs->irqctrl) {
 343		reg += bank->regs->irqctrl;
 344
 345		l = readl_relaxed(reg);
 346		if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
 347			bank->toggle_mask |= BIT(gpio);
 348		if (trigger & IRQ_TYPE_EDGE_RISING)
 349			l |= BIT(gpio);
 350		else if (trigger & IRQ_TYPE_EDGE_FALLING)
 351			l &= ~(BIT(gpio));
 352		else
 353			return -EINVAL;
 354
 355		writel_relaxed(l, reg);
 356	} else if (bank->regs->edgectrl1) {
 357		if (gpio & 0x08)
 358			reg += bank->regs->edgectrl2;
 359		else
 360			reg += bank->regs->edgectrl1;
 361
 362		gpio &= 0x07;
 363		l = readl_relaxed(reg);
 364		l &= ~(3 << (gpio << 1));
 365		if (trigger & IRQ_TYPE_EDGE_RISING)
 366			l |= 2 << (gpio << 1);
 367		if (trigger & IRQ_TYPE_EDGE_FALLING)
 368			l |= BIT(gpio << 1);
 369		writel_relaxed(l, reg);
 370	}
 371	return 0;
 372}
 373
 374static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
 375{
 376	if (bank->regs->pinctrl) {
 377		void __iomem *reg = bank->base + bank->regs->pinctrl;
 378
 379		/* Claim the pin for MPU */
 380		writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
 381	}
 382
 383	if (bank->regs->ctrl && !BANK_USED(bank)) {
 384		void __iomem *reg = bank->base + bank->regs->ctrl;
 385		u32 ctrl;
 386
 387		ctrl = readl_relaxed(reg);
 388		/* Module is enabled, clocks are not gated */
 389		ctrl &= ~GPIO_MOD_CTRL_BIT;
 390		writel_relaxed(ctrl, reg);
 391		bank->context.ctrl = ctrl;
 392	}
 393}
 394
 395static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
 396{
 397	if (bank->regs->ctrl && !BANK_USED(bank)) {
 398		void __iomem *reg = bank->base + bank->regs->ctrl;
 399		u32 ctrl;
 400
 401		ctrl = readl_relaxed(reg);
 402		/* Module is disabled, clocks are gated */
 403		ctrl |= GPIO_MOD_CTRL_BIT;
 404		writel_relaxed(ctrl, reg);
 405		bank->context.ctrl = ctrl;
 406	}
 407}
 408
 409static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
 410{
 411	void __iomem *reg = bank->base + bank->regs->direction;
 412
 413	return readl_relaxed(reg) & BIT(offset);
 414}
 415
 416static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
 417{
 418	if (!LINE_USED(bank->mod_usage, offset)) {
 419		omap_enable_gpio_module(bank, offset);
 420		omap_set_gpio_direction(bank, offset, 1);
 421	}
 422	bank->irq_usage |= BIT(offset);
 423}
 424
 425static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
 426{
 427	struct gpio_bank *bank = omap_irq_data_get_bank(d);
 428	int retval;
 429	unsigned long flags;
 430	unsigned offset = d->hwirq;
 431
 432	if (type & ~IRQ_TYPE_SENSE_MASK)
 433		return -EINVAL;
 434
 435	if (!bank->regs->leveldetect0 &&
 436		(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
 437		return -EINVAL;
 438
 439	raw_spin_lock_irqsave(&bank->lock, flags);
 440	retval = omap_set_gpio_triggering(bank, offset, type);
 441	if (retval) {
 442		raw_spin_unlock_irqrestore(&bank->lock, flags);
 443		goto error;
 444	}
 445	omap_gpio_init_irq(bank, offset);
 446	if (!omap_gpio_is_input(bank, offset)) {
 447		raw_spin_unlock_irqrestore(&bank->lock, flags);
 448		retval = -EINVAL;
 449		goto error;
 450	}
 451	raw_spin_unlock_irqrestore(&bank->lock, flags);
 452
 453	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 454		irq_set_handler_locked(d, handle_level_irq);
 455	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 456		/*
 457		 * Edge IRQs are already cleared/acked in irq_handler and
 458		 * not need to be masked, as result handle_edge_irq()
 459		 * logic is excessed here and may cause lose of interrupts.
 460		 * So just use handle_simple_irq.
 461		 */
 462		irq_set_handler_locked(d, handle_simple_irq);
 463
 464	return 0;
 465
 466error:
 467	return retval;
 468}
 469
 470static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 471{
 472	void __iomem *reg = bank->base;
 473
 474	reg += bank->regs->irqstatus;
 475	writel_relaxed(gpio_mask, reg);
 476
 477	/* Workaround for clearing DSP GPIO interrupts to allow retention */
 478	if (bank->regs->irqstatus2) {
 479		reg = bank->base + bank->regs->irqstatus2;
 480		writel_relaxed(gpio_mask, reg);
 481	}
 482
 483	/* Flush posted write for the irq status to avoid spurious interrupts */
 484	readl_relaxed(reg);
 485}
 486
 487static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
 488					     unsigned offset)
 489{
 490	omap_clear_gpio_irqbank(bank, BIT(offset));
 491}
 492
 493static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
 494{
 495	void __iomem *reg = bank->base;
 496	u32 l;
 497	u32 mask = (BIT(bank->width)) - 1;
 498
 499	reg += bank->regs->irqenable;
 500	l = readl_relaxed(reg);
 501	if (bank->regs->irqenable_inv)
 502		l = ~l;
 503	l &= mask;
 504	return l;
 505}
 506
 507static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
 508					   unsigned offset, int enable)
 509{
 510	void __iomem *reg = bank->base;
 511	u32 gpio_mask = BIT(offset);
 512
 513	if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {
 514		if (enable) {
 515			reg += bank->regs->set_irqenable;
 516			bank->context.irqenable1 |= gpio_mask;
 517		} else {
 518			reg += bank->regs->clr_irqenable;
 519			bank->context.irqenable1 &= ~gpio_mask;
 520		}
 521		writel_relaxed(gpio_mask, reg);
 522	} else {
 523		bank->context.irqenable1 =
 524			omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,
 525				      enable ^ bank->regs->irqenable_inv);
 526	}
 527
 528	/*
 529	 * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM
 530	 * note requiring correlation between the IRQ enable registers and
 531	 * the wakeup registers.  In any case, we want wakeup from idle
 532	 * enabled for the GPIOs which support this feature.
 533	 */
 534	if (bank->regs->wkup_en &&
 535	    (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) {
 536		bank->context.wake_en =
 537			omap_gpio_rmw(bank->base + bank->regs->wkup_en,
 538				      gpio_mask, enable);
 539	}
 540}
 541
 542/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
 543static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 544{
 545	struct gpio_bank *bank = omap_irq_data_get_bank(d);
 546
 547	return irq_set_irq_wake(bank->irq, enable);
 548}
 549
 550/*
 551 * We need to unmask the GPIO bank interrupt as soon as possible to
 552 * avoid missing GPIO interrupts for other lines in the bank.
 553 * Then we need to mask-read-clear-unmask the triggered GPIO lines
 554 * in the bank to avoid missing nested interrupts for a GPIO line.
 555 * If we wait to unmask individual GPIO lines in the bank after the
 556 * line's interrupt handler has been run, we may miss some nested
 557 * interrupts.
 558 */
 559static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
 560{
 561	void __iomem *isr_reg = NULL;
 562	u32 enabled, isr, edge;
 563	unsigned int bit;
 564	struct gpio_bank *bank = gpiobank;
 565	unsigned long wa_lock_flags;
 566	unsigned long lock_flags;
 567
 568	isr_reg = bank->base + bank->regs->irqstatus;
 569	if (WARN_ON(!isr_reg))
 570		goto exit;
 571
 572	if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
 573		      "gpio irq%i while runtime suspended?\n", irq))
 574		return IRQ_NONE;
 575
 576	while (1) {
 577		raw_spin_lock_irqsave(&bank->lock, lock_flags);
 578
 579		enabled = omap_get_gpio_irqbank_mask(bank);
 580		isr = readl_relaxed(isr_reg) & enabled;
 581
 582		/*
 583		 * Clear edge sensitive interrupts before calling handler(s)
 584		 * so subsequent edge transitions are not missed while the
 585		 * handlers are running.
 586		 */
 587		edge = isr & ~bank->level_mask;
 588		if (edge)
 589			omap_clear_gpio_irqbank(bank, edge);
 590
 591		raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
 592
 593		if (!isr)
 594			break;
 595
 596		while (isr) {
 597			bit = __ffs(isr);
 598			isr &= ~(BIT(bit));
 599
 600			raw_spin_lock_irqsave(&bank->lock, lock_flags);
 601			/*
 602			 * Some chips can't respond to both rising and falling
 603			 * at the same time.  If this irq was requested with
 604			 * both flags, we need to flip the ICR data for the IRQ
 605			 * to respond to the IRQ for the opposite direction.
 606			 * This will be indicated in the bank toggle_mask.
 607			 */
 608			if (bank->toggle_mask & (BIT(bit)))
 609				omap_toggle_gpio_edge_triggering(bank, bit);
 610
 611			raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
 612
 613			raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
 614
 615			generic_handle_domain_irq(bank->chip.irq.domain, bit);
 616
 617			raw_spin_unlock_irqrestore(&bank->wa_lock,
 618						   wa_lock_flags);
 619		}
 620	}
 621exit:
 622	return IRQ_HANDLED;
 623}
 624
 625static unsigned int omap_gpio_irq_startup(struct irq_data *d)
 626{
 627	struct gpio_bank *bank = omap_irq_data_get_bank(d);
 628	unsigned long flags;
 629	unsigned offset = d->hwirq;
 630
 631	raw_spin_lock_irqsave(&bank->lock, flags);
 632
 633	if (!LINE_USED(bank->mod_usage, offset))
 634		omap_set_gpio_direction(bank, offset, 1);
 635	omap_enable_gpio_module(bank, offset);
 636	bank->irq_usage |= BIT(offset);
 637
 638	raw_spin_unlock_irqrestore(&bank->lock, flags);
 639	omap_gpio_unmask_irq(d);
 640
 641	return 0;
 642}
 643
 644static void omap_gpio_irq_shutdown(struct irq_data *d)
 645{
 646	struct gpio_bank *bank = omap_irq_data_get_bank(d);
 647	unsigned long flags;
 648	unsigned offset = d->hwirq;
 649
 650	raw_spin_lock_irqsave(&bank->lock, flags);
 651	bank->irq_usage &= ~(BIT(offset));
 652	omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 653	omap_clear_gpio_irqstatus(bank, offset);
 654	omap_set_gpio_irqenable(bank, offset, 0);
 655	if (!LINE_USED(bank->mod_usage, offset))
 656		omap_clear_gpio_debounce(bank, offset);
 657	omap_disable_gpio_module(bank, offset);
 658	raw_spin_unlock_irqrestore(&bank->lock, flags);
 659}
 660
 661static void omap_gpio_irq_bus_lock(struct irq_data *data)
 662{
 663	struct gpio_bank *bank = omap_irq_data_get_bank(data);
 664
 665	pm_runtime_get_sync(bank->chip.parent);
 666}
 667
 668static void gpio_irq_bus_sync_unlock(struct irq_data *data)
 669{
 670	struct gpio_bank *bank = omap_irq_data_get_bank(data);
 671
 672	pm_runtime_put(bank->chip.parent);
 673}
 674
 675static void omap_gpio_mask_irq(struct irq_data *d)
 676{
 677	struct gpio_bank *bank = omap_irq_data_get_bank(d);
 678	unsigned offset = d->hwirq;
 679	unsigned long flags;
 680
 681	raw_spin_lock_irqsave(&bank->lock, flags);
 682	omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 683	omap_set_gpio_irqenable(bank, offset, 0);
 684	raw_spin_unlock_irqrestore(&bank->lock, flags);
 685	gpiochip_disable_irq(&bank->chip, offset);
 686}
 687
 688static void omap_gpio_unmask_irq(struct irq_data *d)
 689{
 690	struct gpio_bank *bank = omap_irq_data_get_bank(d);
 691	unsigned offset = d->hwirq;
 692	u32 trigger = irqd_get_trigger_type(d);
 693	unsigned long flags;
 694
 695	gpiochip_enable_irq(&bank->chip, offset);
 696	raw_spin_lock_irqsave(&bank->lock, flags);
 697	omap_set_gpio_irqenable(bank, offset, 1);
 698
 699	/*
 700	 * For level-triggered GPIOs, clearing must be done after the source
 701	 * is cleared, thus after the handler has run. OMAP4 needs this done
 702	 * after enabing the interrupt to clear the wakeup status.
 703	 */
 704	if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
 705	    trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
 706		omap_clear_gpio_irqstatus(bank, offset);
 707
 708	if (trigger)
 709		omap_set_gpio_triggering(bank, offset, trigger);
 710
 711	raw_spin_unlock_irqrestore(&bank->lock, flags);
 712}
 713
 714static void omap_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
 715{
 716	struct gpio_bank *bank = omap_irq_data_get_bank(d);
 717
 718	seq_puts(p, dev_name(bank->dev));
 719}
 720
 721static const struct irq_chip omap_gpio_irq_chip = {
 722	.irq_startup = omap_gpio_irq_startup,
 723	.irq_shutdown = omap_gpio_irq_shutdown,
 724	.irq_mask = omap_gpio_mask_irq,
 725	.irq_unmask = omap_gpio_unmask_irq,
 726	.irq_set_type = omap_gpio_irq_type,
 727	.irq_set_wake = omap_gpio_wake_enable,
 728	.irq_bus_lock = omap_gpio_irq_bus_lock,
 729	.irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
 730	.irq_print_chip = omap_gpio_irq_print_chip,
 731	.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
 732	 GPIOCHIP_IRQ_RESOURCE_HELPERS,
 733};
 734
 735static const struct irq_chip omap_gpio_irq_chip_nowake = {
 736	.irq_startup = omap_gpio_irq_startup,
 737	.irq_shutdown = omap_gpio_irq_shutdown,
 738	.irq_mask = omap_gpio_mask_irq,
 739	.irq_unmask = omap_gpio_unmask_irq,
 740	.irq_set_type = omap_gpio_irq_type,
 741	.irq_bus_lock = omap_gpio_irq_bus_lock,
 742	.irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
 743	.irq_print_chip = omap_gpio_irq_print_chip,
 744	.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
 745	 GPIOCHIP_IRQ_RESOURCE_HELPERS,
 746};
 747
 748/*---------------------------------------------------------------------*/
 749
 750static int omap_mpuio_suspend_noirq(struct device *dev)
 751{
 752	struct gpio_bank	*bank = dev_get_drvdata(dev);
 753	void __iomem		*mask_reg = bank->base +
 754					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 755	unsigned long		flags;
 756
 757	raw_spin_lock_irqsave(&bank->lock, flags);
 758	writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
 759	raw_spin_unlock_irqrestore(&bank->lock, flags);
 760
 761	return 0;
 762}
 763
 764static int omap_mpuio_resume_noirq(struct device *dev)
 765{
 766	struct gpio_bank	*bank = dev_get_drvdata(dev);
 767	void __iomem		*mask_reg = bank->base +
 768					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 769	unsigned long		flags;
 770
 771	raw_spin_lock_irqsave(&bank->lock, flags);
 772	writel_relaxed(bank->context.wake_en, mask_reg);
 773	raw_spin_unlock_irqrestore(&bank->lock, flags);
 774
 775	return 0;
 776}
 777
 778static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
 779	.suspend_noirq = omap_mpuio_suspend_noirq,
 780	.resume_noirq = omap_mpuio_resume_noirq,
 781};
 782
 783/* use platform_driver for this. */
 784static struct platform_driver omap_mpuio_driver = {
 785	.driver		= {
 786		.name	= "mpuio",
 787		.pm	= &omap_mpuio_dev_pm_ops,
 788	},
 789};
 790
 791static struct platform_device omap_mpuio_device = {
 792	.name		= "mpuio",
 793	.id		= -1,
 794	.dev = {
 795		.driver = &omap_mpuio_driver.driver,
 796	}
 797	/* could list the /proc/iomem resources */
 798};
 799
 800static inline void omap_mpuio_init(struct gpio_bank *bank)
 801{
 802	static bool registered;
 803
 804	platform_set_drvdata(&omap_mpuio_device, bank);
 805	if (!registered) {
 806		(void)platform_device_register(&omap_mpuio_device);
 807		registered = true;
 808	}
 809}
 810
 811/*---------------------------------------------------------------------*/
 812
 813static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 814{
 815	struct gpio_bank *bank = gpiochip_get_data(chip);
 816	unsigned long flags;
 817
 818	pm_runtime_get_sync(chip->parent);
 819
 820	raw_spin_lock_irqsave(&bank->lock, flags);
 821	omap_enable_gpio_module(bank, offset);
 822	bank->mod_usage |= BIT(offset);
 823	raw_spin_unlock_irqrestore(&bank->lock, flags);
 824
 825	return 0;
 826}
 827
 828static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 829{
 830	struct gpio_bank *bank = gpiochip_get_data(chip);
 831	unsigned long flags;
 832
 833	raw_spin_lock_irqsave(&bank->lock, flags);
 834	bank->mod_usage &= ~(BIT(offset));
 835	if (!LINE_USED(bank->irq_usage, offset)) {
 836		omap_set_gpio_direction(bank, offset, 1);
 837		omap_clear_gpio_debounce(bank, offset);
 838	}
 839	omap_disable_gpio_module(bank, offset);
 840	raw_spin_unlock_irqrestore(&bank->lock, flags);
 841
 842	pm_runtime_put(chip->parent);
 843}
 844
 845static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
 846{
 847	struct gpio_bank *bank = gpiochip_get_data(chip);
 848
 849	if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset))
 850		return GPIO_LINE_DIRECTION_IN;
 851
 852	return GPIO_LINE_DIRECTION_OUT;
 853}
 854
 855static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
 856{
 857	struct gpio_bank *bank;
 858	unsigned long flags;
 859
 860	bank = gpiochip_get_data(chip);
 861	raw_spin_lock_irqsave(&bank->lock, flags);
 862	omap_set_gpio_direction(bank, offset, 1);
 863	raw_spin_unlock_irqrestore(&bank->lock, flags);
 864	return 0;
 865}
 866
 867static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
 868{
 869	struct gpio_bank *bank = gpiochip_get_data(chip);
 870	void __iomem *reg;
 871
 872	if (omap_gpio_is_input(bank, offset))
 873		reg = bank->base + bank->regs->datain;
 874	else
 875		reg = bank->base + bank->regs->dataout;
 876
 877	return (readl_relaxed(reg) & BIT(offset)) != 0;
 878}
 879
 880static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
 881{
 882	struct gpio_bank *bank;
 883	unsigned long flags;
 884
 885	bank = gpiochip_get_data(chip);
 886	raw_spin_lock_irqsave(&bank->lock, flags);
 887	bank->set_dataout(bank, offset, value);
 888	omap_set_gpio_direction(bank, offset, 0);
 889	raw_spin_unlock_irqrestore(&bank->lock, flags);
 890	return 0;
 891}
 892
 893static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
 894				  unsigned long *bits)
 895{
 896	struct gpio_bank *bank = gpiochip_get_data(chip);
 897	void __iomem *base = bank->base;
 898	u32 direction, m, val = 0;
 899
 900	direction = readl_relaxed(base + bank->regs->direction);
 901
 902	m = direction & *mask;
 903	if (m)
 904		val |= readl_relaxed(base + bank->regs->datain) & m;
 905
 906	m = ~direction & *mask;
 907	if (m)
 908		val |= readl_relaxed(base + bank->regs->dataout) & m;
 909
 910	*bits = val;
 911
 912	return 0;
 913}
 914
 915static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
 916			      unsigned debounce)
 917{
 918	struct gpio_bank *bank;
 919	unsigned long flags;
 920	int ret;
 921
 922	bank = gpiochip_get_data(chip);
 923
 924	raw_spin_lock_irqsave(&bank->lock, flags);
 925	ret = omap2_set_gpio_debounce(bank, offset, debounce);
 926	raw_spin_unlock_irqrestore(&bank->lock, flags);
 927
 928	if (ret)
 929		dev_info(chip->parent,
 930			 "Could not set line %u debounce to %u microseconds (%d)",
 931			 offset, debounce, ret);
 932
 933	return ret;
 934}
 935
 936static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
 937				unsigned long config)
 938{
 939	u32 debounce;
 940	int ret = -ENOTSUPP;
 941
 942	switch (pinconf_to_config_param(config)) {
 943	case PIN_CONFIG_BIAS_DISABLE:
 944	case PIN_CONFIG_BIAS_PULL_UP:
 945	case PIN_CONFIG_BIAS_PULL_DOWN:
 946		ret = gpiochip_generic_config(chip, offset, config);
 947		break;
 948	case PIN_CONFIG_INPUT_DEBOUNCE:
 949		debounce = pinconf_to_config_argument(config);
 950		ret = omap_gpio_debounce(chip, offset, debounce);
 951		break;
 952	default:
 953		break;
 954	}
 955
 956	return ret;
 957}
 958
 959static int omap_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
 960{
 961	struct gpio_bank *bank;
 962	unsigned long flags;
 963
 964	bank = gpiochip_get_data(chip);
 965	raw_spin_lock_irqsave(&bank->lock, flags);
 966	bank->set_dataout(bank, offset, value);
 967	raw_spin_unlock_irqrestore(&bank->lock, flags);
 968
 969	return 0;
 970}
 971
 972static int omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
 973				  unsigned long *bits)
 974{
 975	struct gpio_bank *bank = gpiochip_get_data(chip);
 976	void __iomem *reg = bank->base + bank->regs->dataout;
 977	unsigned long flags;
 978	u32 l;
 979
 980	raw_spin_lock_irqsave(&bank->lock, flags);
 981	l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
 982	writel_relaxed(l, reg);
 983	bank->context.dataout = l;
 984	raw_spin_unlock_irqrestore(&bank->lock, flags);
 985
 986	return 0;
 987}
 988
 989/*---------------------------------------------------------------------*/
 990
 991static void omap_gpio_show_rev(struct gpio_bank *bank)
 992{
 993	static bool called;
 994	u32 rev;
 995
 996	if (called || bank->regs->revision == USHRT_MAX)
 997		return;
 998
 999	rev = readw_relaxed(bank->base + bank->regs->revision);
1000	pr_info("OMAP GPIO hardware version %d.%d\n",
1001		(rev >> 4) & 0x0f, rev & 0x0f);
1002
1003	called = true;
1004}
1005
1006static void omap_gpio_mod_init(struct gpio_bank *bank)
1007{
1008	void __iomem *base = bank->base;
1009	u32 l = 0xffffffff;
1010
1011	if (bank->width == 16)
1012		l = 0xffff;
1013
1014	if (bank->is_mpuio) {
1015		writel_relaxed(l, bank->base + bank->regs->irqenable);
1016		return;
1017	}
1018
1019	omap_gpio_rmw(base + bank->regs->irqenable, l,
1020		      bank->regs->irqenable_inv);
1021	omap_gpio_rmw(base + bank->regs->irqstatus, l,
1022		      !bank->regs->irqenable_inv);
1023	if (bank->regs->debounce_en)
1024		writel_relaxed(0, base + bank->regs->debounce_en);
1025
1026	/* Save OE default value (0xffffffff) in the context */
1027	bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1028	 /* Initialize interface clk ungated, module enabled */
1029	if (bank->regs->ctrl)
1030		writel_relaxed(0, base + bank->regs->ctrl);
1031}
1032
1033static int omap_gpio_chip_init(struct gpio_bank *bank, struct device *pm_dev)
1034{
1035	struct gpio_irq_chip *irq;
1036	static int gpio;
1037	const char *label;
1038	int ret;
1039
1040	/*
1041	 * REVISIT eventually switch from OMAP-specific gpio structs
1042	 * over to the generic ones
1043	 */
1044	bank->chip.request = omap_gpio_request;
1045	bank->chip.free = omap_gpio_free;
1046	bank->chip.get_direction = omap_gpio_get_direction;
1047	bank->chip.direction_input = omap_gpio_input;
1048	bank->chip.get = omap_gpio_get;
1049	bank->chip.get_multiple = omap_gpio_get_multiple;
1050	bank->chip.direction_output = omap_gpio_output;
1051	bank->chip.set_config = omap_gpio_set_config;
1052	bank->chip.set = omap_gpio_set;
1053	bank->chip.set_multiple = omap_gpio_set_multiple;
1054	if (bank->is_mpuio) {
1055		bank->chip.label = "mpuio";
1056		if (bank->regs->wkup_en)
1057			bank->chip.parent = &omap_mpuio_device.dev;
1058	} else {
1059		label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1060				       gpio, gpio + bank->width - 1);
1061		if (!label)
1062			return -ENOMEM;
1063		bank->chip.label = label;
1064	}
1065	bank->chip.base = -1;
1066	bank->chip.ngpio = bank->width;
1067
1068	irq = &bank->chip.irq;
1069	/* MPUIO is a bit different, reading IRQ status clears it */
1070	if (bank->is_mpuio && !bank->regs->wkup_en)
1071		gpio_irq_chip_set_chip(irq, &omap_gpio_irq_chip_nowake);
1072	else
1073		gpio_irq_chip_set_chip(irq, &omap_gpio_irq_chip);
1074	irq->handler = handle_bad_irq;
1075	irq->default_type = IRQ_TYPE_NONE;
1076	irq->num_parents = 1;
1077	irq->parents = &bank->irq;
1078
1079	ret = gpiochip_add_data(&bank->chip, bank);
1080	if (ret)
1081		return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n");
1082
1083	irq_domain_set_pm_device(bank->chip.irq.domain, pm_dev);
1084	ret = devm_request_irq(bank->chip.parent, bank->irq,
1085			       omap_gpio_irq_handler,
1086			       0, dev_name(bank->chip.parent), bank);
1087	if (ret)
1088		gpiochip_remove(&bank->chip);
1089
1090	if (!bank->is_mpuio)
1091		gpio += bank->width;
1092
1093	return ret;
1094}
1095
1096static void omap_gpio_init_context(struct gpio_bank *p)
1097{
1098	const struct omap_gpio_reg_offs *regs = p->regs;
1099	void __iomem *base = p->base;
1100
1101	p->context.sysconfig	= readl_relaxed(base + regs->sysconfig);
1102	p->context.ctrl		= readl_relaxed(base + regs->ctrl);
1103	p->context.oe		= readl_relaxed(base + regs->direction);
1104	p->context.wake_en	= readl_relaxed(base + regs->wkup_en);
1105	p->context.leveldetect0	= readl_relaxed(base + regs->leveldetect0);
1106	p->context.leveldetect1	= readl_relaxed(base + regs->leveldetect1);
1107	p->context.risingdetect	= readl_relaxed(base + regs->risingdetect);
1108	p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1109	p->context.irqenable1	= readl_relaxed(base + regs->irqenable);
1110	p->context.irqenable2	= readl_relaxed(base + regs->irqenable2);
1111	p->context.dataout	= readl_relaxed(base + regs->dataout);
1112
1113	p->context_valid = true;
1114}
1115
1116static void omap_gpio_restore_context(struct gpio_bank *bank)
1117{
1118	const struct omap_gpio_reg_offs *regs = bank->regs;
1119	void __iomem *base = bank->base;
1120
1121	writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);
1122	writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
1123	writel_relaxed(bank->context.ctrl, base + regs->ctrl);
1124	writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
1125	writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
1126	writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
1127	writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
1128	writel_relaxed(bank->context.dataout, base + regs->dataout);
1129	writel_relaxed(bank->context.oe, base + regs->direction);
1130
1131	if (bank->dbck_enable_mask) {
1132		writel_relaxed(bank->context.debounce, base + regs->debounce);
1133		writel_relaxed(bank->context.debounce_en,
1134			       base + regs->debounce_en);
1135	}
1136
1137	writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
1138	writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
1139}
1140
1141static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1142{
1143	struct device *dev = bank->chip.parent;
1144	void __iomem *base = bank->base;
1145	u32 mask, nowake;
1146
1147	bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1148
1149	/* Save syconfig, it's runtime value can be different from init value */
1150	if (bank->loses_context)
1151		bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig);
1152
1153	if (!bank->enabled_non_wakeup_gpios)
1154		goto update_gpio_context_count;
1155
1156	/* Check for pending EDGE_FALLING, ignore EDGE_BOTH */
1157	mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect;
1158	mask &= ~bank->context.risingdetect;
1159	bank->saved_datain |= mask;
1160
1161	/* Check for pending EDGE_RISING, ignore EDGE_BOTH */
1162	mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect;
1163	mask &= ~bank->context.fallingdetect;
1164	bank->saved_datain &= ~mask;
1165
1166	if (!may_lose_context)
1167		goto update_gpio_context_count;
1168
1169	/*
1170	 * If going to OFF, remove triggering for all wkup domain
1171	 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1172	 * generated.  See OMAP2420 Errata item 1.101.
1173	 */
1174	if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
1175		nowake = bank->enabled_non_wakeup_gpios;
1176		omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
1177		omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
1178	}
1179
1180update_gpio_context_count:
1181	if (bank->get_context_loss_count)
1182		bank->context_loss_count =
1183				bank->get_context_loss_count(dev);
1184
1185	omap_gpio_dbck_disable(bank);
1186}
1187
1188static void omap_gpio_unidle(struct gpio_bank *bank)
1189{
1190	struct device *dev = bank->chip.parent;
1191	u32 l = 0, gen, gen0, gen1;
1192	int c;
1193
1194	/*
1195	 * On the first resume during the probe, the context has not
1196	 * been initialised and so initialise it now. Also initialise
1197	 * the context loss count.
1198	 */
1199	if (bank->loses_context && !bank->context_valid) {
1200		omap_gpio_init_context(bank);
1201
1202		if (bank->get_context_loss_count)
1203			bank->context_loss_count =
1204				bank->get_context_loss_count(dev);
1205	}
1206
1207	omap_gpio_dbck_enable(bank);
1208
1209	if (bank->loses_context) {
1210		if (!bank->get_context_loss_count) {
1211			omap_gpio_restore_context(bank);
1212		} else {
1213			c = bank->get_context_loss_count(dev);
1214			if (c != bank->context_loss_count) {
1215				omap_gpio_restore_context(bank);
1216			} else {
1217				return;
1218			}
1219		}
1220	} else {
1221		/* Restore changes done for OMAP2420 errata 1.101 */
1222		writel_relaxed(bank->context.fallingdetect,
1223			       bank->base + bank->regs->fallingdetect);
1224		writel_relaxed(bank->context.risingdetect,
1225			       bank->base + bank->regs->risingdetect);
1226	}
1227
1228	l = readl_relaxed(bank->base + bank->regs->datain);
1229
1230	/*
1231	 * Check if any of the non-wakeup interrupt GPIOs have changed
1232	 * state.  If so, generate an IRQ by software.  This is
1233	 * horribly racy, but it's the best we can do to work around
1234	 * this silicon bug.
1235	 */
1236	l ^= bank->saved_datain;
1237	l &= bank->enabled_non_wakeup_gpios;
1238
1239	/*
1240	 * No need to generate IRQs for the rising edge for gpio IRQs
1241	 * configured with falling edge only; and vice versa.
1242	 */
1243	gen0 = l & bank->context.fallingdetect;
1244	gen0 &= bank->saved_datain;
1245
1246	gen1 = l & bank->context.risingdetect;
1247	gen1 &= ~(bank->saved_datain);
1248
1249	/* FIXME: Consider GPIO IRQs with level detections properly! */
1250	gen = l & (~(bank->context.fallingdetect) &
1251					 ~(bank->context.risingdetect));
1252	/* Consider all GPIO IRQs needed to be updated */
1253	gen |= gen0 | gen1;
1254
1255	if (gen) {
1256		u32 old0, old1;
1257
1258		old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1259		old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1260
1261		if (!bank->regs->irqstatus_raw0) {
1262			writel_relaxed(old0 | gen, bank->base +
1263						bank->regs->leveldetect0);
1264			writel_relaxed(old1 | gen, bank->base +
1265						bank->regs->leveldetect1);
1266		}
1267
1268		if (bank->regs->irqstatus_raw0) {
1269			writel_relaxed(old0 | l, bank->base +
1270						bank->regs->leveldetect0);
1271			writel_relaxed(old1 | l, bank->base +
1272						bank->regs->leveldetect1);
1273		}
1274		writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1275		writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1276	}
1277}
1278
1279static int gpio_omap_cpu_notifier(struct notifier_block *nb,
1280				  unsigned long cmd, void *v)
1281{
1282	struct gpio_bank *bank;
1283	unsigned long flags;
1284	int ret = NOTIFY_OK;
1285	u32 isr, mask;
1286
1287	bank = container_of(nb, struct gpio_bank, nb);
1288
1289	raw_spin_lock_irqsave(&bank->lock, flags);
1290	if (bank->is_suspended)
1291		goto out_unlock;
1292
1293	switch (cmd) {
1294	case CPU_CLUSTER_PM_ENTER:
1295		mask = omap_get_gpio_irqbank_mask(bank);
1296		isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask;
1297		if (isr) {
1298			ret = NOTIFY_BAD;
1299			break;
1300		}
1301		omap_gpio_idle(bank, true);
1302		break;
1303	case CPU_CLUSTER_PM_ENTER_FAILED:
1304	case CPU_CLUSTER_PM_EXIT:
1305		omap_gpio_unidle(bank);
1306		break;
1307	}
1308
1309out_unlock:
1310	raw_spin_unlock_irqrestore(&bank->lock, flags);
1311
1312	return ret;
1313}
1314
1315static const struct omap_gpio_reg_offs omap2_gpio_regs = {
1316	.revision =		OMAP24XX_GPIO_REVISION,
1317	.sysconfig =		OMAP24XX_GPIO_SYSCONFIG,
1318	.direction =		OMAP24XX_GPIO_OE,
1319	.datain =		OMAP24XX_GPIO_DATAIN,
1320	.dataout =		OMAP24XX_GPIO_DATAOUT,
1321	.set_dataout =		OMAP24XX_GPIO_SETDATAOUT,
1322	.clr_dataout =		OMAP24XX_GPIO_CLEARDATAOUT,
1323	.irqstatus =		OMAP24XX_GPIO_IRQSTATUS1,
1324	.irqstatus2 =		OMAP24XX_GPIO_IRQSTATUS2,
1325	.irqenable =		OMAP24XX_GPIO_IRQENABLE1,
1326	.irqenable2 =		OMAP24XX_GPIO_IRQENABLE2,
1327	.set_irqenable =	OMAP24XX_GPIO_SETIRQENABLE1,
1328	.clr_irqenable =	OMAP24XX_GPIO_CLEARIRQENABLE1,
1329	.debounce =		OMAP24XX_GPIO_DEBOUNCE_VAL,
1330	.debounce_en =		OMAP24XX_GPIO_DEBOUNCE_EN,
1331	.ctrl =			OMAP24XX_GPIO_CTRL,
1332	.wkup_en =		OMAP24XX_GPIO_WAKE_EN,
1333	.leveldetect0 =		OMAP24XX_GPIO_LEVELDETECT0,
1334	.leveldetect1 =		OMAP24XX_GPIO_LEVELDETECT1,
1335	.risingdetect =		OMAP24XX_GPIO_RISINGDETECT,
1336	.fallingdetect =	OMAP24XX_GPIO_FALLINGDETECT,
1337};
1338
1339static const struct omap_gpio_reg_offs omap4_gpio_regs = {
1340	.revision =		OMAP4_GPIO_REVISION,
1341	.sysconfig =		OMAP4_GPIO_SYSCONFIG,
1342	.direction =		OMAP4_GPIO_OE,
1343	.datain =		OMAP4_GPIO_DATAIN,
1344	.dataout =		OMAP4_GPIO_DATAOUT,
1345	.set_dataout =		OMAP4_GPIO_SETDATAOUT,
1346	.clr_dataout =		OMAP4_GPIO_CLEARDATAOUT,
1347	.irqstatus =		OMAP4_GPIO_IRQSTATUS0,
1348	.irqstatus2 =		OMAP4_GPIO_IRQSTATUS1,
1349	.irqstatus_raw0 =	OMAP4_GPIO_IRQSTATUSRAW0,
1350	.irqstatus_raw1 =	OMAP4_GPIO_IRQSTATUSRAW1,
1351	.irqenable =		OMAP4_GPIO_IRQSTATUSSET0,
1352	.irqenable2 =		OMAP4_GPIO_IRQSTATUSSET1,
1353	.set_irqenable =	OMAP4_GPIO_IRQSTATUSSET0,
1354	.clr_irqenable =	OMAP4_GPIO_IRQSTATUSCLR0,
1355	.debounce =		OMAP4_GPIO_DEBOUNCINGTIME,
1356	.debounce_en =		OMAP4_GPIO_DEBOUNCENABLE,
1357	.ctrl =			OMAP4_GPIO_CTRL,
1358	.wkup_en =		OMAP4_GPIO_IRQWAKEN0,
1359	.leveldetect0 =		OMAP4_GPIO_LEVELDETECT0,
1360	.leveldetect1 =		OMAP4_GPIO_LEVELDETECT1,
1361	.risingdetect =		OMAP4_GPIO_RISINGDETECT,
1362	.fallingdetect =	OMAP4_GPIO_FALLINGDETECT,
1363};
1364
1365static const struct omap_gpio_platform_data omap2_pdata = {
1366	.regs = &omap2_gpio_regs,
1367	.bank_width = 32,
1368	.dbck_flag = false,
1369};
1370
1371static const struct omap_gpio_platform_data omap3_pdata = {
1372	.regs = &omap2_gpio_regs,
1373	.bank_width = 32,
1374	.dbck_flag = true,
1375};
1376
1377static const struct omap_gpio_platform_data omap4_pdata = {
1378	.regs = &omap4_gpio_regs,
1379	.bank_width = 32,
1380	.dbck_flag = true,
1381};
1382
1383static const struct of_device_id omap_gpio_match[] = {
1384	{
1385		.compatible = "ti,omap4-gpio",
1386		.data = &omap4_pdata,
1387	},
1388	{
1389		.compatible = "ti,omap3-gpio",
1390		.data = &omap3_pdata,
1391	},
1392	{
1393		.compatible = "ti,omap2-gpio",
1394		.data = &omap2_pdata,
1395	},
1396	{ },
1397};
1398MODULE_DEVICE_TABLE(of, omap_gpio_match);
1399
1400static int omap_gpio_probe(struct platform_device *pdev)
1401{
1402	struct device *dev = &pdev->dev;
1403	struct device_node *node = dev->of_node;
1404	const struct omap_gpio_platform_data *pdata;
1405	struct gpio_bank *bank;
1406	int ret;
1407
1408	pdata = device_get_match_data(dev);
1409
1410	pdata = pdata ?: dev_get_platdata(dev);
1411	if (!pdata)
1412		return -EINVAL;
1413
1414	bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1415	if (!bank)
1416		return -ENOMEM;
1417
1418	bank->dev = dev;
1419
1420	bank->irq = platform_get_irq(pdev, 0);
1421	if (bank->irq < 0)
1422		return bank->irq;
1423
1424	bank->chip.parent = dev;
1425	bank->chip.owner = THIS_MODULE;
1426	bank->dbck_flag = pdata->dbck_flag;
1427	bank->stride = pdata->bank_stride;
1428	bank->width = pdata->bank_width;
1429	bank->is_mpuio = pdata->is_mpuio;
1430	bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1431	bank->regs = pdata->regs;
1432
1433	if (node) {
1434		if (!of_property_read_bool(node, "ti,gpio-always-on"))
1435			bank->loses_context = true;
1436	} else {
1437		bank->loses_context = pdata->loses_context;
1438
1439		if (bank->loses_context)
1440			bank->get_context_loss_count =
1441				pdata->get_context_loss_count;
1442	}
1443
1444	if (bank->regs->set_dataout && bank->regs->clr_dataout)
1445		bank->set_dataout = omap_set_gpio_dataout_reg;
1446	else
1447		bank->set_dataout = omap_set_gpio_dataout_mask;
1448
1449	raw_spin_lock_init(&bank->lock);
1450	raw_spin_lock_init(&bank->wa_lock);
1451
1452	/* Static mapping, never released */
1453	bank->base = devm_platform_ioremap_resource(pdev, 0);
1454	if (IS_ERR(bank->base)) {
1455		return PTR_ERR(bank->base);
1456	}
1457
1458	if (bank->dbck_flag) {
1459		bank->dbck = devm_clk_get(dev, "dbclk");
1460		if (IS_ERR(bank->dbck)) {
1461			dev_err(dev,
1462				"Could not get gpio dbck. Disable debounce\n");
1463			bank->dbck_flag = false;
1464		} else {
1465			clk_prepare(bank->dbck);
1466		}
1467	}
1468
1469	platform_set_drvdata(pdev, bank);
1470
1471	pm_runtime_enable(dev);
1472	pm_runtime_get_sync(dev);
1473
1474	if (bank->is_mpuio)
1475		omap_mpuio_init(bank);
1476
1477	omap_gpio_mod_init(bank);
1478
1479	ret = omap_gpio_chip_init(bank, dev);
1480	if (ret) {
1481		pm_runtime_put_sync(dev);
1482		pm_runtime_disable(dev);
1483		if (bank->dbck_flag)
1484			clk_unprepare(bank->dbck);
1485		return ret;
1486	}
1487
1488	omap_gpio_show_rev(bank);
1489
1490	bank->nb.notifier_call = gpio_omap_cpu_notifier;
1491	cpu_pm_register_notifier(&bank->nb);
1492
1493	pm_runtime_put(dev);
1494
1495	return 0;
1496}
1497
1498static void omap_gpio_remove(struct platform_device *pdev)
1499{
1500	struct gpio_bank *bank = platform_get_drvdata(pdev);
1501
1502	cpu_pm_unregister_notifier(&bank->nb);
1503	gpiochip_remove(&bank->chip);
1504	pm_runtime_disable(&pdev->dev);
1505	if (bank->dbck_flag)
1506		clk_unprepare(bank->dbck);
1507}
1508
1509static int omap_gpio_runtime_suspend(struct device *dev)
1510{
1511	struct gpio_bank *bank = dev_get_drvdata(dev);
1512	unsigned long flags;
1513
1514	raw_spin_lock_irqsave(&bank->lock, flags);
1515	omap_gpio_idle(bank, true);
1516	bank->is_suspended = true;
1517	raw_spin_unlock_irqrestore(&bank->lock, flags);
1518
1519	return 0;
1520}
1521
1522static int omap_gpio_runtime_resume(struct device *dev)
1523{
1524	struct gpio_bank *bank = dev_get_drvdata(dev);
1525	unsigned long flags;
1526
1527	raw_spin_lock_irqsave(&bank->lock, flags);
1528	omap_gpio_unidle(bank);
1529	bank->is_suspended = false;
1530	raw_spin_unlock_irqrestore(&bank->lock, flags);
1531
1532	return 0;
1533}
1534
1535static int omap_gpio_suspend(struct device *dev)
1536{
1537	struct gpio_bank *bank = dev_get_drvdata(dev);
1538
1539	if (bank->is_suspended)
1540		return 0;
1541
1542	bank->needs_resume = 1;
1543
1544	return omap_gpio_runtime_suspend(dev);
1545}
1546
1547static int omap_gpio_resume(struct device *dev)
1548{
1549	struct gpio_bank *bank = dev_get_drvdata(dev);
1550
1551	if (!bank->needs_resume)
1552		return 0;
1553
1554	bank->needs_resume = 0;
1555
1556	return omap_gpio_runtime_resume(dev);
1557}
1558
1559static const struct dev_pm_ops gpio_pm_ops = {
1560	RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, NULL)
1561	LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
1562};
1563
1564static struct platform_driver omap_gpio_driver = {
1565	.probe		= omap_gpio_probe,
1566	.remove		= omap_gpio_remove,
1567	.driver		= {
1568		.name	= "omap_gpio",
1569		.pm	= pm_ptr(&gpio_pm_ops),
1570		.of_match_table = omap_gpio_match,
1571	},
1572};
1573
1574/*
1575 * gpio driver register needs to be done before
1576 * machine_init functions access gpio APIs.
1577 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1578 */
1579static int __init omap_gpio_drv_reg(void)
1580{
1581	int ret;
1582
1583	ret = platform_driver_register(&omap_mpuio_driver);
1584	if (ret)
1585		return ret;
1586
1587	ret = platform_driver_register(&omap_gpio_driver);
1588	if (ret)
1589		platform_driver_unregister(&omap_mpuio_driver);
1590
1591	return ret;
1592}
1593postcore_initcall(omap_gpio_drv_reg);
1594
1595static void __exit omap_gpio_exit(void)
1596{
1597	platform_driver_unregister(&omap_gpio_driver);
1598	platform_driver_unregister(&omap_mpuio_driver);
1599}
1600module_exit(omap_gpio_exit);
1601
1602MODULE_DESCRIPTION("omap gpio driver");
1603MODULE_ALIAS("platform:gpio-omap");
1604MODULE_LICENSE("GPL v2");