gpio-octeon.c

  1/*
  2 * This file is subject to the terms and conditions of the GNU General Public
  3 * License.  See the file "COPYING" in the main directory of this archive
  4 * for more details.
  5 *
  6 * Copyright (C) 2011, 2012 Cavium Inc.
  7 */
  8
  9#include <linux/platform_device.h>
 10#include <linux/kernel.h>
 11#include <linux/module.h>
 12#include <linux/gpio/driver.h>
 13#include <linux/io.h>
 14
 15#include <asm/octeon/octeon.h>
 16#include <asm/octeon/cvmx-gpio-defs.h>
 17
 18#define RX_DAT 0x80
 19#define TX_SET 0x88
 20#define TX_CLEAR 0x90
 21/*
 22 * The address offset of the GPIO configuration register for a given
 23 * line.
 24 */
 25static unsigned int bit_cfg_reg(unsigned int offset)
 26{
 27	/*
 28	 * The register stride is 8, with a discontinuity after the
 29	 * first 16.
 30	 */
 31	if (offset < 16)
 32		return 8 * offset;
 33	else
 34		return 8 * (offset - 16) + 0x100;
 35}
 36
 37struct octeon_gpio {
 38	struct gpio_chip chip;
 39	u64 register_base;
 40};
 41
 42static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
 43{
 44	struct octeon_gpio *gpio = gpiochip_get_data(chip);
 45
 46	cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
 47	return 0;
 48}
 49
 50static int octeon_gpio_set(struct gpio_chip *chip, unsigned int offset,
 51			   int value)
 52{
 53	struct octeon_gpio *gpio = gpiochip_get_data(chip);
 54	u64 mask = 1ull << offset;
 55	u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
 56	cvmx_write_csr(reg, mask);
 57
 58	return 0;
 59}
 60
 61static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
 62			       int value)
 63{
 64	struct octeon_gpio *gpio = gpiochip_get_data(chip);
 65	union cvmx_gpio_bit_cfgx cfgx;
 66
 67	octeon_gpio_set(chip, offset, value);
 68
 69	cfgx.u64 = 0;
 70	cfgx.s.tx_oe = 1;
 71
 72	cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
 73	return 0;
 74}
 75
 76static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
 77{
 78	struct octeon_gpio *gpio = gpiochip_get_data(chip);
 79	u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
 80
 81	return ((1ull << offset) & read_bits) != 0;
 82}
 83
 84static int octeon_gpio_probe(struct platform_device *pdev)
 85{
 86	struct octeon_gpio *gpio;
 87	struct gpio_chip *chip;
 88	void __iomem *reg_base;
 89	int err = 0;
 90
 91	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
 92	if (!gpio)
 93		return -ENOMEM;
 94	chip = &gpio->chip;
 95
 96	reg_base = devm_platform_ioremap_resource(pdev, 0);
 97	if (IS_ERR(reg_base))
 98		return PTR_ERR(reg_base);
 99
100	gpio->register_base = (u64)reg_base;
101	pdev->dev.platform_data = chip;
102	chip->label = "octeon-gpio";
103	chip->parent = &pdev->dev;
104	chip->owner = THIS_MODULE;
105	chip->base = 0;
106	chip->can_sleep = false;
107	chip->ngpio = 20;
108	chip->direction_input = octeon_gpio_dir_in;
109	chip->get = octeon_gpio_get;
110	chip->direction_output = octeon_gpio_dir_out;
111	chip->set = octeon_gpio_set;
112	err = devm_gpiochip_add_data(&pdev->dev, chip, gpio);
113	if (err)
114		return err;
115
116	dev_info(&pdev->dev, "OCTEON GPIO driver probed.\n");
117	return 0;
118}
119
120static const struct of_device_id octeon_gpio_match[] = {
121	{
122		.compatible = "cavium,octeon-3860-gpio",
123	},
124	{},
125};
126MODULE_DEVICE_TABLE(of, octeon_gpio_match);
127
128static struct platform_driver octeon_gpio_driver = {
129	.driver = {
130		.name		= "octeon_gpio",
131		.of_match_table = octeon_gpio_match,
132	},
133	.probe		= octeon_gpio_probe,
134};
135
136module_platform_driver(octeon_gpio_driver);
137
138MODULE_DESCRIPTION("Cavium Inc. OCTEON GPIO Driver");
139MODULE_AUTHOR("David Daney");
140MODULE_LICENSE("GPL");