gpio-nomadik.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * GPIO driver for the IP block found in the Nomadik SoC; it is an AMBA device,
  4 * managing 32 pins with alternate functions. It can also handle the STA2X11
  5 * block from ST.
  6 *
  7 * The GPIO chips are shared with pinctrl-nomadik if used; it needs access for
  8 * pinmuxing functionality and others.
  9 *
 10 * This driver also handles the mobileye,eyeq5-gpio compatible. It is an STA2X11
 11 * but with only data, direction and interrupts register active. We want to
 12 * avoid touching SLPM, RWIMSC, FWIMSC, AFSLA and AFSLB registers; that is,
 13 * wake and alternate function registers. It is NOT compatible with
 14 * pinctrl-nomadik.
 15 *
 16 * Copyright (C) 2008,2009 STMicroelectronics
 17 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
 18 *   Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
 19 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
 20 */
 21#include <linux/cleanup.h>
 22#include <linux/clk.h>
 23#include <linux/gpio/consumer.h>
 24#include <linux/gpio/driver.h>
 25#include <linux/interrupt.h>
 26#include <linux/kernel.h>
 27#include <linux/mod_devicetable.h>
 28#include <linux/pinctrl/pinctrl.h>
 29#include <linux/platform_device.h>
 30#include <linux/property.h>
 31#include <linux/reset.h>
 32#include <linux/seq_file.h>
 33#include <linux/slab.h>
 34#include <linux/string_choices.h>
 35#include <linux/types.h>
 36
 37#include <linux/gpio/gpio-nomadik.h>
 38
 39#ifndef CONFIG_PINCTRL_NOMADIK
 40static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
 41#endif
 42
 43void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, unsigned int offset,
 44			 enum nmk_gpio_slpm mode)
 45{
 46	u32 slpm;
 47
 48	/* We should NOT have been called. */
 49	if (WARN_ON(nmk_chip->is_mobileye_soc))
 50		return;
 51
 52	slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
 53	if (mode == NMK_GPIO_SLPM_NOCHANGE)
 54		slpm |= BIT(offset);
 55	else
 56		slpm &= ~BIT(offset);
 57	writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
 58}
 59
 60static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
 61				  unsigned int offset, int val)
 62{
 63	if (val)
 64		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
 65	else
 66		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
 67}
 68
 69void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
 70			    unsigned int offset, int val)
 71{
 72	writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
 73	__nmk_gpio_set_output(nmk_chip, offset, val);
 74}
 75
 76/* IRQ functions */
 77
 78static void nmk_gpio_irq_ack(struct irq_data *d)
 79{
 80	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 81	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
 82
 83	clk_enable(nmk_chip->clk);
 84	writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
 85	clk_disable(nmk_chip->clk);
 86}
 87
 88enum nmk_gpio_irq_type {
 89	NORMAL,
 90	WAKE,
 91};
 92
 93static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
 94				  int offset, enum nmk_gpio_irq_type which,
 95				  bool enable)
 96{
 97	u32 *rimscval;
 98	u32 *fimscval;
 99	u32 rimscreg;
100	u32 fimscreg;
101
102	if (which == NORMAL) {
103		rimscreg = NMK_GPIO_RIMSC;
104		fimscreg = NMK_GPIO_FIMSC;
105		rimscval = &nmk_chip->rimsc;
106		fimscval = &nmk_chip->fimsc;
107	} else  {
108		/* We should NOT have been called. */
109		if (WARN_ON(nmk_chip->is_mobileye_soc))
110			return;
111		rimscreg = NMK_GPIO_RWIMSC;
112		fimscreg = NMK_GPIO_FWIMSC;
113		rimscval = &nmk_chip->rwimsc;
114		fimscval = &nmk_chip->fwimsc;
115	}
116
117	/* we must individually set/clear the two edges */
118	if (nmk_chip->edge_rising & BIT(offset)) {
119		if (enable)
120			*rimscval |= BIT(offset);
121		else
122			*rimscval &= ~BIT(offset);
123		writel(*rimscval, nmk_chip->addr + rimscreg);
124	}
125	if (nmk_chip->edge_falling & BIT(offset)) {
126		if (enable)
127			*fimscval |= BIT(offset);
128		else
129			*fimscval &= ~BIT(offset);
130		writel(*fimscval, nmk_chip->addr + fimscreg);
131	}
132}
133
134static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
135				int offset, bool on)
136{
137	/* We should NOT have been called. */
138	if (WARN_ON(nmk_chip->is_mobileye_soc))
139		return;
140
141	/*
142	 * Ensure WAKEUP_ENABLE is on.  No need to disable it if wakeup is
143	 * disabled, since setting SLPM to 1 increases power consumption, and
144	 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
145	 */
146	if (nmk_chip->sleepmode && on) {
147		__nmk_gpio_set_slpm(nmk_chip, offset,
148				    NMK_GPIO_SLPM_WAKEUP_ENABLE);
149	}
150
151	__nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
152}
153
154static void nmk_gpio_irq_maskunmask(struct nmk_gpio_chip *nmk_chip,
155				    struct irq_data *d, bool enable)
156{
157	unsigned long flags;
158
159	clk_enable(nmk_chip->clk);
160	spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
161	spin_lock(&nmk_chip->lock);
162
163	__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
164
165	if (!nmk_chip->is_mobileye_soc && !(nmk_chip->real_wake & BIT(d->hwirq)))
166		__nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
167
168	spin_unlock(&nmk_chip->lock);
169	spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
170	clk_disable(nmk_chip->clk);
171}
172
173static void nmk_gpio_irq_mask(struct irq_data *d)
174{
175	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
176	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
177
178	nmk_gpio_irq_maskunmask(nmk_chip, d, false);
179	gpiochip_disable_irq(gc, irqd_to_hwirq(d));
180}
181
182static void nmk_gpio_irq_unmask(struct irq_data *d)
183{
184	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
185	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
186
187	gpiochip_enable_irq(gc, irqd_to_hwirq(d));
188	nmk_gpio_irq_maskunmask(nmk_chip, d, true);
189}
190
191static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
192{
193	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
194	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
195	unsigned long flags;
196
197	/* Handler is registered in all cases. */
198	if (nmk_chip->is_mobileye_soc)
199		return -ENXIO;
200
201	clk_enable(nmk_chip->clk);
202	spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
203	spin_lock(&nmk_chip->lock);
204
205	if (irqd_irq_disabled(d))
206		__nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
207
208	if (on)
209		nmk_chip->real_wake |= BIT(d->hwirq);
210	else
211		nmk_chip->real_wake &= ~BIT(d->hwirq);
212
213	spin_unlock(&nmk_chip->lock);
214	spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
215	clk_disable(nmk_chip->clk);
216
217	return 0;
218}
219
220static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
221{
222	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
223	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
224	bool enabled = !irqd_irq_disabled(d);
225	bool wake = irqd_is_wakeup_set(d);
226	unsigned long flags;
227
228	if (type & IRQ_TYPE_LEVEL_HIGH)
229		return -EINVAL;
230	if (type & IRQ_TYPE_LEVEL_LOW)
231		return -EINVAL;
232
233	clk_enable(nmk_chip->clk);
234	spin_lock_irqsave(&nmk_chip->lock, flags);
235
236	if (enabled)
237		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
238
239	if (!nmk_chip->is_mobileye_soc && (enabled || wake))
240		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
241
242	nmk_chip->edge_rising &= ~BIT(d->hwirq);
243	if (type & IRQ_TYPE_EDGE_RISING)
244		nmk_chip->edge_rising |= BIT(d->hwirq);
245
246	nmk_chip->edge_falling &= ~BIT(d->hwirq);
247	if (type & IRQ_TYPE_EDGE_FALLING)
248		nmk_chip->edge_falling |= BIT(d->hwirq);
249
250	if (enabled)
251		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
252
253	if (!nmk_chip->is_mobileye_soc && (enabled || wake))
254		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
255
256	spin_unlock_irqrestore(&nmk_chip->lock, flags);
257	clk_disable(nmk_chip->clk);
258
259	return 0;
260}
261
262static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
263{
264	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
265	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
266
267	clk_enable(nmk_chip->clk);
268	nmk_gpio_irq_unmask(d);
269	return 0;
270}
271
272static void nmk_gpio_irq_shutdown(struct irq_data *d)
273{
274	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
275	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
276
277	nmk_gpio_irq_mask(d);
278	clk_disable(nmk_chip->clk);
279}
280
281static irqreturn_t nmk_gpio_irq_handler(int irq, void *dev_id)
282{
283	struct nmk_gpio_chip *nmk_chip = dev_id;
284	struct gpio_chip *chip = &nmk_chip->chip;
285	unsigned long mask = GENMASK(chip->ngpio - 1, 0);
286	unsigned long status;
287	int bit;
288
289	clk_enable(nmk_chip->clk);
290
291	status = readl(nmk_chip->addr + NMK_GPIO_IS);
292
293	/* Ensure we cannot leave pending bits; this should never occur. */
294	if (unlikely(status & ~mask))
295		writel(status & ~mask, nmk_chip->addr + NMK_GPIO_IC);
296
297	clk_disable(nmk_chip->clk);
298
299	for_each_set_bit(bit, &status, chip->ngpio)
300		generic_handle_domain_irq_safe(chip->irq.domain, bit);
301
302	return IRQ_RETVAL((status & mask) != 0);
303}
304
305/* I/O Functions */
306
307static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned int offset)
308{
309	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
310	int dir;
311
312	clk_enable(nmk_chip->clk);
313
314	dir = readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset);
315
316	clk_disable(nmk_chip->clk);
317
318	if (dir)
319		return GPIO_LINE_DIRECTION_OUT;
320
321	return GPIO_LINE_DIRECTION_IN;
322}
323
324static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned int offset)
325{
326	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
327
328	clk_enable(nmk_chip->clk);
329
330	writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
331
332	clk_disable(nmk_chip->clk);
333
334	return 0;
335}
336
337static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned int offset)
338{
339	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
340	int value;
341
342	clk_enable(nmk_chip->clk);
343
344	value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
345
346	clk_disable(nmk_chip->clk);
347
348	return value;
349}
350
351static int nmk_gpio_set_output(struct gpio_chip *chip, unsigned int offset,
352			       int val)
353{
354	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
355
356	clk_enable(nmk_chip->clk);
357
358	__nmk_gpio_set_output(nmk_chip, offset, val);
359
360	clk_disable(nmk_chip->clk);
361
362	return 0;
363}
364
365static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned int offset,
366				int val)
367{
368	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
369
370	clk_enable(nmk_chip->clk);
371
372	__nmk_gpio_make_output(nmk_chip, offset, val);
373
374	clk_disable(nmk_chip->clk);
375
376	return 0;
377}
378
379#ifdef CONFIG_DEBUG_FS
380
381static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
382{
383	u32 afunc, bfunc;
384
385	/* We don't support modes. */
386	if (nmk_chip->is_mobileye_soc)
387		return NMK_GPIO_ALT_GPIO;
388
389	clk_enable(nmk_chip->clk);
390
391	afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
392	bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
393
394	clk_disable(nmk_chip->clk);
395
396	return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
397}
398
399void nmk_gpio_dbg_show_one(struct seq_file *s, struct pinctrl_dev *pctldev,
400			   struct gpio_chip *chip, unsigned int offset)
401{
402	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
403#ifdef CONFIG_PINCTRL_NOMADIK
404	struct gpio_desc *desc;
405#endif
406	int mode;
407	bool is_out;
408	bool data_out;
409	bool pull;
410	static const char * const modes[] = {
411		[NMK_GPIO_ALT_GPIO]	= "gpio",
412		[NMK_GPIO_ALT_A]	= "altA",
413		[NMK_GPIO_ALT_B]	= "altB",
414		[NMK_GPIO_ALT_C]	= "altC",
415		[NMK_GPIO_ALT_C + 1]	= "altC1",
416		[NMK_GPIO_ALT_C + 2]	= "altC2",
417		[NMK_GPIO_ALT_C + 3]	= "altC3",
418		[NMK_GPIO_ALT_C + 4]	= "altC4",
419	};
420
421	char *label = gpiochip_dup_line_label(chip, offset);
422	if (IS_ERR(label))
423		return;
424
425	clk_enable(nmk_chip->clk);
426	is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
427	pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
428	data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
429	mode = nmk_gpio_get_mode(nmk_chip, offset);
430#ifdef CONFIG_PINCTRL_NOMADIK
431	if (mode == NMK_GPIO_ALT_C && pctldev) {
432		desc = gpio_device_get_desc(chip->gpiodev, offset);
433		if (IS_ERR(desc))
434			return;
435
436		mode = nmk_prcm_gpiocr_get_mode(pctldev, desc_to_gpio(desc));
437	}
438#endif
439
440	if (is_out) {
441		seq_printf(s, " gpio-%-3d (%-20.20s) out %s           %s",
442			   offset, label ?: "(none)", str_hi_lo(data_out),
443			   (mode < 0) ? "unknown" : modes[mode]);
444	} else {
445		int irq = chip->to_irq(chip, offset);
446		const int pullidx = pull ? 1 : 0;
447		int val;
448		static const char * const pulls[] = {
449			"none        ",
450			"pull enabled",
451		};
452
453		seq_printf(s, " gpio-%-3d (%-20.20s) in  %s %s",
454			   offset, label ?: "(none)", pulls[pullidx],
455			   (mode < 0) ? "unknown" : modes[mode]);
456
457		val = nmk_gpio_get_input(chip, offset);
458		seq_printf(s, " VAL %d", val);
459
460		/*
461		 * This races with request_irq(), set_irq_type(),
462		 * and set_irq_wake() ... but those are "rare".
463		 */
464		if (irq > 0 && irq_has_action(irq)) {
465			char *trigger;
466			bool wake;
467
468			if (nmk_chip->edge_rising & BIT(offset))
469				trigger = "edge-rising";
470			else if (nmk_chip->edge_falling & BIT(offset))
471				trigger = "edge-falling";
472			else
473				trigger = "edge-undefined";
474
475			wake = !!(nmk_chip->real_wake & BIT(offset));
476
477			seq_printf(s, " irq-%d %s%s",
478				   irq, trigger, wake ? " wakeup" : "");
479		}
480	}
481	clk_disable(nmk_chip->clk);
482}
483
484static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
485{
486	unsigned int i;
487
488	for (i = 0; i < chip->ngpio; i++) {
489		nmk_gpio_dbg_show_one(s, NULL, chip, i);
490		seq_puts(s, "\n");
491	}
492}
493
494#else
495
496#define nmk_gpio_dbg_show	NULL
497
498#endif
499
500/*
501 * We will allocate memory for the state container using devm* allocators
502 * binding to the first device reaching this point, it doesn't matter if
503 * it is the pin controller or GPIO driver. However we need to use the right
504 * platform device when looking up resources so pay attention to pdev.
505 */
506struct nmk_gpio_chip *nmk_gpio_populate_chip(struct fwnode_handle *fwnode,
507					     struct platform_device *pdev)
508{
509	struct nmk_gpio_chip *nmk_chip;
510	struct platform_device *gpio_pdev;
511	struct device *dev = &pdev->dev;
512	struct reset_control *reset;
513	struct device *gpio_dev;
514	struct gpio_chip *chip;
515	struct resource *res;
516	struct clk *clk;
517	void __iomem *base;
518	u32 id, ngpio;
519	int ret;
520
521	gpio_dev = bus_find_device_by_fwnode(&platform_bus_type, fwnode);
522	if (!gpio_dev) {
523		dev_err(dev, "populate \"%pfwP\": device not found\n", fwnode);
524		return ERR_PTR(-ENODEV);
525	}
526	gpio_pdev = to_platform_device(gpio_dev);
527
528	if (device_property_read_u32(gpio_dev, "gpio-bank", &id)) {
529		dev_err(dev, "populate: gpio-bank property not found\n");
530		platform_device_put(gpio_pdev);
531		return ERR_PTR(-EINVAL);
532	}
533
534#ifdef CONFIG_PINCTRL_NOMADIK
535	if (id >= ARRAY_SIZE(nmk_gpio_chips)) {
536		dev_err(dev, "populate: invalid id: %u\n", id);
537		platform_device_put(gpio_pdev);
538		return ERR_PTR(-EINVAL);
539	}
540	/* Already populated? */
541	nmk_chip = nmk_gpio_chips[id];
542	if (nmk_chip) {
543		platform_device_put(gpio_pdev);
544		return nmk_chip;
545	}
546#endif
547
548	nmk_chip = devm_kzalloc(dev, sizeof(*nmk_chip), GFP_KERNEL);
549	if (!nmk_chip) {
550		platform_device_put(gpio_pdev);
551		return ERR_PTR(-ENOMEM);
552	}
553
554	if (device_property_read_u32(gpio_dev, "ngpios", &ngpio)) {
555		ngpio = NMK_GPIO_PER_CHIP;
556		dev_dbg(dev, "populate: using default ngpio (%u)\n", ngpio);
557	}
558
559	nmk_chip->is_mobileye_soc = device_is_compatible(gpio_dev,
560							 "mobileye,eyeq5-gpio");
561	nmk_chip->bank = id;
562	chip = &nmk_chip->chip;
563	chip->base = -1;
564	chip->ngpio = ngpio;
565	chip->label = dev_name(gpio_dev);
566	chip->parent = gpio_dev;
567
568	/* NOTE: different devices! No devm_platform_ioremap_resource() here! */
569	res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
570	base = devm_ioremap_resource(dev, res);
571	if (IS_ERR(base)) {
572		platform_device_put(gpio_pdev);
573		return ERR_CAST(base);
574	}
575	nmk_chip->addr = base;
576
577	/* NOTE: do not use devm_ here! */
578	clk = clk_get_optional(gpio_dev, NULL);
579	if (IS_ERR(clk)) {
580		platform_device_put(gpio_pdev);
581		return ERR_CAST(clk);
582	}
583	clk_prepare(clk);
584	nmk_chip->clk = clk;
585
586	/* NOTE: do not use devm_ here! */
587	reset = reset_control_get_optional_shared(gpio_dev, NULL);
588	if (IS_ERR(reset)) {
589		clk_unprepare(clk);
590		clk_put(clk);
591		platform_device_put(gpio_pdev);
592		dev_err(dev, "failed getting reset control: %pe\n",
593			reset);
594		return ERR_CAST(reset);
595	}
596
597	/*
598	 * Reset might be shared and asserts/deasserts calls are unbalanced. We
599	 * only support sharing this reset with other gpio-nomadik devices that
600	 * use this reset to ensure deassertion at probe.
601	 */
602	ret = reset_control_deassert(reset);
603	if (ret) {
604		reset_control_put(reset);
605		clk_unprepare(clk);
606		clk_put(clk);
607		platform_device_put(gpio_pdev);
608		dev_err(dev, "failed reset deassert: %d\n", ret);
609		return ERR_PTR(ret);
610	}
611
612#ifdef CONFIG_PINCTRL_NOMADIK
613	nmk_gpio_chips[id] = nmk_chip;
614#endif
615	return nmk_chip;
616}
617
618static void nmk_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
619{
620	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
621	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
622
623	seq_printf(p, "nmk%u-%u-%u", nmk_chip->bank,
624		   gc->base, gc->base + gc->ngpio - 1);
625}
626
627static const struct irq_chip nmk_irq_chip = {
628	.irq_ack = nmk_gpio_irq_ack,
629	.irq_mask = nmk_gpio_irq_mask,
630	.irq_unmask = nmk_gpio_irq_unmask,
631	.irq_set_type = nmk_gpio_irq_set_type,
632	.irq_set_wake = nmk_gpio_irq_set_wake,
633	.irq_startup = nmk_gpio_irq_startup,
634	.irq_shutdown = nmk_gpio_irq_shutdown,
635	.irq_print_chip = nmk_gpio_irq_print_chip,
636	.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
637	GPIOCHIP_IRQ_RESOURCE_HELPERS,
638};
639
640static int nmk_gpio_probe(struct platform_device *pdev)
641{
642	struct device *dev = &pdev->dev;
643	struct nmk_gpio_chip *nmk_chip;
644	struct gpio_irq_chip *girq;
645	bool supports_sleepmode;
646	struct gpio_chip *chip;
647	int irq;
648	int ret;
649
650	nmk_chip = nmk_gpio_populate_chip(dev_fwnode(dev), pdev);
651	if (IS_ERR(nmk_chip)) {
652		dev_err(dev, "could not populate nmk chip struct\n");
653		return PTR_ERR(nmk_chip);
654	}
655
656	supports_sleepmode =
657		device_property_read_bool(dev, "st,supports-sleepmode");
658
659	/* Correct platform device ID */
660	pdev->id = nmk_chip->bank;
661
662	irq = platform_get_irq(pdev, 0);
663	if (irq < 0)
664		return irq;
665
666	/*
667	 * The virt address in nmk_chip->addr is in the nomadik register space,
668	 * so we can simply convert the resource address, without remapping
669	 */
670	nmk_chip->sleepmode = supports_sleepmode;
671	spin_lock_init(&nmk_chip->lock);
672
673	chip = &nmk_chip->chip;
674	chip->parent = dev;
675	chip->request = gpiochip_generic_request;
676	chip->free = gpiochip_generic_free;
677	chip->get_direction = nmk_gpio_get_dir;
678	chip->direction_input = nmk_gpio_make_input;
679	chip->get = nmk_gpio_get_input;
680	chip->direction_output = nmk_gpio_make_output;
681	chip->set = nmk_gpio_set_output;
682	chip->dbg_show = nmk_gpio_dbg_show;
683	chip->can_sleep = false;
684	chip->owner = THIS_MODULE;
685
686	girq = &chip->irq;
687	gpio_irq_chip_set_chip(girq, &nmk_irq_chip);
688	girq->parent_handler = NULL;
689	girq->num_parents = 0;
690	girq->parents = NULL;
691	girq->default_type = IRQ_TYPE_NONE;
692	girq->handler = handle_edge_irq;
693
694	ret = devm_request_irq(dev, irq, nmk_gpio_irq_handler, IRQF_SHARED,
695			       dev_name(dev), nmk_chip);
696	if (ret) {
697		dev_err(dev, "failed requesting IRQ\n");
698		return ret;
699	}
700
701	if (!nmk_chip->is_mobileye_soc) {
702		clk_enable(nmk_chip->clk);
703		nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
704		clk_disable(nmk_chip->clk);
705	}
706
707	ret = gpiochip_add_data(chip, nmk_chip);
708	if (ret)
709		return ret;
710
711	platform_set_drvdata(pdev, nmk_chip);
712
713	dev_info(dev, "chip registered\n");
714
715	return 0;
716}
717
718static const struct of_device_id nmk_gpio_match[] = {
719	{ .compatible = "st,nomadik-gpio", },
720	{ .compatible = "mobileye,eyeq5-gpio", },
721	{}
722};
723
724static struct platform_driver nmk_gpio_driver = {
725	.driver = {
726		.name = "nomadik-gpio",
727		.of_match_table = nmk_gpio_match,
728		.suppress_bind_attrs = true,
729	},
730	.probe = nmk_gpio_probe,
731};
732
733static int __init nmk_gpio_init(void)
734{
735	return platform_driver_register(&nmk_gpio_driver);
736}
737subsys_initcall(nmk_gpio_init);