gpio-mxs.c

  1// SPDX-License-Identifier: GPL-2.0+
  2//
  3// MXS GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
  4// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  5//
  6// Based on code from Freescale,
  7// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  8
  9#include <linux/err.h>
 10#include <linux/gpio/driver.h>
 11#include <linux/gpio/generic.h>
 12#include <linux/init.h>
 13#include <linux/interrupt.h>
 14#include <linux/io.h>
 15#include <linux/irq.h>
 16#include <linux/irqdomain.h>
 17#include <linux/module.h>
 18#include <linux/of.h>
 19#include <linux/of_address.h>
 20#include <linux/platform_device.h>
 21#include <linux/slab.h>
 22
 23#define MXS_SET		0x4
 24#define MXS_CLR		0x8
 25
 26#define PINCTRL_DOUT(p)		((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
 27#define PINCTRL_DIN(p)		((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
 28#define PINCTRL_DOE(p)		((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
 29#define PINCTRL_PIN2IRQ(p)	((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
 30#define PINCTRL_IRQEN(p)	((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
 31#define PINCTRL_IRQLEV(p)	((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
 32#define PINCTRL_IRQPOL(p)	((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
 33#define PINCTRL_IRQSTAT(p)	((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
 34
 35#define GPIO_INT_FALL_EDGE	0x0
 36#define GPIO_INT_LOW_LEV	0x1
 37#define GPIO_INT_RISE_EDGE	0x2
 38#define GPIO_INT_HIGH_LEV	0x3
 39#define GPIO_INT_LEV_MASK	(1 << 0)
 40#define GPIO_INT_POL_MASK	(1 << 1)
 41
 42enum mxs_gpio_id {
 43	IMX23_GPIO,
 44	IMX28_GPIO,
 45};
 46
 47struct mxs_gpio_port {
 48	void __iomem *base;
 49	int id;
 50	int irq;
 51	struct irq_domain *domain;
 52	struct gpio_generic_chip chip;
 53	struct device *dev;
 54	enum mxs_gpio_id devid;
 55	u32 both_edges;
 56};
 57
 58static inline int is_imx23_gpio(struct mxs_gpio_port *port)
 59{
 60	return port->devid == IMX23_GPIO;
 61}
 62
 63/* Note: This driver assumes 32 GPIOs are handled in one register */
 64
 65static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
 66{
 67	u32 val;
 68	u32 pin_mask = 1 << d->hwirq;
 69	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 70	struct irq_chip_type *ct = irq_data_get_chip_type(d);
 71	struct mxs_gpio_port *port = gc->private;
 72	void __iomem *pin_addr;
 73	int edge;
 74
 75	if (!(ct->type & type))
 76		if (irq_setup_alt_chip(d, type))
 77			return -EINVAL;
 78
 79	port->both_edges &= ~pin_mask;
 80	switch (type) {
 81	case IRQ_TYPE_EDGE_BOTH:
 82		val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
 83		if (val)
 84			edge = GPIO_INT_FALL_EDGE;
 85		else
 86			edge = GPIO_INT_RISE_EDGE;
 87		port->both_edges |= pin_mask;
 88		break;
 89	case IRQ_TYPE_EDGE_RISING:
 90		edge = GPIO_INT_RISE_EDGE;
 91		break;
 92	case IRQ_TYPE_EDGE_FALLING:
 93		edge = GPIO_INT_FALL_EDGE;
 94		break;
 95	case IRQ_TYPE_LEVEL_LOW:
 96		edge = GPIO_INT_LOW_LEV;
 97		break;
 98	case IRQ_TYPE_LEVEL_HIGH:
 99		edge = GPIO_INT_HIGH_LEV;
100		break;
101	default:
102		return -EINVAL;
103	}
104
105	/* set level or edge */
106	pin_addr = port->base + PINCTRL_IRQLEV(port);
107	if (edge & GPIO_INT_LEV_MASK) {
108		writel(pin_mask, pin_addr + MXS_SET);
109		writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
110	} else {
111		writel(pin_mask, pin_addr + MXS_CLR);
112		writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
113	}
114
115	/* set polarity */
116	pin_addr = port->base + PINCTRL_IRQPOL(port);
117	if (edge & GPIO_INT_POL_MASK)
118		writel(pin_mask, pin_addr + MXS_SET);
119	else
120		writel(pin_mask, pin_addr + MXS_CLR);
121
122	writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
123
124	return 0;
125}
126
127static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
128{
129	u32 bit, val, edge;
130	void __iomem *pin_addr;
131
132	bit = 1 << gpio;
133
134	pin_addr = port->base + PINCTRL_IRQPOL(port);
135	val = readl(pin_addr);
136	edge = val & bit;
137
138	if (edge)
139		writel(bit, pin_addr + MXS_CLR);
140	else
141		writel(bit, pin_addr + MXS_SET);
142}
143
144/* MXS has one interrupt *per* gpio port */
145static void mxs_gpio_irq_handler(struct irq_desc *desc)
146{
147	u32 irq_stat;
148	struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
149
150	desc->irq_data.chip->irq_ack(&desc->irq_data);
151
152	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
153			readl(port->base + PINCTRL_IRQEN(port));
154
155	while (irq_stat != 0) {
156		int irqoffset = fls(irq_stat) - 1;
157		if (port->both_edges & (1 << irqoffset))
158			mxs_flip_edge(port, irqoffset);
159
160		generic_handle_domain_irq(port->domain, irqoffset);
161		irq_stat &= ~(1 << irqoffset);
162	}
163}
164
165/*
166 * Set interrupt number "irq" in the GPIO as a wake-up source.
167 * While system is running, all registered GPIO interrupts need to have
168 * wake-up enabled. When system is suspended, only selected GPIO interrupts
169 * need to have wake-up enabled.
170 * @param  irq          interrupt source number
171 * @param  enable       enable as wake-up if equal to non-zero
172 * @return       This function returns 0 on success.
173 */
174static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
175{
176	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
177	struct mxs_gpio_port *port = gc->private;
178
179	if (enable)
180		enable_irq_wake(port->irq);
181	else
182		disable_irq_wake(port->irq);
183
184	return 0;
185}
186
187static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
188{
189	struct irq_chip_generic *gc;
190	struct irq_chip_type *ct;
191	int rv;
192
193	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
194					 port->base, handle_level_irq);
195	if (!gc)
196		return -ENOMEM;
197
198	gc->private = port;
199
200	ct = &gc->chip_types[0];
201	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
202	ct->chip.irq_ack = irq_gc_ack_set_bit;
203	ct->chip.irq_mask = irq_gc_mask_disable_reg;
204	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
205	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
206	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
207	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
208	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
209	ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
210	ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
211
212	ct = &gc->chip_types[1];
213	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
214	ct->chip.irq_ack = irq_gc_ack_set_bit;
215	ct->chip.irq_mask = irq_gc_mask_disable_reg;
216	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
217	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
218	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
219	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
220	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
221	ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
222	ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
223	ct->handler = handle_level_irq;
224
225	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
226					 IRQ_GC_INIT_NESTED_LOCK,
227					 IRQ_NOREQUEST, 0);
228
229	return rv;
230}
231
232static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
233{
234	struct mxs_gpio_port *port = gpiochip_get_data(gc);
235
236	return irq_find_mapping(port->domain, offset);
237}
238
239static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
240{
241	struct mxs_gpio_port *port = gpiochip_get_data(gc);
242	u32 mask = 1 << offset;
243	u32 dir;
244
245	dir = readl(port->base + PINCTRL_DOE(port));
246	if (dir & mask)
247		return GPIO_LINE_DIRECTION_OUT;
248
249	return GPIO_LINE_DIRECTION_IN;
250}
251
252static const struct of_device_id mxs_gpio_dt_ids[] = {
253	{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
254	{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
255	{ /* sentinel */ }
256};
257MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
258
259static int mxs_gpio_probe(struct platform_device *pdev)
260{
261	struct device_node *np = pdev->dev.of_node;
262	struct gpio_generic_chip_config config;
263	struct device_node *parent;
264	static void __iomem *base;
265	struct mxs_gpio_port *port;
266	int irq_base;
267	int err;
268
269	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
270	if (!port)
271		return -ENOMEM;
272
273	port->id = of_alias_get_id(np, "gpio");
274	if (port->id < 0)
275		return port->id;
276	port->devid = (uintptr_t)of_device_get_match_data(&pdev->dev);
277	port->dev = &pdev->dev;
278	port->irq = platform_get_irq(pdev, 0);
279	if (port->irq < 0)
280		return port->irq;
281
282	/*
283	 * map memory region only once, as all the gpio ports
284	 * share the same one
285	 */
286	if (!base) {
287		parent = of_get_parent(np);
288		base = of_iomap(parent, 0);
289		of_node_put(parent);
290		if (!base)
291			return -EADDRNOTAVAIL;
292	}
293	port->base = base;
294
295	/* initially disable the interrupts */
296	writel(0, port->base + PINCTRL_PIN2IRQ(port));
297	writel(0, port->base + PINCTRL_IRQEN(port));
298
299	/* clear address has to be used to clear IRQSTAT bits */
300	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
301
302	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
303	if (irq_base < 0) {
304		err = irq_base;
305		goto out_iounmap;
306	}
307
308	port->domain = irq_domain_create_legacy(dev_fwnode(&pdev->dev), 32, irq_base, 0,
309						&irq_domain_simple_ops, NULL);
310	if (!port->domain) {
311		err = -ENODEV;
312		goto out_iounmap;
313	}
314
315	/* gpio-mxs can be a generic irq chip */
316	err = mxs_gpio_init_gc(port, irq_base);
317	if (err < 0)
318		goto out_irqdomain_remove;
319
320	/* setup one handler for each entry */
321	irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
322					 port);
323
324	config = (struct gpio_generic_chip_config) {
325		.dev = &pdev->dev,
326		.sz = 4,
327		.dat = port->base + PINCTRL_DIN(port),
328		.set = port->base + PINCTRL_DOUT(port) + MXS_SET,
329		.clr = port->base + PINCTRL_DOUT(port) + MXS_CLR,
330		.dirout = port->base + PINCTRL_DOE(port),
331	};
332
333	err = gpio_generic_chip_init(&port->chip, &config);
334	if (err)
335		goto out_irqdomain_remove;
336
337	port->chip.gc.to_irq = mxs_gpio_to_irq;
338	port->chip.gc.get_direction = mxs_gpio_get_direction;
339	port->chip.gc.base = port->id * 32;
340
341	err = gpiochip_add_data(&port->chip.gc, port);
342	if (err)
343		goto out_irqdomain_remove;
344
345	return 0;
346
347out_irqdomain_remove:
348	irq_domain_remove(port->domain);
349out_iounmap:
350	iounmap(port->base);
351	return err;
352}
353
354static struct platform_driver mxs_gpio_driver = {
355	.driver		= {
356		.name	= "gpio-mxs",
357		.of_match_table = mxs_gpio_dt_ids,
358		.suppress_bind_attrs = true,
359	},
360	.probe		= mxs_gpio_probe,
361};
362
363static int __init mxs_gpio_init(void)
364{
365	return platform_driver_register(&mxs_gpio_driver);
366}
367postcore_initcall(mxs_gpio_init);
368
369MODULE_AUTHOR("Freescale Semiconductor, "
370	      "Daniel Mack <danielncaiaq.de>, "
371	      "Juergen Beisert <kernel@pengutronix.de>");
372MODULE_DESCRIPTION("Freescale MXS GPIO");