gpio-mxc.c

  1// SPDX-License-Identifier: GPL-2.0+
  2//
  3// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
  4// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  5//
  6// Based on code from Freescale Semiconductor,
  7// Authors: Daniel Mack, Juergen Beisert.
  8// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  9
 10#include <linux/cleanup.h>
 11#include <linux/clk.h>
 12#include <linux/err.h>
 13#include <linux/init.h>
 14#include <linux/interrupt.h>
 15#include <linux/io.h>
 16#include <linux/irq.h>
 17#include <linux/irqdomain.h>
 18#include <linux/irqchip/chained_irq.h>
 19#include <linux/module.h>
 20#include <linux/platform_device.h>
 21#include <linux/pm_runtime.h>
 22#include <linux/slab.h>
 23#include <linux/spinlock.h>
 24#include <linux/syscore_ops.h>
 25#include <linux/gpio/driver.h>
 26#include <linux/gpio/generic.h>
 27#include <linux/of.h>
 28#include <linux/bug.h>
 29
 30#define IMX_SCU_WAKEUP_OFF		0
 31#define IMX_SCU_WAKEUP_LOW_LVL		4
 32#define IMX_SCU_WAKEUP_FALL_EDGE	5
 33#define IMX_SCU_WAKEUP_RISE_EDGE	6
 34#define IMX_SCU_WAKEUP_HIGH_LVL		7
 35
 36/* device type dependent stuff */
 37struct mxc_gpio_hwdata {
 38	unsigned dr_reg;
 39	unsigned gdir_reg;
 40	unsigned psr_reg;
 41	unsigned icr1_reg;
 42	unsigned icr2_reg;
 43	unsigned imr_reg;
 44	unsigned isr_reg;
 45	int edge_sel_reg;
 46	unsigned low_level;
 47	unsigned high_level;
 48	unsigned rise_edge;
 49	unsigned fall_edge;
 50};
 51
 52struct mxc_gpio_reg_saved {
 53	u32 icr1;
 54	u32 icr2;
 55	u32 imr;
 56	u32 gdir;
 57	u32 edge_sel;
 58	u32 dr;
 59};
 60
 61struct mxc_gpio_port {
 62	struct list_head node;
 63	void __iomem *base;
 64	struct clk *clk;
 65	int irq;
 66	int irq_high;
 67	void (*mx_irq_handler)(struct irq_desc *desc);
 68	struct irq_domain *domain;
 69	struct gpio_generic_chip gen_gc;
 70	struct device *dev;
 71	u32 both_edges;
 72	struct mxc_gpio_reg_saved gpio_saved_reg;
 73	bool power_off;
 74	u32 wakeup_pads;
 75	bool is_pad_wakeup;
 76	u32 pad_type[32];
 77	const struct mxc_gpio_hwdata *hwdata;
 78};
 79
 80static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
 81	.dr_reg		= 0x1c,
 82	.gdir_reg	= 0x00,
 83	.psr_reg	= 0x24,
 84	.icr1_reg	= 0x28,
 85	.icr2_reg	= 0x2c,
 86	.imr_reg	= 0x30,
 87	.isr_reg	= 0x34,
 88	.edge_sel_reg	= -EINVAL,
 89	.low_level	= 0x03,
 90	.high_level	= 0x02,
 91	.rise_edge	= 0x00,
 92	.fall_edge	= 0x01,
 93};
 94
 95static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
 96	.dr_reg		= 0x00,
 97	.gdir_reg	= 0x04,
 98	.psr_reg	= 0x08,
 99	.icr1_reg	= 0x0c,
100	.icr2_reg	= 0x10,
101	.imr_reg	= 0x14,
102	.isr_reg	= 0x18,
103	.edge_sel_reg	= -EINVAL,
104	.low_level	= 0x00,
105	.high_level	= 0x01,
106	.rise_edge	= 0x02,
107	.fall_edge	= 0x03,
108};
109
110static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
111	.dr_reg		= 0x00,
112	.gdir_reg	= 0x04,
113	.psr_reg	= 0x08,
114	.icr1_reg	= 0x0c,
115	.icr2_reg	= 0x10,
116	.imr_reg	= 0x14,
117	.isr_reg	= 0x18,
118	.edge_sel_reg	= 0x1c,
119	.low_level	= 0x00,
120	.high_level	= 0x01,
121	.rise_edge	= 0x02,
122	.fall_edge	= 0x03,
123};
124
125#define GPIO_DR			(port->hwdata->dr_reg)
126#define GPIO_GDIR		(port->hwdata->gdir_reg)
127#define GPIO_PSR		(port->hwdata->psr_reg)
128#define GPIO_ICR1		(port->hwdata->icr1_reg)
129#define GPIO_ICR2		(port->hwdata->icr2_reg)
130#define GPIO_IMR		(port->hwdata->imr_reg)
131#define GPIO_ISR		(port->hwdata->isr_reg)
132#define GPIO_EDGE_SEL		(port->hwdata->edge_sel_reg)
133
134#define GPIO_INT_LOW_LEV	(port->hwdata->low_level)
135#define GPIO_INT_HIGH_LEV	(port->hwdata->high_level)
136#define GPIO_INT_RISE_EDGE	(port->hwdata->rise_edge)
137#define GPIO_INT_FALL_EDGE	(port->hwdata->fall_edge)
138#define GPIO_INT_BOTH_EDGES	0x4
139
140static const struct of_device_id mxc_gpio_dt_ids[] = {
141	{ .compatible = "fsl,imx1-gpio", .data =  &imx1_imx21_gpio_hwdata },
142	{ .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata },
143	{ .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata },
144	{ .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata },
145	{ .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata },
146	{ .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata },
147	{ .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata },
148	{ .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata },
149	{ /* sentinel */ }
150};
151MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
152
153/*
154 * MX2 has one interrupt *for all* gpio ports. The list is used
155 * to save the references to all ports, so that mx2_gpio_irq_handler
156 * can walk through all interrupt status registers.
157 */
158static LIST_HEAD(mxc_gpio_ports);
159
160/* Note: This driver assumes 32 GPIOs are handled in one register */
161
162static int gpio_set_irq_type(struct irq_data *d, u32 type)
163{
164	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
165	struct mxc_gpio_port *port = gc->private;
166	u32 bit, val;
167	u32 gpio_idx = d->hwirq;
168	int edge;
169	void __iomem *reg = port->base;
170
171	port->both_edges &= ~(1 << gpio_idx);
172	switch (type) {
173	case IRQ_TYPE_EDGE_RISING:
174		edge = GPIO_INT_RISE_EDGE;
175		break;
176	case IRQ_TYPE_EDGE_FALLING:
177		edge = GPIO_INT_FALL_EDGE;
178		break;
179	case IRQ_TYPE_EDGE_BOTH:
180		if (GPIO_EDGE_SEL >= 0) {
181			edge = GPIO_INT_BOTH_EDGES;
182		} else {
183			val = port->gen_gc.gc.get(&port->gen_gc.gc, gpio_idx);
184			if (val) {
185				edge = GPIO_INT_LOW_LEV;
186				pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
187			} else {
188				edge = GPIO_INT_HIGH_LEV;
189				pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
190			}
191			port->both_edges |= 1 << gpio_idx;
192		}
193		break;
194	case IRQ_TYPE_LEVEL_LOW:
195		edge = GPIO_INT_LOW_LEV;
196		break;
197	case IRQ_TYPE_LEVEL_HIGH:
198		edge = GPIO_INT_HIGH_LEV;
199		break;
200	default:
201		return -EINVAL;
202	}
203
204	scoped_guard(gpio_generic_lock_irqsave, &port->gen_gc) {
205		if (GPIO_EDGE_SEL >= 0) {
206			val = readl(port->base + GPIO_EDGE_SEL);
207			if (edge == GPIO_INT_BOTH_EDGES)
208				writel(val | (1 << gpio_idx),
209				       port->base + GPIO_EDGE_SEL);
210			else
211				writel(val & ~(1 << gpio_idx),
212				       port->base + GPIO_EDGE_SEL);
213		}
214
215		if (edge != GPIO_INT_BOTH_EDGES) {
216			reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
217			bit = gpio_idx & 0xf;
218			val = readl(reg) & ~(0x3 << (bit << 1));
219			writel(val | (edge << (bit << 1)), reg);
220		}
221
222		writel(1 << gpio_idx, port->base + GPIO_ISR);
223		port->pad_type[gpio_idx] = type;
224	}
225
226	return port->gen_gc.gc.direction_input(&port->gen_gc.gc, gpio_idx);
227}
228
229static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
230{
231	void __iomem *reg = port->base;
232	u32 bit, val;
233	int edge;
234
235	guard(gpio_generic_lock_irqsave)(&port->gen_gc);
236
237	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
238	bit = gpio & 0xf;
239	val = readl(reg);
240	edge = (val >> (bit << 1)) & 3;
241	val &= ~(0x3 << (bit << 1));
242	if (edge == GPIO_INT_HIGH_LEV) {
243		edge = GPIO_INT_LOW_LEV;
244		pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
245	} else if (edge == GPIO_INT_LOW_LEV) {
246		edge = GPIO_INT_HIGH_LEV;
247		pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
248	} else {
249		pr_err("mxc: invalid configuration for GPIO %d: %x\n",
250		       gpio, edge);
251		return;
252	}
253	writel(val | (edge << (bit << 1)), reg);
254}
255
256/* handle 32 interrupts in one status register */
257static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
258{
259	while (irq_stat != 0) {
260		int irqoffset = fls(irq_stat) - 1;
261
262		if (port->both_edges & (1 << irqoffset))
263			mxc_flip_edge(port, irqoffset);
264
265		generic_handle_domain_irq(port->domain, irqoffset);
266
267		irq_stat &= ~(1 << irqoffset);
268	}
269}
270
271/* MX1 and MX3 has one interrupt *per* gpio port */
272static void mx3_gpio_irq_handler(struct irq_desc *desc)
273{
274	u32 irq_stat;
275	struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
276	struct irq_chip *chip = irq_desc_get_chip(desc);
277
278	if (port->is_pad_wakeup)
279		return;
280
281	chained_irq_enter(chip, desc);
282
283	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
284
285	mxc_gpio_irq_handler(port, irq_stat);
286
287	chained_irq_exit(chip, desc);
288}
289
290/* MX2 has one interrupt *for all* gpio ports */
291static void mx2_gpio_irq_handler(struct irq_desc *desc)
292{
293	u32 irq_msk, irq_stat;
294	struct mxc_gpio_port *port;
295	struct irq_chip *chip = irq_desc_get_chip(desc);
296
297	chained_irq_enter(chip, desc);
298
299	/* walk through all interrupt status registers */
300	list_for_each_entry(port, &mxc_gpio_ports, node) {
301		irq_msk = readl(port->base + GPIO_IMR);
302		if (!irq_msk)
303			continue;
304
305		irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
306		if (irq_stat)
307			mxc_gpio_irq_handler(port, irq_stat);
308	}
309	chained_irq_exit(chip, desc);
310}
311
312/*
313 * Set interrupt number "irq" in the GPIO as a wake-up source.
314 * While system is running, all registered GPIO interrupts need to have
315 * wake-up enabled. When system is suspended, only selected GPIO interrupts
316 * need to have wake-up enabled.
317 * @param  irq          interrupt source number
318 * @param  enable       enable as wake-up if equal to non-zero
319 * @return       This function returns 0 on success.
320 */
321static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
322{
323	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
324	struct mxc_gpio_port *port = gc->private;
325	u32 gpio_idx = d->hwirq;
326	int ret;
327
328	if (enable) {
329		if (port->irq_high && (gpio_idx >= 16))
330			ret = enable_irq_wake(port->irq_high);
331		else
332			ret = enable_irq_wake(port->irq);
333		port->wakeup_pads |= (1 << gpio_idx);
334	} else {
335		if (port->irq_high && (gpio_idx >= 16))
336			ret = disable_irq_wake(port->irq_high);
337		else
338			ret = disable_irq_wake(port->irq);
339		port->wakeup_pads &= ~(1 << gpio_idx);
340	}
341
342	return ret;
343}
344
345static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
346{
347	struct irq_chip_generic *gc;
348	struct irq_chip_type *ct;
349	int rv;
350
351	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
352					 port->base, handle_level_irq);
353	if (!gc)
354		return -ENOMEM;
355	gc->private = port;
356
357	ct = gc->chip_types;
358	ct->chip.irq_ack = irq_gc_ack_set_bit;
359	ct->chip.irq_mask = irq_gc_mask_clr_bit;
360	ct->chip.irq_unmask = irq_gc_mask_set_bit;
361	ct->chip.irq_set_type = gpio_set_irq_type;
362	ct->chip.irq_set_wake = gpio_set_wake_irq;
363	ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
364	ct->regs.ack = GPIO_ISR;
365	ct->regs.mask = GPIO_IMR;
366
367	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
368					 IRQ_GC_INIT_NESTED_LOCK,
369					 IRQ_NOREQUEST, 0);
370
371	return rv;
372}
373
374static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
375{
376	struct mxc_gpio_port *port = gpiochip_get_data(gc);
377
378	return irq_find_mapping(port->domain, offset);
379}
380
381static int mxc_gpio_request(struct gpio_chip *chip, unsigned int offset)
382{
383	int ret;
384
385	ret = gpiochip_generic_request(chip, offset);
386	if (ret)
387		return ret;
388
389	return pm_runtime_resume_and_get(chip->parent);
390}
391
392static void mxc_gpio_free(struct gpio_chip *chip, unsigned int offset)
393{
394	gpiochip_generic_free(chip, offset);
395	pm_runtime_put(chip->parent);
396}
397
398static void mxc_update_irq_chained_handler(struct mxc_gpio_port *port, bool enable)
399{
400	if (enable)
401		irq_set_chained_handler_and_data(port->irq, port->mx_irq_handler, port);
402	else
403		irq_set_chained_handler_and_data(port->irq, NULL, NULL);
404
405	/* setup handler for GPIO 16 to 31 */
406	if (port->irq_high > 0) {
407		if (enable)
408			irq_set_chained_handler_and_data(port->irq_high,
409							 port->mx_irq_handler,
410							 port);
411		else
412			irq_set_chained_handler_and_data(port->irq_high, NULL, NULL);
413	}
414}
415
416static int mxc_gpio_probe(struct platform_device *pdev)
417{
418	struct gpio_generic_chip_config config = { };
419	struct device_node *np = pdev->dev.of_node;
420	struct mxc_gpio_port *port;
421	int irq_count;
422	int irq_base;
423	int err;
424
425	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
426	if (!port)
427		return -ENOMEM;
428
429	port->dev = &pdev->dev;
430	port->hwdata = device_get_match_data(&pdev->dev);
431
432	port->base = devm_platform_ioremap_resource(pdev, 0);
433	if (IS_ERR(port->base))
434		return PTR_ERR(port->base);
435
436	irq_count = platform_irq_count(pdev);
437	if (irq_count < 0)
438		return irq_count;
439
440	if (irq_count > 1) {
441		port->irq_high = platform_get_irq(pdev, 1);
442		if (port->irq_high < 0)
443			port->irq_high = 0;
444	}
445
446	port->irq = platform_get_irq(pdev, 0);
447	if (port->irq < 0)
448		return port->irq;
449
450	/* the controller clock is optional */
451	port->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
452	if (IS_ERR(port->clk))
453		return PTR_ERR(port->clk);
454
455	if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
456		port->power_off = true;
457
458	pm_runtime_get_noresume(&pdev->dev);
459	pm_runtime_set_active(&pdev->dev);
460	pm_runtime_enable(&pdev->dev);
461
462	/* disable the interrupt and clear the status */
463	writel(0, port->base + GPIO_IMR);
464	writel(~0, port->base + GPIO_ISR);
465
466	if (of_device_is_compatible(np, "fsl,imx21-gpio")) {
467		/*
468		 * Setup one handler for all GPIO interrupts. Actually setting
469		 * the handler is needed only once, but doing it for every port
470		 * is more robust and easier.
471		 */
472		port->irq_high = -1;
473		port->mx_irq_handler = mx2_gpio_irq_handler;
474	} else
475		port->mx_irq_handler = mx3_gpio_irq_handler;
476
477	mxc_update_irq_chained_handler(port, true);
478
479	config.dev = &pdev->dev;
480	config.sz = 4;
481	config.dat = port->base + GPIO_PSR;
482	config.set = port->base + GPIO_DR;
483	config.dirout = port->base + GPIO_GDIR;
484	config.flags = GPIO_GENERIC_READ_OUTPUT_REG_SET;
485
486	err = gpio_generic_chip_init(&port->gen_gc, &config);
487	if (err)
488		goto out_bgio;
489
490	port->gen_gc.gc.request = mxc_gpio_request;
491	port->gen_gc.gc.free = mxc_gpio_free;
492	port->gen_gc.gc.to_irq = mxc_gpio_to_irq;
493	/*
494	 * Driver is DT-only, so a fixed base needs only be maintained for legacy
495	 * userspace with sysfs interface.
496	 */
497	if (IS_ENABLED(CONFIG_GPIO_SYSFS))
498		port->gen_gc.gc.base = of_alias_get_id(np, "gpio") * 32;
499	else /* silence boot time warning */
500		port->gen_gc.gc.base = -1;
501
502	err = devm_gpiochip_add_data(&pdev->dev, &port->gen_gc.gc, port);
503	if (err)
504		goto out_bgio;
505
506	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
507	if (irq_base < 0) {
508		err = irq_base;
509		goto out_bgio;
510	}
511
512	port->domain = irq_domain_create_legacy(dev_fwnode(&pdev->dev), 32, irq_base, 0,
513						&irq_domain_simple_ops, NULL);
514	if (!port->domain) {
515		err = -ENODEV;
516		goto out_bgio;
517	}
518
519	irq_domain_set_pm_device(port->domain, &pdev->dev);
520
521	/* gpio-mxc can be a generic irq chip */
522	err = mxc_gpio_init_gc(port, irq_base);
523	if (err < 0)
524		goto out_irqdomain_remove;
525
526	list_add_tail(&port->node, &mxc_gpio_ports);
527
528	platform_set_drvdata(pdev, port);
529	pm_runtime_put_autosuspend(&pdev->dev);
530
531	return 0;
532
533out_irqdomain_remove:
534	irq_domain_remove(port->domain);
535out_bgio:
536	pm_runtime_disable(&pdev->dev);
537	pm_runtime_put_noidle(&pdev->dev);
538	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
539	return err;
540}
541
542static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
543{
544	if (!port->power_off)
545		return;
546
547	port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
548	port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
549	port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
550	port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
551	port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
552	port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
553}
554
555static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
556{
557	if (!port->power_off)
558		return;
559
560	writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
561	writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
562	writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
563	writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
564	writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
565	writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
566}
567
568static bool mxc_gpio_generic_config(struct mxc_gpio_port *port,
569		unsigned int offset, unsigned long conf)
570{
571	struct device_node *np = port->dev->of_node;
572
573	if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") ||
574	    of_device_is_compatible(np, "fsl,imx8qxp-gpio") ||
575	    of_device_is_compatible(np, "fsl,imx8qm-gpio"))
576		return (gpiochip_generic_config(&port->gen_gc.gc,
577						offset, conf) == 0);
578
579	return false;
580}
581
582static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable)
583{
584	unsigned long config;
585	bool ret = false;
586	int i, type;
587	bool is_imx8qm = of_device_is_compatible(port->dev->of_node, "fsl,imx8qm-gpio");
588
589	static const u32 pad_type_map[] = {
590		IMX_SCU_WAKEUP_OFF,		/* 0 */
591		IMX_SCU_WAKEUP_RISE_EDGE,	/* IRQ_TYPE_EDGE_RISING */
592		IMX_SCU_WAKEUP_FALL_EDGE,	/* IRQ_TYPE_EDGE_FALLING */
593		IMX_SCU_WAKEUP_RISE_EDGE,	/* IRQ_TYPE_EDGE_BOTH */
594		IMX_SCU_WAKEUP_HIGH_LVL,	/* IRQ_TYPE_LEVEL_HIGH */
595		IMX_SCU_WAKEUP_OFF,		/* 5 */
596		IMX_SCU_WAKEUP_OFF,		/* 6 */
597		IMX_SCU_WAKEUP_OFF,		/* 7 */
598		IMX_SCU_WAKEUP_LOW_LVL,		/* IRQ_TYPE_LEVEL_LOW */
599	};
600
601	for (i = 0; i < 32; i++) {
602		if ((port->wakeup_pads & (1 << i))) {
603			type = port->pad_type[i];
604			if (enable)
605				config = pad_type_map[type];
606			else
607				config = IMX_SCU_WAKEUP_OFF;
608
609			if (is_imx8qm && config == IMX_SCU_WAKEUP_FALL_EDGE) {
610				dev_warn_once(port->dev,
611					      "No falling-edge support for wakeup on i.MX8QM\n");
612				config = IMX_SCU_WAKEUP_OFF;
613			}
614
615			ret |= mxc_gpio_generic_config(port, i, config);
616		}
617	}
618
619	return ret;
620}
621
622static int mxc_gpio_runtime_suspend(struct device *dev)
623{
624	struct mxc_gpio_port *port = dev_get_drvdata(dev);
625
626	mxc_gpio_save_regs(port);
627	clk_disable_unprepare(port->clk);
628	mxc_update_irq_chained_handler(port, false);
629
630	return 0;
631}
632
633static int mxc_gpio_runtime_resume(struct device *dev)
634{
635	struct mxc_gpio_port *port = dev_get_drvdata(dev);
636	int ret;
637
638	mxc_update_irq_chained_handler(port, true);
639	ret = clk_prepare_enable(port->clk);
640	if (ret) {
641		mxc_update_irq_chained_handler(port, false);
642		return ret;
643	}
644
645	mxc_gpio_restore_regs(port);
646
647	return 0;
648}
649
650static int mxc_gpio_noirq_suspend(struct device *dev)
651{
652	struct platform_device *pdev = to_platform_device(dev);
653	struct mxc_gpio_port *port = platform_get_drvdata(pdev);
654
655	if (port->wakeup_pads > 0)
656		port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true);
657
658	return 0;
659}
660
661static int mxc_gpio_noirq_resume(struct device *dev)
662{
663	struct platform_device *pdev = to_platform_device(dev);
664	struct mxc_gpio_port *port = platform_get_drvdata(pdev);
665
666	if (port->wakeup_pads > 0)
667		mxc_gpio_set_pad_wakeup(port, false);
668	port->is_pad_wakeup = false;
669
670	return 0;
671}
672
673static const struct dev_pm_ops mxc_gpio_dev_pm_ops = {
674	NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume)
675	RUNTIME_PM_OPS(mxc_gpio_runtime_suspend, mxc_gpio_runtime_resume, NULL)
676};
677
678static int mxc_gpio_syscore_suspend(void *data)
679{
680	struct mxc_gpio_port *port;
681	int ret;
682
683	/* walk through all ports */
684	list_for_each_entry(port, &mxc_gpio_ports, node) {
685		ret = clk_prepare_enable(port->clk);
686		if (ret)
687			return ret;
688		mxc_gpio_save_regs(port);
689		clk_disable_unprepare(port->clk);
690	}
691
692	return 0;
693}
694
695static void mxc_gpio_syscore_resume(void *data)
696{
697	struct mxc_gpio_port *port;
698	int ret;
699
700	/* walk through all ports */
701	list_for_each_entry(port, &mxc_gpio_ports, node) {
702		ret = clk_prepare_enable(port->clk);
703		if (ret) {
704			pr_err("mxc: failed to enable gpio clock %d\n", ret);
705			return;
706		}
707		mxc_gpio_restore_regs(port);
708		clk_disable_unprepare(port->clk);
709	}
710}
711
712static const struct syscore_ops mxc_gpio_syscore_ops = {
713	.suspend = mxc_gpio_syscore_suspend,
714	.resume = mxc_gpio_syscore_resume,
715};
716
717static struct syscore mxc_gpio_syscore = {
718	.ops = &mxc_gpio_syscore_ops,
719};
720
721static struct platform_driver mxc_gpio_driver = {
722	.driver		= {
723		.name	= "gpio-mxc",
724		.of_match_table = mxc_gpio_dt_ids,
725		.suppress_bind_attrs = true,
726		.pm = pm_ptr(&mxc_gpio_dev_pm_ops),
727	},
728	.probe		= mxc_gpio_probe,
729};
730
731static int __init gpio_mxc_init(void)
732{
733	register_syscore(&mxc_gpio_syscore);
734
735	return platform_driver_register(&mxc_gpio_driver);
736}
737subsys_initcall(gpio_mxc_init);
738
739MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
740MODULE_DESCRIPTION("i.MX GPIO Driver");
741MODULE_LICENSE("GPL");