gpio-mvebu.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * GPIO driver for Marvell SoCs
   4 *
   5 * Copyright (C) 2012 Marvell
   6 *
   7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   8 * Andrew Lunn <andrew@lunn.ch>
   9 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  10 *
  11 * This driver is a fairly straightforward GPIO driver for the
  12 * complete family of Marvell EBU SoC platforms (Orion, Dove,
  13 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
  14 * driver is the different register layout that exists between the
  15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
  16 * platforms (MV78200 from the Discovery family and the Armada
  17 * XP). Therefore, this driver handles three variants of the GPIO
  18 * block:
  19 * - the basic variant, called "orion-gpio", with the simplest
  20 *   register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
  21 *   non-SMP Discovery systems
  22 * - the mv78200 variant for MV78200 Discovery systems. This variant
  23 *   turns the edge mask and level mask registers into CPU0 edge
  24 *   mask/level mask registers, and adds CPU1 edge mask/level mask
  25 *   registers.
  26 * - the armadaxp variant for Armada XP systems. This variant keeps
  27 *   the normal cause/edge mask/level mask registers when the global
  28 *   interrupts are used, but adds per-CPU cause/edge mask/level mask
  29 *   registers n a separate memory area for the per-CPU GPIO
  30 *   interrupts.
  31 */
  32
  33#include <linux/bitops.h>
  34#include <linux/clk.h>
  35#include <linux/err.h>
  36#include <linux/gpio/driver.h>
  37#include <linux/gpio/consumer.h>
  38#include <linux/gpio/machine.h>
  39#include <linux/init.h>
  40#include <linux/io.h>
  41#include <linux/irq.h>
  42#include <linux/irqchip/chained_irq.h>
  43#include <linux/irqdomain.h>
  44#include <linux/mfd/syscon.h>
  45#include <linux/of.h>
  46#include <linux/pinctrl/consumer.h>
  47#include <linux/platform_device.h>
  48#include <linux/property.h>
  49#include <linux/pwm.h>
  50#include <linux/regmap.h>
  51#include <linux/slab.h>
  52#include <linux/string_choices.h>
  53
  54/*
  55 * GPIO unit register offsets.
  56 */
  57#define GPIO_OUT_OFF			0x0000
  58#define GPIO_IO_CONF_OFF		0x0004
  59#define GPIO_BLINK_EN_OFF		0x0008
  60#define GPIO_IN_POL_OFF			0x000c
  61#define GPIO_DATA_IN_OFF		0x0010
  62#define GPIO_EDGE_CAUSE_OFF		0x0014
  63#define GPIO_EDGE_MASK_OFF		0x0018
  64#define GPIO_LEVEL_MASK_OFF		0x001c
  65#define GPIO_BLINK_CNT_SELECT_OFF	0x0020
  66
  67/*
  68 * PWM register offsets.
  69 */
  70#define PWM_BLINK_ON_DURATION_OFF	0x0
  71#define PWM_BLINK_OFF_DURATION_OFF	0x4
  72#define PWM_BLINK_COUNTER_B_OFF		0x8
  73
  74/* Armada 8k variant gpios register offsets */
  75#define AP80X_GPIO0_OFF_A8K		0x1040
  76#define CP11X_GPIO0_OFF_A8K		0x100
  77#define CP11X_GPIO1_OFF_A8K		0x140
  78
  79/* The MV78200 has per-CPU registers for edge mask and level mask */
  80#define GPIO_EDGE_MASK_MV78200_OFF(cpu)	  ((cpu) ? 0x30 : 0x18)
  81#define GPIO_LEVEL_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x34 : 0x1C)
  82
  83/*
  84 * The Armada XP has per-CPU registers for interrupt cause, interrupt
  85 * mask and interrupt level mask. Those are in percpu_regs range.
  86 */
  87#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
  88#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
  89#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
  90
  91#define MVEBU_GPIO_SOC_VARIANT_ORION	0x1
  92#define MVEBU_GPIO_SOC_VARIANT_MV78200	0x2
  93#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
  94#define MVEBU_GPIO_SOC_VARIANT_A8K	0x4
  95
  96#define MVEBU_MAX_GPIO_PER_BANK		32
  97
  98struct mvebu_pwm {
  99	struct regmap		*regs;
 100	u32			 offset;
 101	unsigned long		 clk_rate;
 102	struct gpio_desc	*gpiod;
 103	spinlock_t		 lock;
 104	struct mvebu_gpio_chip	*mvchip;
 105
 106	/* Used to preserve GPIO/PWM registers across suspend/resume */
 107	u32			 blink_select;
 108	u32			 blink_on_duration;
 109	u32			 blink_off_duration;
 110};
 111
 112struct mvebu_gpio_chip {
 113	struct gpio_chip   chip;
 114	struct regmap     *regs;
 115	u32		   offset;
 116	struct regmap     *percpu_regs;
 117	int		   irqbase;
 118	struct irq_domain *domain;
 119	int		   soc_variant;
 120
 121	/* Used for PWM support */
 122	struct clk	  *clk;
 123	struct mvebu_pwm  *mvpwm;
 124
 125	/* Used to preserve GPIO registers across suspend/resume */
 126	u32		   out_reg;
 127	u32		   io_conf_reg;
 128	u32		   blink_en_reg;
 129	u32		   in_pol_reg;
 130	u32		   edge_mask_regs[4];
 131	u32		   level_mask_regs[4];
 132};
 133
 134/*
 135 * Functions returning addresses of individual registers for a given
 136 * GPIO controller.
 137 */
 138
 139static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
 140			 struct regmap **map, unsigned int *offset)
 141{
 142	int cpu;
 143
 144	switch (mvchip->soc_variant) {
 145	case MVEBU_GPIO_SOC_VARIANT_ORION:
 146	case MVEBU_GPIO_SOC_VARIANT_MV78200:
 147	case MVEBU_GPIO_SOC_VARIANT_A8K:
 148		*map = mvchip->regs;
 149		*offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
 150		break;
 151	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
 152		cpu = smp_processor_id();
 153		*map = mvchip->percpu_regs;
 154		*offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
 155		break;
 156	default:
 157		BUG();
 158	}
 159}
 160
 161static u32
 162mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
 163{
 164	struct regmap *map;
 165	unsigned int offset;
 166	u32 val;
 167
 168	mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
 169	regmap_read(map, offset, &val);
 170
 171	return val;
 172}
 173
 174static void
 175mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
 176{
 177	struct regmap *map;
 178	unsigned int offset;
 179
 180	mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
 181	regmap_write(map, offset, val);
 182}
 183
 184static inline void
 185mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
 186			struct regmap **map, unsigned int *offset)
 187{
 188	int cpu;
 189
 190	switch (mvchip->soc_variant) {
 191	case MVEBU_GPIO_SOC_VARIANT_ORION:
 192	case MVEBU_GPIO_SOC_VARIANT_A8K:
 193		*map = mvchip->regs;
 194		*offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
 195		break;
 196	case MVEBU_GPIO_SOC_VARIANT_MV78200:
 197		cpu = smp_processor_id();
 198		*map = mvchip->regs;
 199		*offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
 200		break;
 201	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
 202		cpu = smp_processor_id();
 203		*map = mvchip->percpu_regs;
 204		*offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
 205		break;
 206	default:
 207		BUG();
 208	}
 209}
 210
 211static u32
 212mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
 213{
 214	struct regmap *map;
 215	unsigned int offset;
 216	u32 val;
 217
 218	mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
 219	regmap_read(map, offset, &val);
 220
 221	return val;
 222}
 223
 224static void
 225mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
 226{
 227	struct regmap *map;
 228	unsigned int offset;
 229
 230	mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
 231	regmap_write(map, offset, val);
 232}
 233
 234static void
 235mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
 236			 struct regmap **map, unsigned int *offset)
 237{
 238	int cpu;
 239
 240	switch (mvchip->soc_variant) {
 241	case MVEBU_GPIO_SOC_VARIANT_ORION:
 242	case MVEBU_GPIO_SOC_VARIANT_A8K:
 243		*map = mvchip->regs;
 244		*offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
 245		break;
 246	case MVEBU_GPIO_SOC_VARIANT_MV78200:
 247		cpu = smp_processor_id();
 248		*map = mvchip->regs;
 249		*offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
 250		break;
 251	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
 252		cpu = smp_processor_id();
 253		*map = mvchip->percpu_regs;
 254		*offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
 255		break;
 256	default:
 257		BUG();
 258	}
 259}
 260
 261static u32
 262mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
 263{
 264	struct regmap *map;
 265	unsigned int offset;
 266	u32 val;
 267
 268	mvebu_gpioreg_level_mask(mvchip, &map, &offset);
 269	regmap_read(map, offset, &val);
 270
 271	return val;
 272}
 273
 274static void
 275mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
 276{
 277	struct regmap *map;
 278	unsigned int offset;
 279
 280	mvebu_gpioreg_level_mask(mvchip, &map, &offset);
 281	regmap_write(map, offset, val);
 282}
 283
 284/*
 285 * Functions returning offsets of individual registers for a given
 286 * PWM controller.
 287 */
 288static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
 289{
 290	return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF;
 291}
 292
 293static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
 294{
 295	return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF;
 296}
 297
 298/*
 299 * Functions implementing the gpio_chip methods
 300 */
 301static int mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
 302{
 303	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 304
 305	return regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
 306				  BIT(pin), value ? BIT(pin) : 0);
 307}
 308
 309static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
 310{
 311	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 312	u32 u;
 313
 314	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
 315
 316	if (u & BIT(pin)) {
 317		u32 data_in, in_pol;
 318
 319		regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
 320			    &data_in);
 321		regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
 322			    &in_pol);
 323		u = data_in ^ in_pol;
 324	} else {
 325		regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
 326	}
 327
 328	return (u >> pin) & 1;
 329}
 330
 331static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
 332			     int value)
 333{
 334	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 335
 336	regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
 337			   BIT(pin), value ? BIT(pin) : 0);
 338}
 339
 340static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
 341{
 342	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 343	int ret;
 344
 345	/*
 346	 * Check with the pinctrl driver whether this pin is usable as
 347	 * an input GPIO
 348	 */
 349	ret = pinctrl_gpio_direction_input(chip, pin);
 350	if (ret)
 351		return ret;
 352
 353	regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
 354			   BIT(pin), BIT(pin));
 355
 356	return 0;
 357}
 358
 359static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
 360				       int value)
 361{
 362	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 363	int ret;
 364
 365	/*
 366	 * Check with the pinctrl driver whether this pin is usable as
 367	 * an output GPIO
 368	 */
 369	ret = pinctrl_gpio_direction_output(chip, pin);
 370	if (ret)
 371		return ret;
 372
 373	mvebu_gpio_blink(chip, pin, 0);
 374	mvebu_gpio_set(chip, pin, value);
 375
 376	regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
 377			   BIT(pin), 0);
 378
 379	return 0;
 380}
 381
 382static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
 383{
 384	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 385	u32 u;
 386
 387	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
 388
 389	if (u & BIT(pin))
 390		return GPIO_LINE_DIRECTION_IN;
 391
 392	return GPIO_LINE_DIRECTION_OUT;
 393}
 394
 395static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
 396{
 397	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 398
 399	return irq_create_mapping(mvchip->domain, pin);
 400}
 401
 402/*
 403 * Functions implementing the irq_chip methods
 404 */
 405static void mvebu_gpio_irq_ack(struct irq_data *d)
 406{
 407	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 408	struct mvebu_gpio_chip *mvchip = gc->private;
 409	u32 mask = d->mask;
 410
 411	guard(raw_spinlock)(&gc->lock);
 412	mvebu_gpio_write_edge_cause(mvchip, ~mask);
 413}
 414
 415static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
 416{
 417	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 418	struct mvebu_gpio_chip *mvchip = gc->private;
 419	struct irq_chip_type *ct = irq_data_get_chip_type(d);
 420	u32 mask = d->mask;
 421
 422	guard(raw_spinlock)(&gc->lock);
 423	ct->mask_cache_priv &= ~mask;
 424	mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
 425}
 426
 427static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
 428{
 429	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 430	struct mvebu_gpio_chip *mvchip = gc->private;
 431	struct irq_chip_type *ct = irq_data_get_chip_type(d);
 432	u32 mask = d->mask;
 433
 434	guard(raw_spinlock)(&gc->lock);
 435	mvebu_gpio_write_edge_cause(mvchip, ~mask);
 436	ct->mask_cache_priv |= mask;
 437	mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
 438}
 439
 440static void mvebu_gpio_level_irq_mask(struct irq_data *d)
 441{
 442	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 443	struct mvebu_gpio_chip *mvchip = gc->private;
 444	struct irq_chip_type *ct = irq_data_get_chip_type(d);
 445	u32 mask = d->mask;
 446
 447	guard(raw_spinlock)(&gc->lock);
 448	ct->mask_cache_priv &= ~mask;
 449	mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
 450}
 451
 452static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
 453{
 454	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 455	struct mvebu_gpio_chip *mvchip = gc->private;
 456	struct irq_chip_type *ct = irq_data_get_chip_type(d);
 457	u32 mask = d->mask;
 458
 459	guard(raw_spinlock)(&gc->lock);
 460	ct->mask_cache_priv |= mask;
 461	mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
 462}
 463
 464/*****************************************************************************
 465 * MVEBU GPIO IRQ
 466 *
 467 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
 468 * value of the line or the opposite value.
 469 *
 470 * Level IRQ handlers: DATA_IN is used directly as cause register.
 471 *		       Interrupt are masked by LEVEL_MASK registers.
 472 * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
 473 *		       Interrupt are masked by EDGE_MASK registers.
 474 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
 475 *		       the polarity to catch the next line transaction.
 476 *		       This is a race condition that might not perfectly
 477 *		       work on some use cases.
 478 *
 479 * Every eight GPIO lines are grouped (OR'ed) before going up to main
 480 * cause register.
 481 *
 482 *		      EDGE  cause    mask
 483 *	  data-in   /--------| |-----| |----\
 484 *     -----| |-----			     ---- to main cause reg
 485 *	     X	    \----------------| |----/
 486 *	  polarity    LEVEL	     mask
 487 *
 488 ****************************************************************************/
 489
 490static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 491{
 492	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 493	struct irq_chip_type *ct = irq_data_get_chip_type(d);
 494	struct mvebu_gpio_chip *mvchip = gc->private;
 495	int pin;
 496	u32 u;
 497
 498	pin = d->hwirq;
 499
 500	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
 501	if ((u & BIT(pin)) == 0)
 502		return -EINVAL;
 503
 504	type &= IRQ_TYPE_SENSE_MASK;
 505	if (type == IRQ_TYPE_NONE)
 506		return -EINVAL;
 507
 508	/* Check if we need to change chip and handler */
 509	if (!(ct->type & type))
 510		if (irq_setup_alt_chip(d, type))
 511			return -EINVAL;
 512
 513	/*
 514	 * Configure interrupt polarity.
 515	 */
 516	switch (type) {
 517	case IRQ_TYPE_EDGE_RISING:
 518	case IRQ_TYPE_LEVEL_HIGH:
 519		regmap_update_bits(mvchip->regs,
 520				   GPIO_IN_POL_OFF + mvchip->offset,
 521				   BIT(pin), 0);
 522		break;
 523	case IRQ_TYPE_EDGE_FALLING:
 524	case IRQ_TYPE_LEVEL_LOW:
 525		regmap_update_bits(mvchip->regs,
 526				   GPIO_IN_POL_OFF + mvchip->offset,
 527				   BIT(pin), BIT(pin));
 528		break;
 529	case IRQ_TYPE_EDGE_BOTH: {
 530		u32 data_in, in_pol, val;
 531
 532		regmap_read(mvchip->regs,
 533			    GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
 534		regmap_read(mvchip->regs,
 535			    GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
 536
 537		/*
 538		 * set initial polarity based on current input level
 539		 */
 540		if ((data_in ^ in_pol) & BIT(pin))
 541			val = BIT(pin); /* falling */
 542		else
 543			val = 0; /* raising */
 544
 545		regmap_update_bits(mvchip->regs,
 546				   GPIO_IN_POL_OFF + mvchip->offset,
 547				   BIT(pin), val);
 548		break;
 549	}
 550	}
 551	return 0;
 552}
 553
 554static void mvebu_gpio_irq_handler(struct irq_desc *desc)
 555{
 556	struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
 557	struct irq_chip *chip = irq_desc_get_chip(desc);
 558	u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
 559	int i;
 560
 561	if (mvchip == NULL)
 562		return;
 563
 564	chained_irq_enter(chip, desc);
 565
 566	regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
 567	level_mask = mvebu_gpio_read_level_mask(mvchip);
 568	edge_cause = mvebu_gpio_read_edge_cause(mvchip);
 569	edge_mask  = mvebu_gpio_read_edge_mask(mvchip);
 570
 571	cause = (data_in & level_mask) | (edge_cause & edge_mask);
 572
 573	for (i = 0; i < mvchip->chip.ngpio; i++) {
 574		int irq;
 575
 576		if (!(cause & BIT(i)))
 577			continue;
 578
 579		irq = irq_find_mapping(mvchip->domain, i);
 580		type = irq_get_trigger_type(irq);
 581		if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 582			/* Swap polarity (race with GPIO line) */
 583			u32 polarity;
 584
 585			regmap_read(mvchip->regs,
 586				    GPIO_IN_POL_OFF + mvchip->offset,
 587				    &polarity);
 588			polarity ^= BIT(i);
 589			regmap_write(mvchip->regs,
 590				     GPIO_IN_POL_OFF + mvchip->offset,
 591				     polarity);
 592		}
 593
 594		generic_handle_irq(irq);
 595	}
 596
 597	chained_irq_exit(chip, desc);
 598}
 599
 600static const struct regmap_config mvebu_gpio_regmap_config = {
 601	.reg_bits = 32,
 602	.reg_stride = 4,
 603	.val_bits = 32,
 604};
 605
 606/*
 607 * Functions implementing the pwm_chip methods
 608 */
 609static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
 610{
 611	return pwmchip_get_drvdata(chip);
 612}
 613
 614static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
 615{
 616	struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
 617	struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
 618	struct gpio_desc *desc;
 619	unsigned long flags;
 620	int ret = 0;
 621
 622	spin_lock_irqsave(&mvpwm->lock, flags);
 623
 624	if (mvpwm->gpiod) {
 625		ret = -EBUSY;
 626	} else {
 627		desc = gpiochip_request_own_desc(&mvchip->chip,
 628						 pwm->hwpwm, "mvebu-pwm",
 629						 GPIO_ACTIVE_HIGH,
 630						 GPIOD_OUT_LOW);
 631		if (IS_ERR(desc)) {
 632			ret = PTR_ERR(desc);
 633			goto out;
 634		}
 635
 636		mvpwm->gpiod = desc;
 637	}
 638out:
 639	spin_unlock_irqrestore(&mvpwm->lock, flags);
 640	return ret;
 641}
 642
 643static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 644{
 645	struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
 646	unsigned long flags;
 647
 648	spin_lock_irqsave(&mvpwm->lock, flags);
 649	gpiochip_free_own_desc(mvpwm->gpiod);
 650	mvpwm->gpiod = NULL;
 651	spin_unlock_irqrestore(&mvpwm->lock, flags);
 652}
 653
 654static int mvebu_pwm_get_state(struct pwm_chip *chip,
 655			       struct pwm_device *pwm,
 656			       struct pwm_state *state)
 657{
 658
 659	struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
 660	struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
 661	unsigned long long val;
 662	unsigned long flags;
 663	u32 u;
 664
 665	spin_lock_irqsave(&mvpwm->lock, flags);
 666
 667	regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u);
 668	/* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */
 669	if (u > 0)
 670		val = u;
 671	else
 672		val = UINT_MAX + 1ULL;
 673	state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC,
 674			mvpwm->clk_rate);
 675
 676	regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u);
 677	/* period = on + off duration */
 678	if (u > 0)
 679		val += u;
 680	else
 681		val += UINT_MAX + 1ULL;
 682	state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate);
 683
 684	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
 685	if (u)
 686		state->enabled = true;
 687	else
 688		state->enabled = false;
 689
 690	spin_unlock_irqrestore(&mvpwm->lock, flags);
 691
 692	return 0;
 693}
 694
 695static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 696			   const struct pwm_state *state)
 697{
 698	struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
 699	struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
 700	unsigned long long val;
 701	unsigned long flags;
 702	unsigned int on, off;
 703
 704	if (state->polarity != PWM_POLARITY_NORMAL)
 705		return -EINVAL;
 706
 707	val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
 708	do_div(val, NSEC_PER_SEC);
 709	if (val > UINT_MAX + 1ULL)
 710		return -EINVAL;
 711	/*
 712	 * Zero on/off values don't work as expected. Experimentation shows
 713	 * that zero value is treated as 2^32. This behavior is not documented.
 714	 */
 715	if (val == UINT_MAX + 1ULL)
 716		on = 0;
 717	else if (val)
 718		on = val;
 719	else
 720		on = 1;
 721
 722	val = (unsigned long long) mvpwm->clk_rate * state->period;
 723	do_div(val, NSEC_PER_SEC);
 724	val -= on;
 725	if (val > UINT_MAX + 1ULL)
 726		return -EINVAL;
 727	if (val == UINT_MAX + 1ULL)
 728		off = 0;
 729	else if (val)
 730		off = val;
 731	else
 732		off = 1;
 733
 734	spin_lock_irqsave(&mvpwm->lock, flags);
 735
 736	regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on);
 737	regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off);
 738	if (state->enabled)
 739		mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
 740	else
 741		mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
 742
 743	spin_unlock_irqrestore(&mvpwm->lock, flags);
 744
 745	return 0;
 746}
 747
 748static const struct pwm_ops mvebu_pwm_ops = {
 749	.request = mvebu_pwm_request,
 750	.free = mvebu_pwm_free,
 751	.get_state = mvebu_pwm_get_state,
 752	.apply = mvebu_pwm_apply,
 753};
 754
 755static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
 756{
 757	struct mvebu_pwm *mvpwm = mvchip->mvpwm;
 758
 759	regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
 760		    &mvpwm->blink_select);
 761	regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
 762		    &mvpwm->blink_on_duration);
 763	regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
 764		    &mvpwm->blink_off_duration);
 765}
 766
 767static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
 768{
 769	struct mvebu_pwm *mvpwm = mvchip->mvpwm;
 770
 771	regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
 772		     mvpwm->blink_select);
 773	regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
 774		     mvpwm->blink_on_duration);
 775	regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
 776		     mvpwm->blink_off_duration);
 777}
 778
 779static int mvebu_pwm_probe(struct platform_device *pdev,
 780			   struct mvebu_gpio_chip *mvchip,
 781			   int id)
 782{
 783	struct device *dev = &pdev->dev;
 784	struct mvebu_pwm *mvpwm;
 785	struct pwm_chip *chip;
 786	void __iomem *base;
 787	u32 offset;
 788	u32 set;
 789
 790	if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
 791		int ret = device_property_read_u32(dev, "marvell,pwm-offset",
 792						   &offset);
 793		if (ret < 0)
 794			return 0;
 795	} else {
 796		/*
 797		 * There are only two sets of PWM configuration registers for
 798		 * all the GPIO lines on those SoCs which this driver reserves
 799		 * for the first two GPIO chips. So if the resource is missing
 800		 * we can't treat it as an error.
 801		 */
 802		if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
 803			return 0;
 804		offset = 0;
 805	}
 806
 807	if (IS_ERR(mvchip->clk))
 808		return PTR_ERR(mvchip->clk);
 809
 810	chip = devm_pwmchip_alloc(dev, mvchip->chip.ngpio, sizeof(*mvpwm));
 811	if (IS_ERR(chip))
 812		return PTR_ERR(chip);
 813	mvpwm = to_mvebu_pwm(chip);
 814
 815	mvchip->mvpwm = mvpwm;
 816	mvpwm->mvchip = mvchip;
 817	mvpwm->offset = offset;
 818
 819	if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
 820		mvpwm->regs = mvchip->regs;
 821
 822		switch (mvchip->offset) {
 823		case AP80X_GPIO0_OFF_A8K:
 824		case CP11X_GPIO0_OFF_A8K:
 825			/* Blink counter A */
 826			set = 0;
 827			break;
 828		case CP11X_GPIO1_OFF_A8K:
 829			/* Blink counter B */
 830			set = U32_MAX;
 831			mvpwm->offset += PWM_BLINK_COUNTER_B_OFF;
 832			break;
 833		default:
 834			return -EINVAL;
 835		}
 836	} else {
 837		base = devm_platform_ioremap_resource_byname(pdev, "pwm");
 838		if (IS_ERR(base))
 839			return PTR_ERR(base);
 840
 841		mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base,
 842						    &mvebu_gpio_regmap_config);
 843		if (IS_ERR(mvpwm->regs))
 844			return PTR_ERR(mvpwm->regs);
 845
 846		/*
 847		 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
 848		 * with id 1. Don't allow further GPIO chips to be used for PWM.
 849		 */
 850		if (id == 0)
 851			set = 0;
 852		else if (id == 1)
 853			set = U32_MAX;
 854		else
 855			return -EINVAL;
 856	}
 857
 858	regmap_write(mvchip->regs,
 859		     GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
 860
 861	mvpwm->clk_rate = clk_get_rate(mvchip->clk);
 862	if (!mvpwm->clk_rate) {
 863		dev_err(dev, "failed to get clock rate\n");
 864		return -EINVAL;
 865	}
 866
 867	chip->ops = &mvebu_pwm_ops;
 868
 869	spin_lock_init(&mvpwm->lock);
 870
 871	return devm_pwmchip_add(dev, chip);
 872}
 873
 874#ifdef CONFIG_DEBUG_FS
 875#include <linux/seq_file.h>
 876
 877static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 878{
 879	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
 880	u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
 881	const char *label;
 882	int i;
 883
 884	regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
 885	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
 886	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
 887	regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
 888	regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
 889	cause	= mvebu_gpio_read_edge_cause(mvchip);
 890	edg_msk	= mvebu_gpio_read_edge_mask(mvchip);
 891	lvl_msk	= mvebu_gpio_read_level_mask(mvchip);
 892
 893	for_each_requested_gpio(chip, i, label) {
 894		u32 msk;
 895		bool is_out;
 896
 897		msk = BIT(i);
 898		is_out = !(io_conf & msk);
 899
 900		seq_printf(s, " gpio-%-3d (%-20.20s)", i, label);
 901
 902		if (is_out) {
 903			seq_printf(s, " out %s %s\n",
 904				   str_hi_lo(out & msk),
 905				   blink & msk ? "(blink )" : "");
 906			continue;
 907		}
 908
 909		seq_printf(s, " in  %s (act %s) - IRQ",
 910			   str_hi_lo((data_in ^ in_pol) & msk),
 911			   str_lo_hi(in_pol & msk));
 912		if (!((edg_msk | lvl_msk) & msk)) {
 913			seq_puts(s, " disabled\n");
 914			continue;
 915		}
 916		if (edg_msk & msk)
 917			seq_puts(s, " edge ");
 918		if (lvl_msk & msk)
 919			seq_puts(s, " level");
 920		seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear  ");
 921	}
 922}
 923#else
 924#define mvebu_gpio_dbg_show NULL
 925#endif
 926
 927static const struct of_device_id mvebu_gpio_of_match[] = {
 928	{
 929		.compatible = "marvell,orion-gpio",
 930		.data	    = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
 931	},
 932	{
 933		.compatible = "marvell,mv78200-gpio",
 934		.data	    = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
 935	},
 936	{
 937		.compatible = "marvell,armadaxp-gpio",
 938		.data	    = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
 939	},
 940	{
 941		.compatible = "marvell,armada-370-gpio",
 942		.data	    = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
 943	},
 944	{
 945		.compatible = "marvell,armada-8k-gpio",
 946		.data       = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
 947	},
 948	{
 949		/* sentinel */
 950	},
 951};
 952
 953static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
 954{
 955	struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
 956	int i;
 957
 958	regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
 959		    &mvchip->out_reg);
 960	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
 961		    &mvchip->io_conf_reg);
 962	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
 963		    &mvchip->blink_en_reg);
 964	regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
 965		    &mvchip->in_pol_reg);
 966
 967	switch (mvchip->soc_variant) {
 968	case MVEBU_GPIO_SOC_VARIANT_ORION:
 969	case MVEBU_GPIO_SOC_VARIANT_A8K:
 970		regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
 971			    &mvchip->edge_mask_regs[0]);
 972		regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
 973			    &mvchip->level_mask_regs[0]);
 974		break;
 975	case MVEBU_GPIO_SOC_VARIANT_MV78200:
 976		for (i = 0; i < 2; i++) {
 977			regmap_read(mvchip->regs,
 978				    GPIO_EDGE_MASK_MV78200_OFF(i),
 979				    &mvchip->edge_mask_regs[i]);
 980			regmap_read(mvchip->regs,
 981				    GPIO_LEVEL_MASK_MV78200_OFF(i),
 982				    &mvchip->level_mask_regs[i]);
 983		}
 984		break;
 985	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
 986		for (i = 0; i < 4; i++) {
 987			regmap_read(mvchip->regs,
 988				    GPIO_EDGE_MASK_ARMADAXP_OFF(i),
 989				    &mvchip->edge_mask_regs[i]);
 990			regmap_read(mvchip->regs,
 991				    GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
 992				    &mvchip->level_mask_regs[i]);
 993		}
 994		break;
 995	default:
 996		BUG();
 997	}
 998
 999	if (IS_REACHABLE(CONFIG_PWM))
1000		mvebu_pwm_suspend(mvchip);
1001
1002	return 0;
1003}
1004
1005static int mvebu_gpio_resume(struct platform_device *pdev)
1006{
1007	struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
1008	int i;
1009
1010	regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
1011		     mvchip->out_reg);
1012	regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
1013		     mvchip->io_conf_reg);
1014	regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
1015		     mvchip->blink_en_reg);
1016	regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
1017		     mvchip->in_pol_reg);
1018
1019	switch (mvchip->soc_variant) {
1020	case MVEBU_GPIO_SOC_VARIANT_ORION:
1021	case MVEBU_GPIO_SOC_VARIANT_A8K:
1022		regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
1023			     mvchip->edge_mask_regs[0]);
1024		regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
1025			     mvchip->level_mask_regs[0]);
1026		break;
1027	case MVEBU_GPIO_SOC_VARIANT_MV78200:
1028		for (i = 0; i < 2; i++) {
1029			regmap_write(mvchip->regs,
1030				     GPIO_EDGE_MASK_MV78200_OFF(i),
1031				     mvchip->edge_mask_regs[i]);
1032			regmap_write(mvchip->regs,
1033				     GPIO_LEVEL_MASK_MV78200_OFF(i),
1034				     mvchip->level_mask_regs[i]);
1035		}
1036		break;
1037	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1038		for (i = 0; i < 4; i++) {
1039			regmap_write(mvchip->regs,
1040				     GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1041				     mvchip->edge_mask_regs[i]);
1042			regmap_write(mvchip->regs,
1043				     GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1044				     mvchip->level_mask_regs[i]);
1045		}
1046		break;
1047	default:
1048		BUG();
1049	}
1050
1051	if (IS_REACHABLE(CONFIG_PWM))
1052		mvebu_pwm_resume(mvchip);
1053
1054	return 0;
1055}
1056
1057static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1058				struct mvebu_gpio_chip *mvchip)
1059{
1060	void __iomem *base;
1061
1062	base = devm_platform_ioremap_resource(pdev, 0);
1063	if (IS_ERR(base))
1064		return PTR_ERR(base);
1065
1066	mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1067					     &mvebu_gpio_regmap_config);
1068	if (IS_ERR(mvchip->regs))
1069		return PTR_ERR(mvchip->regs);
1070
1071	/*
1072	 * For the legacy SoCs, the regmap directly maps to the GPIO
1073	 * registers, so no offset is needed.
1074	 */
1075	mvchip->offset = 0;
1076
1077	/*
1078	 * The Armada XP has a second range of registers for the
1079	 * per-CPU registers
1080	 */
1081	if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1082		base = devm_platform_ioremap_resource(pdev, 1);
1083		if (IS_ERR(base))
1084			return PTR_ERR(base);
1085
1086		mvchip->percpu_regs =
1087			devm_regmap_init_mmio(&pdev->dev, base,
1088					      &mvebu_gpio_regmap_config);
1089		if (IS_ERR(mvchip->percpu_regs))
1090			return PTR_ERR(mvchip->percpu_regs);
1091	}
1092
1093	return 0;
1094}
1095
1096static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1097				   struct mvebu_gpio_chip *mvchip)
1098{
1099	mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1100	if (IS_ERR(mvchip->regs))
1101		return PTR_ERR(mvchip->regs);
1102
1103	if (device_property_read_u32(&pdev->dev, "offset", &mvchip->offset))
1104		return -EINVAL;
1105
1106	return 0;
1107}
1108
1109static void mvebu_gpio_remove_irq_domain(void *data)
1110{
1111	struct irq_domain *domain = data;
1112
1113	irq_domain_remove(domain);
1114}
1115
1116static int mvebu_gpio_probe(struct platform_device *pdev)
1117{
1118	struct mvebu_gpio_chip *mvchip;
1119	struct device_node *np = pdev->dev.of_node;
1120	struct irq_chip_generic *gc;
1121	struct irq_chip_type *ct;
1122	unsigned int ngpios;
1123	bool have_irqs;
1124	int soc_variant;
1125	int i, cpu, id;
1126	int err;
1127
1128	soc_variant = (unsigned long)device_get_match_data(&pdev->dev);
1129
1130	/* Some gpio controllers do not provide irq support */
1131	err = platform_irq_count(pdev);
1132	if (err < 0)
1133		return err;
1134
1135	have_irqs = err != 0;
1136
1137	mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1138			      GFP_KERNEL);
1139	if (!mvchip)
1140		return -ENOMEM;
1141
1142	platform_set_drvdata(pdev, mvchip);
1143
1144	if (device_property_read_u32(&pdev->dev, "ngpios", &ngpios)) {
1145		dev_err(&pdev->dev, "Missing ngpios OF property\n");
1146		return -ENODEV;
1147	}
1148
1149	id = of_alias_get_id(pdev->dev.of_node, "gpio");
1150	if (id < 0) {
1151		dev_err(&pdev->dev, "Couldn't get OF id\n");
1152		return id;
1153	}
1154
1155	mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1156	/* Not all SoCs require a clock.*/
1157	if (!IS_ERR(mvchip->clk))
1158		clk_prepare_enable(mvchip->clk);
1159
1160	mvchip->soc_variant = soc_variant;
1161	mvchip->chip.label = dev_name(&pdev->dev);
1162	mvchip->chip.parent = &pdev->dev;
1163	mvchip->chip.request = gpiochip_generic_request;
1164	mvchip->chip.free = gpiochip_generic_free;
1165	mvchip->chip.get_direction = mvebu_gpio_get_direction;
1166	mvchip->chip.direction_input = mvebu_gpio_direction_input;
1167	mvchip->chip.get = mvebu_gpio_get;
1168	mvchip->chip.direction_output = mvebu_gpio_direction_output;
1169	mvchip->chip.set = mvebu_gpio_set;
1170	if (have_irqs)
1171		mvchip->chip.to_irq = mvebu_gpio_to_irq;
1172	mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1173	mvchip->chip.ngpio = ngpios;
1174	mvchip->chip.can_sleep = false;
1175	mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1176
1177	if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1178		err = mvebu_gpio_probe_syscon(pdev, mvchip);
1179	else
1180		err = mvebu_gpio_probe_raw(pdev, mvchip);
1181
1182	if (err)
1183		return err;
1184
1185	/*
1186	 * Mask and clear GPIO interrupts.
1187	 */
1188	switch (soc_variant) {
1189	case MVEBU_GPIO_SOC_VARIANT_ORION:
1190	case MVEBU_GPIO_SOC_VARIANT_A8K:
1191		regmap_write(mvchip->regs,
1192			     GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1193		regmap_write(mvchip->regs,
1194			     GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1195		regmap_write(mvchip->regs,
1196			     GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1197		break;
1198	case MVEBU_GPIO_SOC_VARIANT_MV78200:
1199		regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1200		for (cpu = 0; cpu < 2; cpu++) {
1201			regmap_write(mvchip->regs,
1202				     GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
1203			regmap_write(mvchip->regs,
1204				     GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
1205		}
1206		break;
1207	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1208		regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1209		regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1210		regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1211		for (cpu = 0; cpu < 4; cpu++) {
1212			regmap_write(mvchip->percpu_regs,
1213				     GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
1214			regmap_write(mvchip->percpu_regs,
1215				     GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
1216			regmap_write(mvchip->percpu_regs,
1217				     GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
1218		}
1219		break;
1220	default:
1221		BUG();
1222	}
1223
1224	devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1225
1226	/* Some MVEBU SoCs have simple PWM support for GPIO lines */
1227	if (IS_REACHABLE(CONFIG_PWM)) {
1228		err = mvebu_pwm_probe(pdev, mvchip, id);
1229		if (err)
1230			return err;
1231	}
1232
1233	/* Some gpio controllers do not provide irq support */
1234	if (!have_irqs)
1235		return 0;
1236
1237	mvchip->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), ngpios,
1238						  &irq_generic_chip_ops, NULL);
1239	if (!mvchip->domain) {
1240		dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1241			mvchip->chip.label);
1242		return -ENODEV;
1243	}
1244
1245	err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain,
1246				       mvchip->domain);
1247	if (err)
1248		return err;
1249
1250	err = irq_alloc_domain_generic_chips(
1251	    mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1252	    IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
1253	if (err) {
1254		dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1255			mvchip->chip.label);
1256		return err;
1257	}
1258
1259	/*
1260	 * NOTE: The common accessors cannot be used because of the percpu
1261	 * access to the mask registers
1262	 */
1263	gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1264	gc->private = mvchip;
1265	ct = &gc->chip_types[0];
1266	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
1267	ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1268	ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1269	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1270	ct->chip.name = mvchip->chip.label;
1271
1272	ct = &gc->chip_types[1];
1273	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1274	ct->chip.irq_ack = mvebu_gpio_irq_ack;
1275	ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1276	ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1277	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1278	ct->handler = handle_edge_irq;
1279	ct->chip.name = mvchip->chip.label;
1280
1281	/*
1282	 * Setup the interrupt handlers. Each chip can have up to 4
1283	 * interrupt handlers, with each handler dealing with 8 GPIO
1284	 * pins.
1285	 */
1286	for (i = 0; i < 4; i++) {
1287		int irq = platform_get_irq_optional(pdev, i);
1288
1289		if (irq < 0)
1290			continue;
1291		irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
1292						 mvchip);
1293	}
1294
1295	return 0;
1296}
1297
1298static struct platform_driver mvebu_gpio_driver = {
1299	.driver		= {
1300		.name		= "mvebu-gpio",
1301		.of_match_table = mvebu_gpio_of_match,
1302	},
1303	.probe		= mvebu_gpio_probe,
1304	.suspend        = mvebu_gpio_suspend,
1305	.resume         = mvebu_gpio_resume,
1306};
1307builtin_platform_driver(mvebu_gpio_driver);