gpio-mlxbf3.c

  1// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
  2/* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */
  3
  4#include <linux/bitfield.h>
  5#include <linux/bitops.h>
  6#include <linux/device.h>
  7#include <linux/err.h>
  8#include <linux/gpio/driver.h>
  9#include <linux/gpio/generic.h>
 10#include <linux/interrupt.h>
 11#include <linux/io.h>
 12#include <linux/module.h>
 13#include <linux/platform_device.h>
 14#include <linux/spinlock.h>
 15#include <linux/types.h>
 16
 17/*
 18 * There are 2 YU GPIO blocks:
 19 * gpio[0]: HOST_GPIO0->HOST_GPIO31
 20 * gpio[1]: HOST_GPIO32->HOST_GPIO55
 21 */
 22#define MLXBF3_GPIO_MAX_PINS_PER_BLOCK 32
 23#define MLXBF3_GPIO_MAX_PINS_BLOCK0    32
 24#define MLXBF3_GPIO_MAX_PINS_BLOCK1    24
 25
 26/*
 27 * fw_gpio[x] block registers and their offset
 28 */
 29#define MLXBF_GPIO_FW_OUTPUT_ENABLE_SET	  0x00
 30#define MLXBF_GPIO_FW_DATA_OUT_SET        0x04
 31
 32#define MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR 0x00
 33#define MLXBF_GPIO_FW_DATA_OUT_CLEAR      0x04
 34
 35#define MLXBF_GPIO_CAUSE_RISE_EN          0x00
 36#define MLXBF_GPIO_CAUSE_FALL_EN          0x04
 37#define MLXBF_GPIO_READ_DATA_IN           0x08
 38
 39#define MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0  0x00
 40#define MLXBF_GPIO_CAUSE_OR_EVTEN0        0x14
 41#define MLXBF_GPIO_CAUSE_OR_CLRCAUSE      0x18
 42
 43#define MLXBF_GPIO_CLR_ALL_INTS           GENMASK(31, 0)
 44
 45struct mlxbf3_gpio_context {
 46	struct gpio_generic_chip chip;
 47
 48	/* YU GPIO block address */
 49	void __iomem *gpio_set_io;
 50	void __iomem *gpio_clr_io;
 51	void __iomem *gpio_io;
 52
 53	/* YU GPIO cause block address */
 54	void __iomem *gpio_cause_io;
 55};
 56
 57static void mlxbf3_gpio_irq_enable(struct irq_data *irqd)
 58{
 59	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 60	struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
 61	irq_hw_number_t offset = irqd_to_hwirq(irqd);
 62	u32 val;
 63
 64	gpiochip_enable_irq(gc, offset);
 65
 66	guard(gpio_generic_lock_irqsave)(&gs->chip);
 67
 68	writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
 69
 70	val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
 71	val |= BIT(offset);
 72	writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
 73}
 74
 75static void mlxbf3_gpio_irq_disable(struct irq_data *irqd)
 76{
 77	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 78	struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
 79	irq_hw_number_t offset = irqd_to_hwirq(irqd);
 80	u32 val;
 81
 82	scoped_guard(gpio_generic_lock_irqsave, &gs->chip) {
 83		val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
 84		val &= ~BIT(offset);
 85		writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
 86
 87		writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
 88	}
 89
 90	gpiochip_disable_irq(gc, offset);
 91}
 92
 93static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr)
 94{
 95	struct mlxbf3_gpio_context *gs = ptr;
 96	struct gpio_chip *gc = &gs->chip.gc;
 97	unsigned long pending;
 98	u32 level;
 99
100	pending = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0);
101	writel(pending, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
102
103	for_each_set_bit(level, &pending, gc->ngpio)
104		generic_handle_domain_irq(gc->irq.domain, level);
105
106	return IRQ_RETVAL(pending);
107}
108
109static int
110mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
111{
112	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
113	struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
114	irq_hw_number_t offset = irqd_to_hwirq(irqd);
115	u32 val;
116
117	scoped_guard(gpio_generic_lock_irqsave, &gs->chip) {
118		switch (type & IRQ_TYPE_SENSE_MASK) {
119		case IRQ_TYPE_EDGE_BOTH:
120			val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
121			val |= BIT(offset);
122			writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
123			val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
124			val |= BIT(offset);
125			writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
126			break;
127		case IRQ_TYPE_EDGE_RISING:
128			val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
129			val |= BIT(offset);
130			writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
131			break;
132		case IRQ_TYPE_EDGE_FALLING:
133			val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
134			val |= BIT(offset);
135			writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
136			break;
137		default:
138			return -EINVAL;
139		}
140	}
141
142	irq_set_handler_locked(irqd, handle_edge_irq);
143
144	return 0;
145}
146
147/* This function needs to be defined for handle_edge_irq() */
148static void mlxbf3_gpio_irq_ack(struct irq_data *data)
149{
150}
151
152static const struct irq_chip gpio_mlxbf3_irqchip = {
153	.name = "MLNXBF33",
154	.irq_ack = mlxbf3_gpio_irq_ack,
155	.irq_set_type = mlxbf3_gpio_irq_set_type,
156	.irq_enable = mlxbf3_gpio_irq_enable,
157	.irq_disable = mlxbf3_gpio_irq_disable,
158	.flags = IRQCHIP_IMMUTABLE,
159	GPIOCHIP_IRQ_RESOURCE_HELPERS,
160};
161
162static int mlxbf3_gpio_add_pin_ranges(struct gpio_chip *chip)
163{
164	unsigned int id;
165
166	switch(chip->ngpio) {
167	case MLXBF3_GPIO_MAX_PINS_BLOCK0:
168		id = 0;
169		break;
170	case MLXBF3_GPIO_MAX_PINS_BLOCK1:
171		id = 1;
172		break;
173	default:
174		return -EINVAL;
175	}
176
177	return gpiochip_add_pin_range(chip, "MLNXBF34:00",
178			chip->base, id * MLXBF3_GPIO_MAX_PINS_PER_BLOCK,
179			chip->ngpio);
180}
181
182static int mlxbf3_gpio_probe(struct platform_device *pdev)
183{
184	struct gpio_generic_chip_config config;
185	struct device *dev = &pdev->dev;
186	struct mlxbf3_gpio_context *gs;
187	struct gpio_irq_chip *girq;
188	struct gpio_chip *gc;
189	int ret, irq;
190
191	gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL);
192	if (!gs)
193		return -ENOMEM;
194
195	gs->gpio_io = devm_platform_ioremap_resource(pdev, 0);
196	if (IS_ERR(gs->gpio_io))
197		return PTR_ERR(gs->gpio_io);
198
199	gs->gpio_cause_io = devm_platform_ioremap_resource(pdev, 1);
200	if (IS_ERR(gs->gpio_cause_io))
201		return PTR_ERR(gs->gpio_cause_io);
202
203	gs->gpio_set_io = devm_platform_ioremap_resource(pdev, 2);
204	if (IS_ERR(gs->gpio_set_io))
205		return PTR_ERR(gs->gpio_set_io);
206
207	gs->gpio_clr_io = devm_platform_ioremap_resource(pdev, 3);
208	if (IS_ERR(gs->gpio_clr_io))
209		return PTR_ERR(gs->gpio_clr_io);
210	gc = &gs->chip.gc;
211
212	config = (struct gpio_generic_chip_config) {
213		.dev = dev,
214		.sz = 4,
215		.dat = gs->gpio_io + MLXBF_GPIO_READ_DATA_IN,
216		.set = gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET,
217		.clr = gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR,
218		.dirout = gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET,
219		.dirin = gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR,
220	};
221
222	ret = gpio_generic_chip_init(&gs->chip, &config);
223	if (ret)
224		return dev_err_probe(dev, ret,
225				     "%s: failed to initialize the generic GPIO chip",
226				     __func__);
227
228	gc->request = gpiochip_generic_request;
229	gc->free = gpiochip_generic_free;
230	gc->owner = THIS_MODULE;
231	gc->add_pin_ranges = mlxbf3_gpio_add_pin_ranges;
232
233	irq = platform_get_irq_optional(pdev, 0);
234	if (irq >= 0) {
235		girq = &gs->chip.gc.irq;
236		gpio_irq_chip_set_chip(girq, &gpio_mlxbf3_irqchip);
237		girq->default_type = IRQ_TYPE_NONE;
238		/* This will let us handle the parent IRQ in the driver */
239		girq->num_parents = 0;
240		girq->parents = NULL;
241		girq->parent_handler = NULL;
242		girq->handler = handle_bad_irq;
243
244		/*
245		 * Directly request the irq here instead of passing
246		 * a flow-handler because the irq is shared.
247		 */
248		ret = devm_request_irq(dev, irq, mlxbf3_gpio_irq_handler,
249				       IRQF_SHARED, dev_name(dev), gs);
250		if (ret)
251			return dev_err_probe(dev, ret, "failed to request IRQ");
252	}
253
254	platform_set_drvdata(pdev, gs);
255
256	ret = devm_gpiochip_add_data(dev, gc, gs);
257	if (ret)
258		dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n");
259
260	return 0;
261}
262
263static void mlxbf3_gpio_shutdown(struct platform_device *pdev)
264{
265	struct mlxbf3_gpio_context *gs = platform_get_drvdata(pdev);
266
267	/* Disable and clear all interrupts */
268	writel(0, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
269	writel(MLXBF_GPIO_CLR_ALL_INTS, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
270}
271
272static const struct acpi_device_id mlxbf3_gpio_acpi_match[] = {
273	{ "MLNXBF33", 0 },
274	{}
275};
276MODULE_DEVICE_TABLE(acpi, mlxbf3_gpio_acpi_match);
277
278static struct platform_driver mlxbf3_gpio_driver = {
279	.driver = {
280		.name = "mlxbf3_gpio",
281		.acpi_match_table = mlxbf3_gpio_acpi_match,
282	},
283	.probe    = mlxbf3_gpio_probe,
284	.shutdown = mlxbf3_gpio_shutdown,
285};
286module_platform_driver(mlxbf3_gpio_driver);
287
288MODULE_SOFTDEP("pre: pinctrl-mlxbf3");
289MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver");
290MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
291MODULE_LICENSE("Dual BSD/GPL");