gpio-mlxbf2.c

  1// SPDX-License-Identifier: GPL-2.0
  2
  3/*
  4 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
  5 */
  6
  7#include <linux/bitfield.h>
  8#include <linux/bitops.h>
  9#include <linux/cleanup.h>
 10#include <linux/device.h>
 11#include <linux/gpio/driver.h>
 12#include <linux/gpio/generic.h>
 13#include <linux/interrupt.h>
 14#include <linux/io.h>
 15#include <linux/ioport.h>
 16#include <linux/kernel.h>
 17#include <linux/mod_devicetable.h>
 18#include <linux/module.h>
 19#include <linux/platform_device.h>
 20#include <linux/pm.h>
 21#include <linux/resource.h>
 22#include <linux/seq_file.h>
 23#include <linux/spinlock.h>
 24#include <linux/types.h>
 25
 26/*
 27 * There are 3 YU GPIO blocks:
 28 * gpio[0]: HOST_GPIO0->HOST_GPIO31
 29 * gpio[1]: HOST_GPIO32->HOST_GPIO63
 30 * gpio[2]: HOST_GPIO64->HOST_GPIO69
 31 */
 32#define MLXBF2_GPIO_MAX_PINS_PER_BLOCK 32
 33
 34/*
 35 * arm_gpio_lock register:
 36 * bit[31]	lock status: active if set
 37 * bit[15:0]	set lock
 38 * The lock is enabled only if 0xd42f is written to this field
 39 */
 40#define YU_ARM_GPIO_LOCK_ADDR		0x2801088
 41#define YU_ARM_GPIO_LOCK_SIZE		0x8
 42#define YU_LOCK_ACTIVE_BIT(val)		(val >> 31)
 43#define YU_ARM_GPIO_LOCK_ACQUIRE	0xd42f
 44#define YU_ARM_GPIO_LOCK_RELEASE	0x0
 45
 46/*
 47 * gpio[x] block registers and their offset
 48 */
 49#define YU_GPIO_DATAIN			0x04
 50#define YU_GPIO_MODE1			0x08
 51#define YU_GPIO_MODE0			0x0c
 52#define YU_GPIO_DATASET			0x14
 53#define YU_GPIO_DATACLEAR		0x18
 54#define YU_GPIO_CAUSE_RISE_EN		0x44
 55#define YU_GPIO_CAUSE_FALL_EN		0x48
 56#define YU_GPIO_MODE1_CLEAR		0x50
 57#define YU_GPIO_MODE0_SET		0x54
 58#define YU_GPIO_MODE0_CLEAR		0x58
 59#define YU_GPIO_CAUSE_OR_CAUSE_EVTEN0	0x80
 60#define YU_GPIO_CAUSE_OR_EVTEN0		0x94
 61#define YU_GPIO_CAUSE_OR_CLRCAUSE	0x98
 62
 63struct mlxbf2_gpio_context_save_regs {
 64	u32 gpio_mode0;
 65	u32 gpio_mode1;
 66};
 67
 68/* BlueField-2 gpio block context structure. */
 69struct mlxbf2_gpio_context {
 70	struct gpio_generic_chip chip;
 71
 72	/* YU GPIO blocks address */
 73	void __iomem *gpio_io;
 74	struct device *dev;
 75
 76	struct mlxbf2_gpio_context_save_regs *csave_regs;
 77};
 78
 79/* BlueField-2 gpio shared structure. */
 80struct mlxbf2_gpio_param {
 81	void __iomem *io;
 82	struct resource *res;
 83	struct mutex *lock;
 84};
 85
 86static struct resource yu_arm_gpio_lock_res =
 87	DEFINE_RES_MEM_NAMED(YU_ARM_GPIO_LOCK_ADDR, YU_ARM_GPIO_LOCK_SIZE, "YU_ARM_GPIO_LOCK");
 88
 89static DEFINE_MUTEX(yu_arm_gpio_lock_mutex);
 90
 91static struct mlxbf2_gpio_param yu_arm_gpio_lock_param = {
 92	.res = &yu_arm_gpio_lock_res,
 93	.lock = &yu_arm_gpio_lock_mutex,
 94};
 95
 96/* Request memory region and map yu_arm_gpio_lock resource */
 97static int mlxbf2_gpio_get_lock_res(struct platform_device *pdev)
 98{
 99	struct device *dev = &pdev->dev;
100	struct resource *res;
101	resource_size_t size;
102	int ret = 0;
103
104	mutex_lock(yu_arm_gpio_lock_param.lock);
105
106	/* Check if the memory map already exists */
107	if (yu_arm_gpio_lock_param.io)
108		goto exit;
109
110	res = yu_arm_gpio_lock_param.res;
111	size = resource_size(res);
112
113	if (!devm_request_mem_region(dev, res->start, size, res->name)) {
114		ret = -EFAULT;
115		goto exit;
116	}
117
118	yu_arm_gpio_lock_param.io = devm_ioremap(dev, res->start, size);
119	if (!yu_arm_gpio_lock_param.io)
120		ret = -ENOMEM;
121
122exit:
123	mutex_unlock(yu_arm_gpio_lock_param.lock);
124
125	return ret;
126}
127
128/*
129 * Acquire the YU arm_gpio_lock to be able to change the direction
130 * mode. If the lock_active bit is already set, return an error.
131 */
132static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs)
133{
134	u32 arm_gpio_lock_val;
135
136	mutex_lock(yu_arm_gpio_lock_param.lock);
137	gpio_generic_chip_lock(&gs->chip);
138
139	arm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io);
140
141	/*
142	 * When lock active bit[31] is set, ModeX is write enabled
143	 */
144	if (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) {
145		gpio_generic_chip_unlock(&gs->chip);
146		mutex_unlock(yu_arm_gpio_lock_param.lock);
147		return -EINVAL;
148	}
149
150	writel(YU_ARM_GPIO_LOCK_ACQUIRE, yu_arm_gpio_lock_param.io);
151
152	return 0;
153}
154
155/*
156 * Release the YU arm_gpio_lock after changing the direction mode.
157 */
158static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs)
159	__releases(&gs->chip.lock)
160	__releases(yu_arm_gpio_lock_param.lock)
161{
162	writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io);
163	gpio_generic_chip_unlock(&gs->chip);
164	mutex_unlock(yu_arm_gpio_lock_param.lock);
165}
166
167/*
168 * mode0 and mode1 are both locked by the gpio_lock field.
169 *
170 * Together, mode0 and mode1 define the gpio Mode dependeing also
171 * on Reg_DataOut.
172 *
173 * {mode1,mode0}:{Reg_DataOut=0,Reg_DataOut=1}->{DataOut=0,DataOut=1}
174 *
175 * {0,0}:Reg_DataOut{0,1}->{Z,Z} Input PAD
176 * {0,1}:Reg_DataOut{0,1}->{0,1} Full drive Output PAD
177 * {1,0}:Reg_DataOut{0,1}->{0,Z} 0-set PAD to low, 1-float
178 * {1,1}:Reg_DataOut{0,1}->{Z,1} 0-float, 1-set PAD to high
179 */
180
181/*
182 * Set input direction:
183 * {mode1,mode0} = {0,0}
184 */
185static int mlxbf2_gpio_direction_input(struct gpio_chip *chip,
186				       unsigned int offset)
187{
188	struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
189	int ret;
190
191	/*
192	 * Although the arm_gpio_lock was set in the probe function, check again
193	 * if it is still enabled to be able to write to the ModeX registers.
194	 */
195	ret = mlxbf2_gpio_lock_acquire(gs);
196	if (ret < 0)
197		return ret;
198
199	writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_CLEAR);
200	writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
201
202	mlxbf2_gpio_lock_release(gs);
203
204	return ret;
205}
206
207/*
208 * Set output direction:
209 * {mode1,mode0} = {0,1}
210 */
211static int mlxbf2_gpio_direction_output(struct gpio_chip *chip,
212					unsigned int offset,
213					int value)
214{
215	struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
216	int ret = 0;
217
218	/*
219	 * Although the arm_gpio_lock was set in the probe function,
220	 * check again it is still enabled to be able to write to the
221	 * ModeX registers.
222	 */
223	ret = mlxbf2_gpio_lock_acquire(gs);
224	if (ret < 0)
225		return ret;
226
227	writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
228	writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_SET);
229
230	mlxbf2_gpio_lock_release(gs);
231
232	return ret;
233}
234
235static void mlxbf2_gpio_irq_enable(struct irq_data *irqd)
236{
237	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
238	struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
239	int offset = irqd_to_hwirq(irqd);
240	u32 val;
241
242	gpiochip_enable_irq(gc, irqd_to_hwirq(irqd));
243	guard(gpio_generic_lock_irqsave)(&gs->chip);
244	val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
245	val |= BIT(offset);
246	writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
247
248	val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
249	val |= BIT(offset);
250	writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
251}
252
253static void mlxbf2_gpio_irq_disable(struct irq_data *irqd)
254{
255	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
256	struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
257	int offset = irqd_to_hwirq(irqd);
258	u32 val;
259
260	scoped_guard(gpio_generic_lock_irqsave, &gs->chip) {
261		val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
262		val &= ~BIT(offset);
263		writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
264	}
265
266	gpiochip_disable_irq(gc, irqd_to_hwirq(irqd));
267}
268
269static irqreturn_t mlxbf2_gpio_irq_handler(int irq, void *ptr)
270{
271	struct mlxbf2_gpio_context *gs = ptr;
272	struct gpio_chip *gc = &gs->chip.gc;
273	unsigned long pending;
274	u32 level;
275
276	pending = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CAUSE_EVTEN0);
277	writel(pending, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
278
279	for_each_set_bit(level, &pending, gc->ngpio)
280		generic_handle_domain_irq_safe(gc->irq.domain, level);
281
282	return IRQ_RETVAL(pending);
283}
284
285static int
286mlxbf2_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
287{
288	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
289	struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
290	int offset = irqd_to_hwirq(irqd);
291	bool fall = false;
292	bool rise = false;
293	u32 val;
294
295	switch (type & IRQ_TYPE_SENSE_MASK) {
296	case IRQ_TYPE_EDGE_BOTH:
297		fall = true;
298		rise = true;
299		break;
300	case IRQ_TYPE_EDGE_RISING:
301		rise = true;
302		break;
303	case IRQ_TYPE_EDGE_FALLING:
304		fall = true;
305		break;
306	default:
307		return -EINVAL;
308	}
309
310	guard(gpio_generic_lock_irqsave)(&gs->chip);
311
312	if (fall) {
313		val = readl(gs->gpio_io + YU_GPIO_CAUSE_FALL_EN);
314		val |= BIT(offset);
315		writel(val, gs->gpio_io + YU_GPIO_CAUSE_FALL_EN);
316	}
317
318	if (rise) {
319		val = readl(gs->gpio_io + YU_GPIO_CAUSE_RISE_EN);
320		val |= BIT(offset);
321		writel(val, gs->gpio_io + YU_GPIO_CAUSE_RISE_EN);
322	}
323
324	return 0;
325}
326
327static void mlxbf2_gpio_irq_print_chip(struct irq_data *irqd,
328				       struct seq_file *p)
329{
330	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
331	struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
332
333	seq_puts(p, dev_name(gs->dev));
334}
335
336static const struct irq_chip mlxbf2_gpio_irq_chip = {
337	.irq_set_type = mlxbf2_gpio_irq_set_type,
338	.irq_enable = mlxbf2_gpio_irq_enable,
339	.irq_disable = mlxbf2_gpio_irq_disable,
340	.irq_print_chip = mlxbf2_gpio_irq_print_chip,
341	.flags = IRQCHIP_IMMUTABLE,
342	GPIOCHIP_IRQ_RESOURCE_HELPERS,
343};
344
345/* BlueField-2 GPIO driver initialization routine. */
346static int
347mlxbf2_gpio_probe(struct platform_device *pdev)
348{
349	struct gpio_generic_chip_config config;
350	struct mlxbf2_gpio_context *gs;
351	struct device *dev = &pdev->dev;
352	struct gpio_irq_chip *girq;
353	struct gpio_chip *gc;
354	unsigned int npins;
355	const char *name;
356	int ret, irq;
357
358	name = dev_name(dev);
359
360	gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL);
361	if (!gs)
362		return -ENOMEM;
363
364	gs->dev = dev;
365
366	/* YU GPIO block address */
367	gs->gpio_io = devm_platform_ioremap_resource(pdev, 0);
368	if (IS_ERR(gs->gpio_io))
369		return PTR_ERR(gs->gpio_io);
370
371	ret = mlxbf2_gpio_get_lock_res(pdev);
372	if (ret)
373		return dev_err_probe(dev, ret, "Failed to get yu_arm_gpio_lock resource\n");
374
375	if (device_property_read_u32(dev, "npins", &npins))
376		npins = MLXBF2_GPIO_MAX_PINS_PER_BLOCK;
377
378	gc = &gs->chip.gc;
379
380	config = (struct gpio_generic_chip_config) {
381		.dev = dev,
382		.sz = 4,
383		.dat = gs->gpio_io + YU_GPIO_DATAIN,
384		.set = gs->gpio_io + YU_GPIO_DATASET,
385		.clr = gs->gpio_io + YU_GPIO_DATACLEAR,
386	};
387
388	ret = gpio_generic_chip_init(&gs->chip, &config);
389	if (ret)
390		return dev_err_probe(dev, ret, "failed to initialize the generic GPIO chip\n");
391
392	gc->direction_input = mlxbf2_gpio_direction_input;
393	gc->direction_output = mlxbf2_gpio_direction_output;
394	gc->ngpio = npins;
395	gc->owner = THIS_MODULE;
396
397	irq = platform_get_irq_optional(pdev, 0);
398	if (irq >= 0) {
399		girq = &gs->chip.gc.irq;
400		gpio_irq_chip_set_chip(girq, &mlxbf2_gpio_irq_chip);
401		girq->handler = handle_simple_irq;
402		girq->default_type = IRQ_TYPE_NONE;
403		/* This will let us handle the parent IRQ in the driver */
404		girq->num_parents = 0;
405		girq->parents = NULL;
406		girq->parent_handler = NULL;
407
408		/*
409		 * Directly request the irq here instead of passing
410		 * a flow-handler because the irq is shared.
411		 */
412		ret = devm_request_irq(dev, irq, mlxbf2_gpio_irq_handler,
413				       IRQF_SHARED, name, gs);
414		if (ret)
415			return dev_err_probe(dev, ret, "failed to request IRQ");
416	}
417
418	platform_set_drvdata(pdev, gs);
419
420	ret = devm_gpiochip_add_data(dev, &gs->chip.gc, gs);
421	if (ret)
422		return dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n");
423
424	return 0;
425}
426
427static int mlxbf2_gpio_suspend(struct device *dev)
428{
429	struct mlxbf2_gpio_context *gs = dev_get_drvdata(dev);
430
431	gs->csave_regs->gpio_mode0 = readl(gs->gpio_io +
432		YU_GPIO_MODE0);
433	gs->csave_regs->gpio_mode1 = readl(gs->gpio_io +
434		YU_GPIO_MODE1);
435
436	return 0;
437}
438
439static int mlxbf2_gpio_resume(struct device *dev)
440{
441	struct mlxbf2_gpio_context *gs = dev_get_drvdata(dev);
442
443	writel(gs->csave_regs->gpio_mode0, gs->gpio_io +
444		YU_GPIO_MODE0);
445	writel(gs->csave_regs->gpio_mode1, gs->gpio_io +
446		YU_GPIO_MODE1);
447
448	return 0;
449}
450static DEFINE_SIMPLE_DEV_PM_OPS(mlxbf2_pm_ops, mlxbf2_gpio_suspend, mlxbf2_gpio_resume);
451
452static const struct acpi_device_id __maybe_unused mlxbf2_gpio_acpi_match[] = {
453	{ "MLNXBF22", 0 },
454	{},
455};
456MODULE_DEVICE_TABLE(acpi, mlxbf2_gpio_acpi_match);
457
458static struct platform_driver mlxbf2_gpio_driver = {
459	.driver = {
460		.name = "mlxbf2_gpio",
461		.acpi_match_table = mlxbf2_gpio_acpi_match,
462		.pm = pm_sleep_ptr(&mlxbf2_pm_ops),
463	},
464	.probe    = mlxbf2_gpio_probe,
465};
466
467module_platform_driver(mlxbf2_gpio_driver);
468
469MODULE_DESCRIPTION("Mellanox BlueField-2 GPIO Driver");
470MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
471MODULE_LICENSE("GPL v2");