gpio-ich.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
  4 *
  5 * Copyright (C) 2010 Extreme Engineering Solutions.
  6 */
  7
  8#include <linux/bitops.h>
  9#include <linux/gpio/driver.h>
 10#include <linux/ioport.h>
 11#include <linux/mfd/lpc_ich.h>
 12#include <linux/module.h>
 13#include <linux/platform_device.h>
 14
 15#define DRV_NAME "gpio_ich"
 16
 17/*
 18 * GPIO register offsets in GPIO I/O space.
 19 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
 20 * LVLx registers.  Logic in the read/write functions takes a register and
 21 * an absolute bit number and determines the proper register offset and bit
 22 * number in that register.  For example, to read the value of GPIO bit 50
 23 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
 24 * bit 18 (50%32).
 25 */
 26enum GPIO_REG {
 27	GPIO_USE_SEL = 0,
 28	GPIO_IO_SEL,
 29	GPIO_LVL,
 30	GPO_BLINK
 31};
 32
 33static const u8 ichx_regs[4][3] = {
 34	{0x00, 0x30, 0x40},	/* USE_SEL[1-3] offsets */
 35	{0x04, 0x34, 0x44},	/* IO_SEL[1-3] offsets */
 36	{0x0c, 0x38, 0x48},	/* LVL[1-3] offsets */
 37	{0x18, 0x18, 0x18},	/* BLINK offset */
 38};
 39
 40static const u8 ichx_reglen[3] = {
 41	0x30, 0x10, 0x10,
 42};
 43
 44static const u8 avoton_regs[4][3] = {
 45	{0x00, 0x80, 0x00},
 46	{0x04, 0x84, 0x00},
 47	{0x08, 0x88, 0x00},
 48};
 49
 50static const u8 avoton_reglen[3] = {
 51	0x10, 0x10, 0x00,
 52};
 53
 54#define ICHX_WRITE(val, reg, base_res)	outl(val, (reg) + (base_res)->start)
 55#define ICHX_READ(reg, base_res)	inl((reg) + (base_res)->start)
 56
 57struct ichx_desc {
 58	/* Max GPIO pins the chipset can have */
 59	uint ngpio;
 60
 61	/* chipset registers */
 62	const u8 (*regs)[3];
 63	const u8 *reglen;
 64
 65	/* GPO_BLINK is available on this chipset */
 66	bool have_blink;
 67
 68	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
 69	bool uses_gpe0;
 70
 71	/* USE_SEL is bogus on some chipsets, eg 3100 */
 72	u32 use_sel_ignore[3];
 73
 74	/* Some chipsets have quirks, let these use their own request/get */
 75	int (*request)(struct gpio_chip *chip, unsigned int offset);
 76	int (*get)(struct gpio_chip *chip, unsigned int offset);
 77
 78	/*
 79	 * Some chipsets don't let reading output values on GPIO_LVL register
 80	 * this option allows driver caching written output values
 81	 */
 82	bool use_outlvl_cache;
 83};
 84
 85static struct {
 86	spinlock_t lock;
 87	struct device *dev;
 88	struct gpio_chip chip;
 89	struct resource *gpio_base;	/* GPIO IO base */
 90	struct resource *pm_base;	/* Power Management IO base */
 91	struct ichx_desc *desc;	/* Pointer to chipset-specific description */
 92	u32 orig_gpio_ctrl;	/* Orig CTRL value, used to restore on exit */
 93	u8 use_gpio;		/* Which GPIO groups are usable */
 94	int outlvl_cache[3];	/* cached output values */
 95} ichx_priv;
 96
 97static int modparam_gpiobase = -1;	/* dynamic */
 98module_param_named(gpiobase, modparam_gpiobase, int, 0444);
 99MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, which is the default.");
100
101static int ichx_write_bit(int reg, unsigned int nr, int val, int verify)
102{
103	unsigned long flags;
104	u32 data, tmp;
105	int reg_nr = nr / 32;
106	int bit = nr & 0x1f;
107
108	spin_lock_irqsave(&ichx_priv.lock, flags);
109
110	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
111		data = ichx_priv.outlvl_cache[reg_nr];
112	else
113		data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
114				 ichx_priv.gpio_base);
115
116	if (val)
117		data |= BIT(bit);
118	else
119		data &= ~BIT(bit);
120	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
121			 ichx_priv.gpio_base);
122	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
123		ichx_priv.outlvl_cache[reg_nr] = data;
124
125	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
126			ichx_priv.gpio_base);
127
128	spin_unlock_irqrestore(&ichx_priv.lock, flags);
129
130	return (verify && data != tmp) ? -EPERM : 0;
131}
132
133static int ichx_read_bit(int reg, unsigned int nr)
134{
135	unsigned long flags;
136	u32 data;
137	int reg_nr = nr / 32;
138	int bit = nr & 0x1f;
139
140	spin_lock_irqsave(&ichx_priv.lock, flags);
141
142	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
143			 ichx_priv.gpio_base);
144
145	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
146		data = ichx_priv.outlvl_cache[reg_nr] | data;
147
148	spin_unlock_irqrestore(&ichx_priv.lock, flags);
149
150	return !!(data & BIT(bit));
151}
152
153static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned int nr)
154{
155	return !!(ichx_priv.use_gpio & BIT(nr / 32));
156}
157
158static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
159{
160	if (ichx_read_bit(GPIO_IO_SEL, nr))
161		return GPIO_LINE_DIRECTION_IN;
162
163	return GPIO_LINE_DIRECTION_OUT;
164}
165
166static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
167{
168	/*
169	 * Try setting pin as an input and verify it worked since many pins
170	 * are output-only.
171	 */
172	return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1);
173}
174
175static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
176					int val)
177{
178	int ret;
179
180	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
181	if (nr < 32 && ichx_priv.desc->have_blink)
182		ichx_write_bit(GPO_BLINK, nr, 0, 0);
183
184	/* Set GPIO output value. */
185	ret = ichx_write_bit(GPIO_LVL, nr, val, 0);
186	if (ret)
187		return ret;
188
189	/*
190	 * Try setting pin as an output and verify it worked since many pins
191	 * are input-only.
192	 */
193	return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1);
194}
195
196static int ichx_gpio_get(struct gpio_chip *chip, unsigned int nr)
197{
198	return ichx_read_bit(GPIO_LVL, nr);
199}
200
201static int ich6_gpio_get(struct gpio_chip *chip, unsigned int nr)
202{
203	unsigned long flags;
204	u32 data;
205
206	/*
207	 * GPI 0 - 15 need to be read from the power management registers on
208	 * a ICH6/3100 bridge.
209	 */
210	if (nr < 16) {
211		if (!ichx_priv.pm_base)
212			return -ENXIO;
213
214		spin_lock_irqsave(&ichx_priv.lock, flags);
215
216		/* GPI 0 - 15 are latched, write 1 to clear*/
217		ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base);
218		data = ICHX_READ(0, ichx_priv.pm_base);
219
220		spin_unlock_irqrestore(&ichx_priv.lock, flags);
221
222		return !!((data >> 16) & BIT(nr));
223	} else {
224		return ichx_gpio_get(chip, nr);
225	}
226}
227
228static int ichx_gpio_request(struct gpio_chip *chip, unsigned int nr)
229{
230	if (!ichx_gpio_check_available(chip, nr))
231		return -ENXIO;
232
233	/*
234	 * Note we assume the BIOS properly set a bridge's USE value.  Some
235	 * chips (eg Intel 3100) have bogus USE values though, so first see if
236	 * the chipset's USE value can be trusted for this specific bit.
237	 * If it can't be trusted, assume that the pin can be used as a GPIO.
238	 */
239	if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))
240		return 0;
241
242	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
243}
244
245static int ich6_gpio_request(struct gpio_chip *chip, unsigned int nr)
246{
247	/*
248	 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
249	 * bridge as they are controlled by USE register bits 0 and 1.  See
250	 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
251	 * additional info.
252	 */
253	if (nr == 16 || nr == 17)
254		nr -= 16;
255
256	return ichx_gpio_request(chip, nr);
257}
258
259static int ichx_gpio_set(struct gpio_chip *chip, unsigned int nr, int val)
260{
261	return ichx_write_bit(GPIO_LVL, nr, val, 0);
262}
263
264static void ichx_gpiolib_setup(struct gpio_chip *chip)
265{
266	chip->owner = THIS_MODULE;
267	chip->label = DRV_NAME;
268	chip->parent = ichx_priv.dev;
269
270	/* Allow chip-specific overrides of request()/get() */
271	chip->request = ichx_priv.desc->request ?
272		ichx_priv.desc->request : ichx_gpio_request;
273	chip->get = ichx_priv.desc->get ?
274		ichx_priv.desc->get : ichx_gpio_get;
275
276	chip->set = ichx_gpio_set;
277	chip->get_direction = ichx_gpio_get_direction;
278	chip->direction_input = ichx_gpio_direction_input;
279	chip->direction_output = ichx_gpio_direction_output;
280	chip->base = modparam_gpiobase;
281	chip->ngpio = ichx_priv.desc->ngpio;
282	chip->can_sleep = false;
283	chip->dbg_show = NULL;
284}
285
286/* ICH6-based, 631xesb-based */
287static struct ichx_desc ich6_desc = {
288	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
289	.request = ich6_gpio_request,
290	.get = ich6_gpio_get,
291
292	/* GPIO 0-15 are read in the GPE0_STS PM register */
293	.uses_gpe0 = true,
294
295	.ngpio = 50,
296	.have_blink = true,
297	.regs = ichx_regs,
298	.reglen = ichx_reglen,
299};
300
301/* Intel 3100 */
302static struct ichx_desc i3100_desc = {
303	/*
304	 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
305	 * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
306	 * Datasheet for more info.
307	 */
308	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},
309
310	/* The 3100 needs fixups for GPIO 0 - 17 */
311	.request = ich6_gpio_request,
312	.get = ich6_gpio_get,
313
314	/* GPIO 0-15 are read in the GPE0_STS PM register */
315	.uses_gpe0 = true,
316
317	.ngpio = 50,
318	.regs = ichx_regs,
319	.reglen = ichx_reglen,
320};
321
322/* ICH7 and ICH8-based */
323static struct ichx_desc ich7_desc = {
324	.ngpio = 50,
325	.have_blink = true,
326	.regs = ichx_regs,
327	.reglen = ichx_reglen,
328};
329
330/* ICH9-based */
331static struct ichx_desc ich9_desc = {
332	.ngpio = 61,
333	.have_blink = true,
334	.regs = ichx_regs,
335	.reglen = ichx_reglen,
336};
337
338/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
339static struct ichx_desc ich10_cons_desc = {
340	.ngpio = 61,
341	.have_blink = true,
342	.regs = ichx_regs,
343	.reglen = ichx_reglen,
344};
345static struct ichx_desc ich10_corp_desc = {
346	.ngpio = 72,
347	.have_blink = true,
348	.regs = ichx_regs,
349	.reglen = ichx_reglen,
350};
351
352/* Intel 5 series, 6 series, 3400 series, and C200 series */
353static struct ichx_desc intel5_desc = {
354	.ngpio = 76,
355	.regs = ichx_regs,
356	.reglen = ichx_reglen,
357};
358
359/* Avoton */
360static struct ichx_desc avoton_desc = {
361	/* Avoton has only 59 GPIOs, but we assume the first set of register
362	 * (Core) has 32 instead of 31 to keep gpio-ich compliance
363	 */
364	.ngpio = 60,
365	.regs = avoton_regs,
366	.reglen = avoton_reglen,
367	.use_outlvl_cache = true,
368};
369
370static int ichx_gpio_request_regions(struct device *dev,
371	struct resource *res_base, const char *name, u8 use_gpio)
372{
373	int i;
374
375	if (!res_base || !res_base->start || !res_base->end)
376		return -ENODEV;
377
378	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
379		if (!(use_gpio & BIT(i)))
380			continue;
381		if (!devm_request_region(dev,
382				res_base->start + ichx_priv.desc->regs[0][i],
383				ichx_priv.desc->reglen[i], name))
384			return -EBUSY;
385	}
386	return 0;
387}
388
389static int ichx_gpio_probe(struct platform_device *pdev)
390{
391	struct device *dev = &pdev->dev;
392	struct lpc_ich_info *ich_info = dev_get_platdata(dev);
393	struct resource *res_base, *res_pm;
394	int err;
395
396	if (!ich_info)
397		return -ENODEV;
398
399	switch (ich_info->gpio_version) {
400	case ICH_I3100_GPIO:
401		ichx_priv.desc = &i3100_desc;
402		break;
403	case ICH_V5_GPIO:
404		ichx_priv.desc = &intel5_desc;
405		break;
406	case ICH_V6_GPIO:
407		ichx_priv.desc = &ich6_desc;
408		break;
409	case ICH_V7_GPIO:
410		ichx_priv.desc = &ich7_desc;
411		break;
412	case ICH_V9_GPIO:
413		ichx_priv.desc = &ich9_desc;
414		break;
415	case ICH_V10CORP_GPIO:
416		ichx_priv.desc = &ich10_corp_desc;
417		break;
418	case ICH_V10CONS_GPIO:
419		ichx_priv.desc = &ich10_cons_desc;
420		break;
421	case AVOTON_GPIO:
422		ichx_priv.desc = &avoton_desc;
423		break;
424	default:
425		return -ENODEV;
426	}
427
428	ichx_priv.dev = dev;
429	spin_lock_init(&ichx_priv.lock);
430
431	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
432	err = ichx_gpio_request_regions(dev, res_base, pdev->name,
433					ich_info->use_gpio);
434	if (err)
435		return err;
436
437	ichx_priv.gpio_base = res_base;
438	ichx_priv.use_gpio = ich_info->use_gpio;
439
440	/*
441	 * If necessary, determine the I/O address of ACPI/power management
442	 * registers which are needed to read the GPE0 register for GPI pins
443	 * 0 - 15 on some chipsets.
444	 */
445	if (!ichx_priv.desc->uses_gpe0)
446		goto init;
447
448	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
449	if (!res_pm) {
450		dev_warn(dev, "ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
451		goto init;
452	}
453
454	if (!devm_request_region(dev, res_pm->start, resource_size(res_pm),
455				 pdev->name)) {
456		dev_warn(dev, "ACPI BAR is busy, GPI 0 - 15 unavailable\n");
457		goto init;
458	}
459
460	ichx_priv.pm_base = res_pm;
461
462init:
463	ichx_gpiolib_setup(&ichx_priv.chip);
464	err = devm_gpiochip_add_data(dev, &ichx_priv.chip, NULL);
465	if (err) {
466		dev_err(dev, "Failed to register GPIOs\n");
467		return err;
468	}
469
470	dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base,
471		 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1);
472
473	return 0;
474}
475
476static struct platform_driver ichx_gpio_driver = {
477	.driver		= {
478		.name	= DRV_NAME,
479	},
480	.probe		= ichx_gpio_probe,
481};
482
483module_platform_driver(ichx_gpio_driver);
484
485MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
486MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
487MODULE_LICENSE("GPL");
488MODULE_ALIAS("platform:"DRV_NAME);