gpio-hisi.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/* Copyright (c) 2020 HiSilicon Limited. */
  3
  4#include <linux/gpio/driver.h>
  5#include <linux/gpio/generic.h>
  6#include <linux/module.h>
  7#include <linux/mod_devicetable.h>
  8#include <linux/platform_device.h>
  9#include <linux/property.h>
 10
 11#define HISI_GPIO_SWPORT_DR_SET_WX	0x000
 12#define HISI_GPIO_SWPORT_DR_CLR_WX	0x004
 13#define HISI_GPIO_SWPORT_DDR_SET_WX	0x010
 14#define HISI_GPIO_SWPORT_DDR_CLR_WX	0x014
 15#define HISI_GPIO_SWPORT_DDR_ST_WX	0x018
 16#define HISI_GPIO_INTEN_SET_WX		0x020
 17#define HISI_GPIO_INTEN_CLR_WX		0x024
 18#define HISI_GPIO_INTMASK_SET_WX	0x030
 19#define HISI_GPIO_INTMASK_CLR_WX	0x034
 20#define HISI_GPIO_INTTYPE_EDGE_SET_WX	0x040
 21#define HISI_GPIO_INTTYPE_EDGE_CLR_WX	0x044
 22#define HISI_GPIO_INT_POLARITY_SET_WX	0x050
 23#define HISI_GPIO_INT_POLARITY_CLR_WX	0x054
 24#define HISI_GPIO_DEBOUNCE_SET_WX	0x060
 25#define HISI_GPIO_DEBOUNCE_CLR_WX	0x064
 26#define HISI_GPIO_INTSTATUS_WX		0x070
 27#define HISI_GPIO_PORTA_EOI_WX		0x078
 28#define HISI_GPIO_EXT_PORT_WX		0x080
 29#define HISI_GPIO_INTCOMB_MASK_WX	0x0a0
 30#define HISI_GPIO_INT_DEDGE_SET		0x0b0
 31#define HISI_GPIO_INT_DEDGE_CLR		0x0b4
 32#define HISI_GPIO_INT_DEDGE_ST		0x0b8
 33
 34#define HISI_GPIO_LINE_NUM_MAX	32
 35#define HISI_GPIO_DRIVER_NAME	"gpio-hisi"
 36
 37struct hisi_gpio {
 38	struct gpio_generic_chip chip;
 39	struct device		*dev;
 40	void __iomem		*reg_base;
 41	unsigned int		line_num;
 42	int			irq;
 43};
 44
 45static inline u32 hisi_gpio_read_reg(struct gpio_chip *chip,
 46				     unsigned int off)
 47{
 48	struct hisi_gpio *hisi_gpio = container_of(to_gpio_generic_chip(chip),
 49						   struct hisi_gpio, chip);
 50	void __iomem *reg = hisi_gpio->reg_base + off;
 51
 52	return readl(reg);
 53}
 54
 55static inline void hisi_gpio_write_reg(struct gpio_chip *chip,
 56				       unsigned int off, u32 val)
 57{
 58	struct hisi_gpio *hisi_gpio = container_of(to_gpio_generic_chip(chip),
 59						   struct hisi_gpio, chip);
 60	void __iomem *reg = hisi_gpio->reg_base + off;
 61
 62	writel(val, reg);
 63}
 64
 65static void hisi_gpio_set_debounce(struct gpio_chip *chip, unsigned int off,
 66				   u32 debounce)
 67{
 68	if (debounce)
 69		hisi_gpio_write_reg(chip, HISI_GPIO_DEBOUNCE_SET_WX, BIT(off));
 70	else
 71		hisi_gpio_write_reg(chip, HISI_GPIO_DEBOUNCE_CLR_WX, BIT(off));
 72}
 73
 74static int hisi_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
 75				unsigned long config)
 76{
 77	u32 config_para = pinconf_to_config_param(config);
 78	u32 config_arg;
 79
 80	switch (config_para) {
 81	case PIN_CONFIG_INPUT_DEBOUNCE:
 82		config_arg = pinconf_to_config_argument(config);
 83		hisi_gpio_set_debounce(chip, offset, config_arg);
 84		break;
 85	default:
 86		return -ENOTSUPP;
 87	}
 88
 89	return 0;
 90}
 91
 92static void hisi_gpio_set_ack(struct irq_data *d)
 93{
 94	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 95
 96	hisi_gpio_write_reg(chip, HISI_GPIO_PORTA_EOI_WX, BIT(irqd_to_hwirq(d)));
 97}
 98
 99static void hisi_gpio_irq_set_mask(struct irq_data *d)
100{
101	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
102
103	hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_SET_WX, BIT(irqd_to_hwirq(d)));
104	gpiochip_disable_irq(chip, irqd_to_hwirq(d));
105}
106
107static void hisi_gpio_irq_clr_mask(struct irq_data *d)
108{
109	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
110
111	gpiochip_enable_irq(chip, irqd_to_hwirq(d));
112	hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_CLR_WX, BIT(irqd_to_hwirq(d)));
113}
114
115static int hisi_gpio_irq_set_type(struct irq_data *d, u32 type)
116{
117	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
118	unsigned int mask = BIT(irqd_to_hwirq(d));
119
120	switch (type) {
121	case IRQ_TYPE_EDGE_BOTH:
122		hisi_gpio_write_reg(chip, HISI_GPIO_INT_DEDGE_SET, mask);
123		break;
124	case IRQ_TYPE_EDGE_RISING:
125		hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_SET_WX, mask);
126		hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_SET_WX, mask);
127		break;
128	case IRQ_TYPE_EDGE_FALLING:
129		hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_SET_WX, mask);
130		hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_CLR_WX, mask);
131		break;
132	case IRQ_TYPE_LEVEL_HIGH:
133		hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_CLR_WX, mask);
134		hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_SET_WX, mask);
135		break;
136	case IRQ_TYPE_LEVEL_LOW:
137		hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_CLR_WX, mask);
138		hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_CLR_WX, mask);
139		break;
140	default:
141		return -EINVAL;
142	}
143
144	/*
145	 * The dual-edge interrupt and other interrupt's registers do not
146	 * take effect at the same time. The registers of the two-edge
147	 * interrupts have higher priorities, the configuration of
148	 * the dual-edge interrupts must be disabled before the configuration
149	 * of other kind of interrupts.
150	 */
151	if (type != IRQ_TYPE_EDGE_BOTH) {
152		unsigned int both = hisi_gpio_read_reg(chip, HISI_GPIO_INT_DEDGE_ST);
153
154		if (both & mask)
155			hisi_gpio_write_reg(chip, HISI_GPIO_INT_DEDGE_CLR, mask);
156	}
157
158	if (type & IRQ_TYPE_LEVEL_MASK)
159		irq_set_handler_locked(d, handle_level_irq);
160	else if (type & IRQ_TYPE_EDGE_BOTH)
161		irq_set_handler_locked(d, handle_edge_irq);
162
163	return 0;
164}
165
166static void hisi_gpio_irq_enable(struct irq_data *d)
167{
168	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
169
170	hisi_gpio_irq_clr_mask(d);
171	hisi_gpio_write_reg(chip, HISI_GPIO_INTEN_SET_WX, BIT(irqd_to_hwirq(d)));
172}
173
174static void hisi_gpio_irq_disable(struct irq_data *d)
175{
176	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
177
178	hisi_gpio_irq_set_mask(d);
179	hisi_gpio_write_reg(chip, HISI_GPIO_INTEN_CLR_WX, BIT(irqd_to_hwirq(d)));
180}
181
182static void hisi_gpio_irq_handler(struct irq_desc *desc)
183{
184	struct hisi_gpio *hisi_gpio = irq_desc_get_handler_data(desc);
185	unsigned long irq_msk = hisi_gpio_read_reg(&hisi_gpio->chip.gc,
186						   HISI_GPIO_INTSTATUS_WX);
187	struct irq_chip *irq_c = irq_desc_get_chip(desc);
188	int hwirq;
189
190	chained_irq_enter(irq_c, desc);
191	for_each_set_bit(hwirq, &irq_msk, HISI_GPIO_LINE_NUM_MAX)
192		generic_handle_domain_irq(hisi_gpio->chip.gc.irq.domain,
193					  hwirq);
194	chained_irq_exit(irq_c, desc);
195}
196
197static const struct irq_chip hisi_gpio_irq_chip = {
198	.name = "HISI-GPIO",
199	.irq_ack = hisi_gpio_set_ack,
200	.irq_mask = hisi_gpio_irq_set_mask,
201	.irq_unmask = hisi_gpio_irq_clr_mask,
202	.irq_set_type = hisi_gpio_irq_set_type,
203	.irq_enable = hisi_gpio_irq_enable,
204	.irq_disable = hisi_gpio_irq_disable,
205	.flags = IRQCHIP_IMMUTABLE,
206	GPIOCHIP_IRQ_RESOURCE_HELPERS,
207};
208
209static void hisi_gpio_init_irq(struct hisi_gpio *hisi_gpio)
210{
211	struct gpio_chip *chip = &hisi_gpio->chip.gc;
212	struct gpio_irq_chip *girq_chip = &chip->irq;
213
214	gpio_irq_chip_set_chip(girq_chip, &hisi_gpio_irq_chip);
215	girq_chip->default_type = IRQ_TYPE_NONE;
216	girq_chip->num_parents = 1;
217	girq_chip->parents = &hisi_gpio->irq;
218	girq_chip->parent_handler = hisi_gpio_irq_handler;
219	girq_chip->parent_handler_data = hisi_gpio;
220
221	/* Clear Mask of GPIO controller combine IRQ */
222	hisi_gpio_write_reg(chip, HISI_GPIO_INTCOMB_MASK_WX, 1);
223}
224
225static const struct acpi_device_id hisi_gpio_acpi_match[] = {
226	{"HISI0184", 0},
227	{}
228};
229MODULE_DEVICE_TABLE(acpi, hisi_gpio_acpi_match);
230
231static const struct of_device_id hisi_gpio_dts_match[] = {
232	{ .compatible = "hisilicon,ascend910-gpio", },
233	{ }
234};
235MODULE_DEVICE_TABLE(of, hisi_gpio_dts_match);
236
237static void hisi_gpio_get_pdata(struct device *dev,
238				struct hisi_gpio *hisi_gpio)
239{
240	struct platform_device *pdev = to_platform_device(dev);
241	struct fwnode_handle *fwnode;
242	int idx = 0;
243
244	device_for_each_child_node(dev, fwnode)  {
245		/* Cycle for once, no need for an array to save line_num */
246		if (fwnode_property_read_u32(fwnode, "ngpios",
247					     &hisi_gpio->line_num)) {
248			dev_err(dev,
249				"failed to get number of lines for port%d and use default value instead\n",
250				idx);
251			hisi_gpio->line_num = HISI_GPIO_LINE_NUM_MAX;
252		}
253
254		if (WARN_ON(hisi_gpio->line_num > HISI_GPIO_LINE_NUM_MAX))
255			hisi_gpio->line_num = HISI_GPIO_LINE_NUM_MAX;
256
257		hisi_gpio->irq = platform_get_irq(pdev, idx);
258
259		dev_info(dev,
260			 "get hisi_gpio[%d] with %u lines\n", idx,
261			 hisi_gpio->line_num);
262
263		idx++;
264	}
265}
266
267static int hisi_gpio_probe(struct platform_device *pdev)
268{
269	struct gpio_generic_chip_config config;
270	struct device *dev = &pdev->dev;
271	struct hisi_gpio *hisi_gpio;
272	int port_num;
273	int ret;
274
275	/*
276	 * One GPIO controller own one port currently,
277	 * if we get more from ACPI table, return error.
278	 */
279	port_num = device_get_child_node_count(dev);
280	if (WARN_ON(port_num != 1))
281		return -ENODEV;
282
283	hisi_gpio = devm_kzalloc(dev, sizeof(*hisi_gpio), GFP_KERNEL);
284	if (!hisi_gpio)
285		return -ENOMEM;
286
287	hisi_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
288	if (IS_ERR(hisi_gpio->reg_base))
289		return PTR_ERR(hisi_gpio->reg_base);
290
291	hisi_gpio_get_pdata(dev, hisi_gpio);
292
293	hisi_gpio->dev = dev;
294
295	config = (struct gpio_generic_chip_config) {
296		.dev = hisi_gpio->dev,
297		.sz = 4,
298		.dat = hisi_gpio->reg_base + HISI_GPIO_EXT_PORT_WX,
299		.set = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_SET_WX,
300		.clr = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_CLR_WX,
301		.dirout = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_SET_WX,
302		.dirin = hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_CLR_WX,
303		.flags = GPIO_GENERIC_NO_SET_ON_INPUT |
304			 GPIO_GENERIC_UNREADABLE_REG_DIR,
305	};
306
307	ret = gpio_generic_chip_init(&hisi_gpio->chip, &config);
308	if (ret) {
309		dev_err(dev, "failed to init, ret = %d\n", ret);
310		return ret;
311	}
312
313	hisi_gpio->chip.gc.set_config = hisi_gpio_set_config;
314	hisi_gpio->chip.gc.ngpio = hisi_gpio->line_num;
315	hisi_gpio->chip.gc.base = -1;
316
317	if (hisi_gpio->irq > 0)
318		hisi_gpio_init_irq(hisi_gpio);
319
320	ret = devm_gpiochip_add_data(dev, &hisi_gpio->chip.gc, hisi_gpio);
321	if (ret) {
322		dev_err(dev, "failed to register gpiochip, ret = %d\n", ret);
323		return ret;
324	}
325
326	return 0;
327}
328
329static struct platform_driver hisi_gpio_driver = {
330	.driver		= {
331		.name	= HISI_GPIO_DRIVER_NAME,
332		.acpi_match_table = hisi_gpio_acpi_match,
333		.of_match_table = hisi_gpio_dts_match,
334	},
335	.probe		= hisi_gpio_probe,
336};
337
338module_platform_driver(hisi_gpio_driver);
339
340MODULE_LICENSE("GPL");
341MODULE_AUTHOR("Luo Jiaxing <luojiaxing@huawei.com>");
342MODULE_DESCRIPTION("HiSilicon GPIO controller driver");
343MODULE_ALIAS("platform:" HISI_GPIO_DRIVER_NAME);