gpio-ftgpio010.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Faraday Technolog FTGPIO010 gpiochip and interrupt routines
  4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
  5 *
  6 * Based on arch/arm/mach-gemini/gpio.c:
  7 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
  8 *
  9 * Based on plat-mxc/gpio.c:
 10 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
 11 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 12 */
 13
 14#include <linux/bitops.h>
 15#include <linux/clk.h>
 16#include <linux/gpio/driver.h>
 17#include <linux/gpio/generic.h>
 18#include <linux/interrupt.h>
 19#include <linux/io.h>
 20#include <linux/platform_device.h>
 21
 22/* GPIO registers definition */
 23#define GPIO_DATA_OUT		0x00
 24#define GPIO_DATA_IN		0x04
 25#define GPIO_DIR		0x08
 26#define GPIO_BYPASS_IN		0x0C
 27#define GPIO_DATA_SET		0x10
 28#define GPIO_DATA_CLR		0x14
 29#define GPIO_PULL_EN		0x18
 30#define GPIO_PULL_TYPE		0x1C
 31#define GPIO_INT_EN		0x20
 32#define GPIO_INT_STAT_RAW	0x24
 33#define GPIO_INT_STAT_MASKED	0x28
 34#define GPIO_INT_MASK		0x2C
 35#define GPIO_INT_CLR		0x30
 36#define GPIO_INT_TYPE		0x34
 37#define GPIO_INT_BOTH_EDGE	0x38
 38#define GPIO_INT_LEVEL		0x3C
 39#define GPIO_DEBOUNCE_EN	0x40
 40#define GPIO_DEBOUNCE_PRESCALE	0x44
 41
 42/**
 43 * struct ftgpio_gpio - Gemini GPIO state container
 44 * @dev: containing device for this instance
 45 * @chip: generic GPIO chip for this instance
 46 * @base: remapped I/O-memory base
 47 * @clk: silicon clock
 48 */
 49struct ftgpio_gpio {
 50	struct device *dev;
 51	struct gpio_generic_chip chip;
 52	void __iomem *base;
 53	struct clk *clk;
 54};
 55
 56static void ftgpio_gpio_ack_irq(struct irq_data *d)
 57{
 58	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 59	struct ftgpio_gpio *g = gpiochip_get_data(gc);
 60
 61	writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR);
 62}
 63
 64static void ftgpio_gpio_mask_irq(struct irq_data *d)
 65{
 66	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 67	struct ftgpio_gpio *g = gpiochip_get_data(gc);
 68	u32 val;
 69
 70	val = readl(g->base + GPIO_INT_EN);
 71	val &= ~BIT(irqd_to_hwirq(d));
 72	writel(val, g->base + GPIO_INT_EN);
 73	gpiochip_disable_irq(gc, irqd_to_hwirq(d));
 74}
 75
 76static void ftgpio_gpio_unmask_irq(struct irq_data *d)
 77{
 78	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 79	struct ftgpio_gpio *g = gpiochip_get_data(gc);
 80	u32 val;
 81
 82	gpiochip_enable_irq(gc, irqd_to_hwirq(d));
 83	val = readl(g->base + GPIO_INT_EN);
 84	val |= BIT(irqd_to_hwirq(d));
 85	writel(val, g->base + GPIO_INT_EN);
 86}
 87
 88static int ftgpio_gpio_set_irq_type(struct irq_data *d, unsigned int type)
 89{
 90	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 91	struct ftgpio_gpio *g = gpiochip_get_data(gc);
 92	u32 mask = BIT(irqd_to_hwirq(d));
 93	u32 reg_both, reg_level, reg_type;
 94
 95	reg_type = readl(g->base + GPIO_INT_TYPE);
 96	reg_level = readl(g->base + GPIO_INT_LEVEL);
 97	reg_both = readl(g->base + GPIO_INT_BOTH_EDGE);
 98
 99	switch (type) {
100	case IRQ_TYPE_EDGE_BOTH:
101		irq_set_handler_locked(d, handle_edge_irq);
102		reg_type &= ~mask;
103		reg_both |= mask;
104		break;
105	case IRQ_TYPE_EDGE_RISING:
106		irq_set_handler_locked(d, handle_edge_irq);
107		reg_type &= ~mask;
108		reg_both &= ~mask;
109		reg_level &= ~mask;
110		break;
111	case IRQ_TYPE_EDGE_FALLING:
112		irq_set_handler_locked(d, handle_edge_irq);
113		reg_type &= ~mask;
114		reg_both &= ~mask;
115		reg_level |= mask;
116		break;
117	case IRQ_TYPE_LEVEL_HIGH:
118		irq_set_handler_locked(d, handle_level_irq);
119		reg_type |= mask;
120		reg_level &= ~mask;
121		break;
122	case IRQ_TYPE_LEVEL_LOW:
123		irq_set_handler_locked(d, handle_level_irq);
124		reg_type |= mask;
125		reg_level |= mask;
126		break;
127	default:
128		irq_set_handler_locked(d, handle_bad_irq);
129		return -EINVAL;
130	}
131
132	writel(reg_type, g->base + GPIO_INT_TYPE);
133	writel(reg_level, g->base + GPIO_INT_LEVEL);
134	writel(reg_both, g->base + GPIO_INT_BOTH_EDGE);
135
136	ftgpio_gpio_ack_irq(d);
137
138	return 0;
139}
140
141static void ftgpio_gpio_irq_handler(struct irq_desc *desc)
142{
143	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
144	struct ftgpio_gpio *g = gpiochip_get_data(gc);
145	struct irq_chip *irqchip = irq_desc_get_chip(desc);
146	int offset;
147	unsigned long stat;
148
149	chained_irq_enter(irqchip, desc);
150
151	stat = readl(g->base + GPIO_INT_STAT_RAW);
152	if (stat)
153		for_each_set_bit(offset, &stat, gc->ngpio)
154			generic_handle_domain_irq(gc->irq.domain, offset);
155
156	chained_irq_exit(irqchip, desc);
157}
158
159static int ftgpio_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
160				  unsigned long config)
161{
162	enum pin_config_param param = pinconf_to_config_param(config);
163	u32 arg = pinconf_to_config_argument(config);
164	struct ftgpio_gpio *g = gpiochip_get_data(gc);
165	unsigned long pclk_freq;
166	u32 deb_div;
167	u32 val;
168
169	if (param != PIN_CONFIG_INPUT_DEBOUNCE)
170		return -ENOTSUPP;
171
172	/*
173	 * Debounce only works if interrupts are enabled. The manual
174	 * states that if PCLK is 66 MHz, and this is set to 0x7D0, then
175	 * PCLK is divided down to 33 kHz for the debounce timer. 0x7D0 is
176	 * 2000 decimal, so what they mean is simply that the PCLK is
177	 * divided by this value.
178	 *
179	 * As we get a debounce setting in microseconds, we calculate the
180	 * desired period time and see if we can get a suitable debounce
181	 * time.
182	 */
183	pclk_freq = clk_get_rate(g->clk);
184	deb_div = DIV_ROUND_CLOSEST(pclk_freq, arg);
185
186	/* This register is only 24 bits wide */
187	if (deb_div > (1 << 24))
188		return -ENOTSUPP;
189
190	dev_dbg(g->dev, "prescale divisor: %08x, resulting frequency %lu Hz\n",
191		deb_div, (pclk_freq/deb_div));
192
193	val = readl(g->base + GPIO_DEBOUNCE_PRESCALE);
194	if (val == deb_div) {
195		/*
196		 * The debounce timer happens to already be set to the
197		 * desirable value, what a coincidence! We can just enable
198		 * debounce on this GPIO line and return. This happens more
199		 * often than you think, for example when all GPIO keys
200		 * on a system are requesting the same debounce interval.
201		 */
202		val = readl(g->base + GPIO_DEBOUNCE_EN);
203		val |= BIT(offset);
204		writel(val, g->base + GPIO_DEBOUNCE_EN);
205		return 0;
206	}
207
208	val = readl(g->base + GPIO_DEBOUNCE_EN);
209	if (val) {
210		/*
211		 * Oh no! Someone is already using the debounce with
212		 * another setting than what we need. Bummer.
213		 */
214		return -ENOTSUPP;
215	}
216
217	/* First come, first serve */
218	writel(deb_div, g->base + GPIO_DEBOUNCE_PRESCALE);
219	/* Enable debounce */
220	val |= BIT(offset);
221	writel(val, g->base + GPIO_DEBOUNCE_EN);
222
223	return 0;
224}
225
226static const struct irq_chip ftgpio_irq_chip = {
227	.name = "FTGPIO010",
228	.irq_ack = ftgpio_gpio_ack_irq,
229	.irq_mask = ftgpio_gpio_mask_irq,
230	.irq_unmask = ftgpio_gpio_unmask_irq,
231	.irq_set_type = ftgpio_gpio_set_irq_type,
232	.flags = IRQCHIP_IMMUTABLE,
233	 GPIOCHIP_IRQ_RESOURCE_HELPERS,
234};
235
236static int ftgpio_gpio_probe(struct platform_device *pdev)
237{
238	struct gpio_generic_chip_config config;
239	struct device *dev = &pdev->dev;
240	struct ftgpio_gpio *g;
241	struct gpio_irq_chip *girq;
242	int irq;
243	int ret;
244
245	g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
246	if (!g)
247		return -ENOMEM;
248
249	g->dev = dev;
250
251	g->base = devm_platform_ioremap_resource(pdev, 0);
252	if (IS_ERR(g->base))
253		return PTR_ERR(g->base);
254
255	irq = platform_get_irq(pdev, 0);
256	if (irq < 0)
257		return irq;
258
259	g->clk = devm_clk_get_enabled(dev, NULL);
260	if (IS_ERR(g->clk) && PTR_ERR(g->clk) == -EPROBE_DEFER)
261		/*
262		 * Percolate deferrals, for anything else,
263		 * just live without the clocking.
264		 */
265		return PTR_ERR(g->clk);
266
267	config = (struct gpio_generic_chip_config) {
268		.dev = dev,
269		.sz = 4,
270		.dat = g->base + GPIO_DATA_IN,
271		.set = g->base + GPIO_DATA_SET,
272		.clr = g->base + GPIO_DATA_CLR,
273		.dirout = g->base + GPIO_DIR,
274	};
275
276	ret = gpio_generic_chip_init(&g->chip, &config);
277	if (ret)
278		return dev_err_probe(dev, ret, "unable to init generic GPIO\n");
279
280	g->chip.gc.label = dev_name(dev);
281	g->chip.gc.base = -1;
282	g->chip.gc.parent = dev;
283	g->chip.gc.owner = THIS_MODULE;
284	/* ngpio is set by gpio_generic_chip_init() */
285
286	/* We need a silicon clock to do debounce */
287	if (!IS_ERR(g->clk))
288		g->chip.gc.set_config = ftgpio_gpio_set_config;
289
290	girq = &g->chip.gc.irq;
291	gpio_irq_chip_set_chip(girq, &ftgpio_irq_chip);
292	girq->parent_handler = ftgpio_gpio_irq_handler;
293	girq->num_parents = 1;
294	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
295				     GFP_KERNEL);
296	if (!girq->parents)
297		return -ENOMEM;
298
299	girq->default_type = IRQ_TYPE_NONE;
300	girq->handler = handle_bad_irq;
301	girq->parents[0] = irq;
302
303	/* Disable, unmask and clear all interrupts */
304	writel(0x0, g->base + GPIO_INT_EN);
305	writel(0x0, g->base + GPIO_INT_MASK);
306	writel(~0x0, g->base + GPIO_INT_CLR);
307
308	/* Clear any use of debounce */
309	writel(0x0, g->base + GPIO_DEBOUNCE_EN);
310
311	return devm_gpiochip_add_data(dev, &g->chip.gc, g);
312}
313
314static const struct of_device_id ftgpio_gpio_of_match[] = {
315	{
316		.compatible = "cortina,gemini-gpio",
317	},
318	{
319		.compatible = "moxa,moxart-gpio",
320	},
321	{
322		.compatible = "faraday,ftgpio010",
323	},
324	{},
325};
326
327static struct platform_driver ftgpio_gpio_driver = {
328	.driver = {
329		.name		= "ftgpio010-gpio",
330		.of_match_table = ftgpio_gpio_of_match,
331	},
332	.probe = ftgpio_gpio_probe,
333};
334builtin_platform_driver(ftgpio_gpio_driver);