gpio-dwapb.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2011 Jamie Iles
  4 *
  5 * All enquiries to support@picochip.com
  6 */
  7#include <linux/acpi.h>
  8#include <linux/clk.h>
  9#include <linux/err.h>
 10#include <linux/gpio/driver.h>
 11#include <linux/gpio/generic.h>
 12#include <linux/init.h>
 13#include <linux/interrupt.h>
 14#include <linux/io.h>
 15#include <linux/ioport.h>
 16#include <linux/irq.h>
 17#include <linux/mod_devicetable.h>
 18#include <linux/module.h>
 19#include <linux/platform_device.h>
 20#include <linux/property.h>
 21#include <linux/reset.h>
 22#include <linux/slab.h>
 23#include <linux/spinlock.h>
 24
 25#include "gpiolib-acpi.h"
 26
 27#define GPIO_SWPORTA_DR		0x00
 28#define GPIO_SWPORTA_DDR	0x04
 29#define GPIO_SWPORTB_DR		0x0c
 30#define GPIO_SWPORTB_DDR	0x10
 31#define GPIO_SWPORTC_DR		0x18
 32#define GPIO_SWPORTC_DDR	0x1c
 33#define GPIO_SWPORTD_DR		0x24
 34#define GPIO_SWPORTD_DDR	0x28
 35#define GPIO_INTEN		0x30
 36#define GPIO_INTMASK		0x34
 37#define GPIO_INTTYPE_LEVEL	0x38
 38#define GPIO_INT_POLARITY	0x3c
 39#define GPIO_INTSTATUS		0x40
 40#define GPIO_PORTA_DEBOUNCE	0x48
 41#define GPIO_PORTA_EOI		0x4c
 42#define GPIO_EXT_PORTA		0x50
 43#define GPIO_EXT_PORTB		0x54
 44#define GPIO_EXT_PORTC		0x58
 45#define GPIO_EXT_PORTD		0x5c
 46
 47#define DWAPB_DRIVER_NAME	"gpio-dwapb"
 48#define DWAPB_MAX_PORTS		4
 49#define DWAPB_MAX_GPIOS		32
 50
 51#define GPIO_EXT_PORT_STRIDE	0x04 /* register stride 32 bits */
 52#define GPIO_SWPORT_DR_STRIDE	0x0c /* register stride 3*32 bits */
 53#define GPIO_SWPORT_DDR_STRIDE	0x0c /* register stride 3*32 bits */
 54
 55#define GPIO_REG_OFFSET_V1	0
 56#define GPIO_REG_OFFSET_V2	1
 57#define GPIO_REG_OFFSET_MASK	BIT(0)
 58
 59#define GPIO_INTMASK_V2		0x44
 60#define GPIO_INTTYPE_LEVEL_V2	0x34
 61#define GPIO_INT_POLARITY_V2	0x38
 62#define GPIO_INTSTATUS_V2	0x3c
 63#define GPIO_PORTA_EOI_V2	0x40
 64
 65#define DWAPB_NR_CLOCKS		2
 66
 67struct dwapb_gpio;
 68
 69struct dwapb_port_property {
 70	struct fwnode_handle *fwnode;
 71	unsigned int idx;
 72	unsigned int ngpio;
 73	unsigned int gpio_base;
 74	int irq[DWAPB_MAX_GPIOS];
 75};
 76
 77struct dwapb_platform_data {
 78	struct dwapb_port_property *properties;
 79	unsigned int nports;
 80};
 81
 82/* Store GPIO context across system-wide suspend/resume transitions */
 83struct dwapb_context {
 84	u32 data;
 85	u32 dir;
 86	u32 ext;
 87	u32 int_en;
 88	u32 int_mask;
 89	u32 int_type;
 90	u32 int_pol;
 91	u32 int_deb;
 92	u32 wake_en;
 93};
 94
 95struct dwapb_gpio_port_irqchip {
 96	unsigned int		nr_irqs;
 97	unsigned int		irq[DWAPB_MAX_GPIOS];
 98};
 99
100struct dwapb_gpio_port {
101	struct gpio_generic_chip chip;
102	struct dwapb_gpio_port_irqchip *pirq;
103	struct dwapb_gpio	*gpio;
104	struct dwapb_context	*ctx;
105	unsigned int		idx;
106};
107
108static inline struct dwapb_gpio *to_dwapb_gpio(struct gpio_chip *gc)
109{
110	return container_of(to_gpio_generic_chip(gc),
111			    struct dwapb_gpio_port, chip)->gpio;
112}
113
114struct dwapb_gpio {
115	struct	device		*dev;
116	void __iomem		*regs;
117	struct dwapb_gpio_port	*ports;
118	unsigned int		nr_ports;
119	unsigned int		flags;
120	struct reset_control	*rst;
121	struct clk_bulk_data	clks[DWAPB_NR_CLOCKS];
122};
123
124static inline u32 gpio_reg_v2_convert(unsigned int offset)
125{
126	switch (offset) {
127	case GPIO_INTMASK:
128		return GPIO_INTMASK_V2;
129	case GPIO_INTTYPE_LEVEL:
130		return GPIO_INTTYPE_LEVEL_V2;
131	case GPIO_INT_POLARITY:
132		return GPIO_INT_POLARITY_V2;
133	case GPIO_INTSTATUS:
134		return GPIO_INTSTATUS_V2;
135	case GPIO_PORTA_EOI:
136		return GPIO_PORTA_EOI_V2;
137	}
138
139	return offset;
140}
141
142static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
143{
144	if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)
145		return gpio_reg_v2_convert(offset);
146
147	return offset;
148}
149
150static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
151{
152	struct gpio_generic_chip *chip = &gpio->ports[0].chip;
153	void __iomem *reg_base = gpio->regs;
154
155	return gpio_generic_read_reg(chip, reg_base + gpio_reg_convert(gpio, offset));
156}
157
158static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
159			       u32 val)
160{
161	struct gpio_generic_chip *chip = &gpio->ports[0].chip;
162	void __iomem *reg_base = gpio->regs;
163
164	gpio_generic_write_reg(chip, reg_base + gpio_reg_convert(gpio, offset), val);
165}
166
167static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
168{
169	struct dwapb_gpio_port *port;
170	int i;
171
172	for (i = 0; i < gpio->nr_ports; i++) {
173		port = &gpio->ports[i];
174		if (port->idx == offs / DWAPB_MAX_GPIOS)
175			return port;
176	}
177
178	return NULL;
179}
180
181static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
182{
183	struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
184	struct gpio_chip *gc;
185	u32 pol;
186	int val;
187
188	if (!port)
189		return;
190	gc = &port->chip.gc;
191
192	pol = dwapb_read(gpio, GPIO_INT_POLARITY);
193	/* Just read the current value right out of the data register */
194	val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
195	if (val)
196		pol &= ~BIT(offs);
197	else
198		pol |= BIT(offs);
199
200	dwapb_write(gpio, GPIO_INT_POLARITY, pol);
201}
202
203static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
204{
205	struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip;
206	unsigned long irq_status;
207	irq_hw_number_t hwirq;
208
209	irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
210	for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
211		int gpio_irq = irq_find_mapping(gen_gc->gc.irq.domain, hwirq);
212		u32 irq_type = irq_get_trigger_type(gpio_irq);
213
214		generic_handle_irq(gpio_irq);
215
216		if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
217			dwapb_toggle_trigger(gpio, hwirq);
218	}
219
220	return irq_status;
221}
222
223static void dwapb_irq_handler(struct irq_desc *desc)
224{
225	struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
226	struct irq_chip *chip = irq_desc_get_chip(desc);
227
228	chained_irq_enter(chip, desc);
229	dwapb_do_irq(gpio);
230	chained_irq_exit(chip, desc);
231}
232
233static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
234{
235	return IRQ_RETVAL(dwapb_do_irq(dev_id));
236}
237
238static void dwapb_irq_ack(struct irq_data *d)
239{
240	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
241	struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
242	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
243	u32 val = BIT(irqd_to_hwirq(d));
244
245	guard(gpio_generic_lock_irqsave)(gen_gc);
246
247	dwapb_write(gpio, GPIO_PORTA_EOI, val);
248}
249
250static void dwapb_irq_mask(struct irq_data *d)
251{
252	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
253	struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
254	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
255	irq_hw_number_t hwirq = irqd_to_hwirq(d);
256	u32 val;
257
258	scoped_guard(gpio_generic_lock_irqsave, gen_gc) {
259		val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
260		dwapb_write(gpio, GPIO_INTMASK, val);
261	}
262
263	gpiochip_disable_irq(gc, hwirq);
264}
265
266static void dwapb_irq_unmask(struct irq_data *d)
267{
268	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
269	struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
270	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
271	irq_hw_number_t hwirq = irqd_to_hwirq(d);
272	u32 val;
273
274	gpiochip_enable_irq(gc, hwirq);
275
276	guard(gpio_generic_lock_irqsave)(gen_gc);
277
278	val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
279	dwapb_write(gpio, GPIO_INTMASK, val);
280}
281
282static void dwapb_irq_enable(struct irq_data *d)
283{
284	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
285	struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
286	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
287	irq_hw_number_t hwirq = irqd_to_hwirq(d);
288	u32 val;
289
290	guard(gpio_generic_lock_irqsave)(gen_gc);
291
292	val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq);
293	dwapb_write(gpio, GPIO_INTEN, val);
294	val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
295	dwapb_write(gpio, GPIO_INTMASK, val);
296}
297
298static void dwapb_irq_disable(struct irq_data *d)
299{
300	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
301	struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
302	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
303	irq_hw_number_t hwirq = irqd_to_hwirq(d);
304	u32 val;
305
306	guard(gpio_generic_lock_irqsave)(gen_gc);
307
308	val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
309	dwapb_write(gpio, GPIO_INTMASK, val);
310	val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq);
311	dwapb_write(gpio, GPIO_INTEN, val);
312}
313
314static int dwapb_irq_set_type(struct irq_data *d, u32 type)
315{
316	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
317	struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
318	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
319	irq_hw_number_t bit = irqd_to_hwirq(d);
320	unsigned long level, polarity;
321
322	guard(gpio_generic_lock_irqsave)(gen_gc);
323
324	level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
325	polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
326
327	switch (type) {
328	case IRQ_TYPE_EDGE_BOTH:
329		level |= BIT(bit);
330		dwapb_toggle_trigger(gpio, bit);
331		break;
332	case IRQ_TYPE_EDGE_RISING:
333		level |= BIT(bit);
334		polarity |= BIT(bit);
335		break;
336	case IRQ_TYPE_EDGE_FALLING:
337		level |= BIT(bit);
338		polarity &= ~BIT(bit);
339		break;
340	case IRQ_TYPE_LEVEL_HIGH:
341		level &= ~BIT(bit);
342		polarity |= BIT(bit);
343		break;
344	case IRQ_TYPE_LEVEL_LOW:
345		level &= ~BIT(bit);
346		polarity &= ~BIT(bit);
347		break;
348	}
349
350	if (type & IRQ_TYPE_LEVEL_MASK)
351		irq_set_handler_locked(d, handle_level_irq);
352	else if (type & IRQ_TYPE_EDGE_BOTH)
353		irq_set_handler_locked(d, handle_edge_irq);
354
355	dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
356	if (type != IRQ_TYPE_EDGE_BOTH)
357		dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
358
359	return 0;
360}
361
362static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
363{
364	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
365	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
366	struct dwapb_context *ctx = gpio->ports[0].ctx;
367	irq_hw_number_t bit = irqd_to_hwirq(d);
368
369	if (enable)
370		ctx->wake_en |= BIT(bit);
371	else
372		ctx->wake_en &= ~BIT(bit);
373
374	return 0;
375}
376
377static const struct irq_chip dwapb_irq_chip = {
378	.name		= DWAPB_DRIVER_NAME,
379	.irq_ack	= dwapb_irq_ack,
380	.irq_mask	= dwapb_irq_mask,
381	.irq_unmask	= dwapb_irq_unmask,
382	.irq_set_type	= dwapb_irq_set_type,
383	.irq_enable	= dwapb_irq_enable,
384	.irq_disable	= dwapb_irq_disable,
385	.irq_set_wake	= pm_sleep_ptr(dwapb_irq_set_wake),
386	.flags		= IRQCHIP_IMMUTABLE,
387	GPIOCHIP_IRQ_RESOURCE_HELPERS,
388};
389
390static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
391				   unsigned offset, unsigned debounce)
392{
393	struct dwapb_gpio_port *port = gpiochip_get_data(gc);
394	struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
395	struct dwapb_gpio *gpio = port->gpio;
396	unsigned long val_deb;
397	unsigned long mask = BIT(offset);
398
399	guard(gpio_generic_lock_irqsave)(gen_gc);
400
401	val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
402	if (debounce)
403		val_deb |= mask;
404	else
405		val_deb &= ~mask;
406	dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
407
408	return 0;
409}
410
411static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
412				 unsigned long config)
413{
414	u32 debounce;
415
416	if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {
417		debounce = pinconf_to_config_argument(config);
418		return dwapb_gpio_set_debounce(gc, offset, debounce);
419	}
420
421	return gpiochip_generic_config(gc, offset, config);
422}
423
424static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
425			      struct dwapb_port_property *pp)
426{
427	int i;
428
429	/* Group all available IRQs into an array of parental IRQs. */
430	for (i = 0; i < pp->ngpio; ++i) {
431		if (!pp->irq[i])
432			continue;
433
434		pirq->irq[pirq->nr_irqs++] = pp->irq[i];
435	}
436
437	return pirq->nr_irqs ? 0 : -ENOENT;
438}
439
440static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
441				 struct dwapb_gpio_port *port,
442				 struct dwapb_port_property *pp)
443{
444	struct dwapb_gpio_port_irqchip *pirq;
445	struct gpio_chip *gc = &port->chip.gc;
446	struct gpio_irq_chip *girq;
447	int err;
448
449	pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
450	if (!pirq)
451		return;
452
453	if (dwapb_convert_irqs(pirq, pp)) {
454		dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
455		goto err_kfree_pirq;
456	}
457
458	girq = &gc->irq;
459	girq->handler = handle_bad_irq;
460	girq->default_type = IRQ_TYPE_NONE;
461
462	port->pirq = pirq;
463
464	/*
465	 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO
466	 * IRQ lane shared between several devices. In that case the parental
467	 * IRQ has to be handled in the shared way so to be properly delivered
468	 * to all the connected devices.
469	 */
470	if (has_acpi_companion(gpio->dev)) {
471		girq->num_parents = 0;
472		girq->parents = NULL;
473		girq->parent_handler = NULL;
474
475		err = devm_request_irq(gpio->dev, pp->irq[0],
476				       dwapb_irq_handler_mfd,
477				       IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
478		if (err) {
479			dev_err(gpio->dev, "error requesting IRQ\n");
480			goto err_kfree_pirq;
481		}
482	} else {
483		girq->num_parents = pirq->nr_irqs;
484		girq->parents = pirq->irq;
485		girq->parent_handler_data = gpio;
486		girq->parent_handler = dwapb_irq_handler;
487	}
488
489	gpio_irq_chip_set_chip(girq, &dwapb_irq_chip);
490
491	return;
492
493err_kfree_pirq:
494	devm_kfree(gpio->dev, pirq);
495}
496
497static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
498			       struct dwapb_port_property *pp,
499			       unsigned int offs)
500{
501	struct gpio_generic_chip_config config;
502	struct dwapb_gpio_port *port;
503	void __iomem *dat, *set, *dirout;
504	int err;
505
506	port = &gpio->ports[offs];
507	port->gpio = gpio;
508	port->idx = pp->idx;
509
510#ifdef CONFIG_PM_SLEEP
511	port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
512	if (!port->ctx)
513		return -ENOMEM;
514#endif
515
516	dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
517	set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
518	dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
519
520	config = (struct gpio_generic_chip_config) {
521		.dev = gpio->dev,
522		.sz = 4,
523		.dat = dat,
524		.set = set,
525		.dirout = dirout,
526	};
527
528	/* This registers 32 GPIO lines per port */
529	err = gpio_generic_chip_init(&port->chip, &config);
530	if (err) {
531		dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
532			port->idx);
533		return err;
534	}
535
536	port->chip.gc.fwnode = pp->fwnode;
537	port->chip.gc.ngpio = pp->ngpio;
538	port->chip.gc.base = pp->gpio_base;
539	port->chip.gc.request = gpiochip_generic_request;
540	port->chip.gc.free = gpiochip_generic_free;
541
542	/* Only port A support debounce */
543	if (pp->idx == 0)
544		port->chip.gc.set_config = dwapb_gpio_set_config;
545	else
546		port->chip.gc.set_config = gpiochip_generic_config;
547
548	/* Only port A can provide interrupts in all configurations of the IP */
549	if (pp->idx == 0)
550		dwapb_configure_irqs(gpio, port, pp);
551
552	err = devm_gpiochip_add_data(gpio->dev, &port->chip.gc, port);
553	if (err) {
554		dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
555			port->idx);
556		return err;
557	}
558
559	return 0;
560}
561
562static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
563			  struct dwapb_port_property *pp)
564{
565	int irq, j;
566
567	for (j = 0; j < pp->ngpio; j++) {
568		if (has_acpi_companion(dev))
569			irq = platform_get_irq_optional(to_platform_device(dev), j);
570		else
571			irq = fwnode_irq_get(fwnode, j);
572		if (irq > 0)
573			pp->irq[j] = irq;
574	}
575}
576
577static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
578{
579	struct dwapb_platform_data *pdata;
580	struct dwapb_port_property *pp;
581	int nports;
582	int i;
583
584	nports = device_get_child_node_count(dev);
585	if (nports == 0)
586		return ERR_PTR(-ENODEV);
587
588	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
589	if (!pdata)
590		return ERR_PTR(-ENOMEM);
591
592	pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
593	if (!pdata->properties)
594		return ERR_PTR(-ENOMEM);
595
596	pdata->nports = nports;
597
598	i = 0;
599	device_for_each_child_node_scoped(dev, fwnode)  {
600		pp = &pdata->properties[i++];
601		pp->fwnode = fwnode;
602
603		if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
604		    pp->idx >= DWAPB_MAX_PORTS) {
605			dev_err(dev,
606				"missing/invalid port index for port%d\n", i);
607			return ERR_PTR(-EINVAL);
608		}
609
610		if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
611		    fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
612			dev_info(dev,
613				 "failed to get number of gpios for port%d\n",
614				 i);
615			pp->ngpio = DWAPB_MAX_GPIOS;
616		}
617
618		pp->gpio_base	= -1;
619
620		/* For internal use only, new platforms mustn't exercise this */
621		if (is_software_node(fwnode))
622			fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);
623
624		/*
625		 * Only port A can provide interrupts in all configurations of
626		 * the IP.
627		 */
628		if (pp->idx == 0)
629			dwapb_get_irq(dev, fwnode, pp);
630	}
631
632	return pdata;
633}
634
635static void dwapb_assert_reset(void *data)
636{
637	struct dwapb_gpio *gpio = data;
638
639	reset_control_assert(gpio->rst);
640}
641
642static int dwapb_get_reset(struct dwapb_gpio *gpio)
643{
644	int err;
645
646	gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
647	if (IS_ERR(gpio->rst))
648		return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
649				     "Cannot get reset descriptor\n");
650
651	err = reset_control_deassert(gpio->rst);
652	if (err) {
653		dev_err(gpio->dev, "Cannot deassert reset lane\n");
654		return err;
655	}
656
657	return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
658}
659
660static void dwapb_disable_clks(void *data)
661{
662	struct dwapb_gpio *gpio = data;
663
664	clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
665}
666
667static int dwapb_get_clks(struct dwapb_gpio *gpio)
668{
669	int err;
670
671	/* Optional bus and debounce clocks */
672	gpio->clks[0].id = "bus";
673	gpio->clks[1].id = "db";
674	err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
675					 gpio->clks);
676	if (err)
677		return dev_err_probe(gpio->dev, err,
678				     "Cannot get APB/Debounce clocks\n");
679
680	err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
681	if (err) {
682		dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
683		return err;
684	}
685
686	return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
687}
688
689static const struct of_device_id dwapb_of_match[] = {
690	{ .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
691	{ .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
692	{ /* Sentinel */ }
693};
694MODULE_DEVICE_TABLE(of, dwapb_of_match);
695
696static const struct acpi_device_id dwapb_acpi_match[] = {
697	{"HISI0181", GPIO_REG_OFFSET_V1},
698	{"APMC0D07", GPIO_REG_OFFSET_V1},
699	{"APMC0D81", GPIO_REG_OFFSET_V2},
700	{"FUJI200A", GPIO_REG_OFFSET_V1},
701	{ }
702};
703MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
704
705static int dwapb_gpio_probe(struct platform_device *pdev)
706{
707	unsigned int i;
708	struct dwapb_gpio *gpio;
709	int err;
710	struct dwapb_platform_data *pdata;
711	struct device *dev = &pdev->dev;
712
713	pdata = dwapb_gpio_get_pdata(dev);
714	if (IS_ERR(pdata))
715		return PTR_ERR(pdata);
716
717	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
718	if (!gpio)
719		return -ENOMEM;
720
721	gpio->dev = &pdev->dev;
722	gpio->nr_ports = pdata->nports;
723
724	err = dwapb_get_reset(gpio);
725	if (err)
726		return err;
727
728	gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
729				   sizeof(*gpio->ports), GFP_KERNEL);
730	if (!gpio->ports)
731		return -ENOMEM;
732
733	gpio->regs = devm_platform_ioremap_resource(pdev, 0);
734	if (IS_ERR(gpio->regs))
735		return PTR_ERR(gpio->regs);
736
737	err = dwapb_get_clks(gpio);
738	if (err)
739		return err;
740
741	gpio->flags = (uintptr_t)device_get_match_data(dev);
742
743	for (i = 0; i < gpio->nr_ports; i++) {
744		err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
745		if (err)
746			return err;
747	}
748
749	platform_set_drvdata(pdev, gpio);
750
751	return 0;
752}
753
754static int dwapb_gpio_suspend(struct device *dev)
755{
756	struct dwapb_gpio *gpio = dev_get_drvdata(dev);
757	struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip;
758	int i;
759
760	scoped_guard(gpio_generic_lock_irqsave, gen_gc) {
761		for (i = 0; i < gpio->nr_ports; i++) {
762			unsigned int offset;
763			unsigned int idx = gpio->ports[i].idx;
764			struct dwapb_context *ctx = gpio->ports[i].ctx;
765
766			offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
767			ctx->dir = dwapb_read(gpio, offset);
768
769			offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
770			ctx->data = dwapb_read(gpio, offset);
771
772			offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
773			ctx->ext = dwapb_read(gpio, offset);
774
775			/* Only port A can provide interrupts */
776			if (idx == 0) {
777				ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
778				ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
779				ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
780				ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
781				ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
782
783				/* Mask out interrupts */
784				dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
785			}
786		}
787	}
788
789	clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
790
791	return 0;
792}
793
794static int dwapb_gpio_resume(struct device *dev)
795{
796	struct dwapb_gpio *gpio = dev_get_drvdata(dev);
797	struct gpio_chip *gc = &gpio->ports[0].chip.gc;
798	struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
799	int i, err;
800
801	err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
802	if (err) {
803		dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
804		return err;
805	}
806
807	guard(gpio_generic_lock_irqsave)(gen_gc);
808
809	for (i = 0; i < gpio->nr_ports; i++) {
810		unsigned int offset;
811		unsigned int idx = gpio->ports[i].idx;
812		struct dwapb_context *ctx = gpio->ports[i].ctx;
813
814		offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
815		dwapb_write(gpio, offset, ctx->data);
816
817		offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
818		dwapb_write(gpio, offset, ctx->dir);
819
820		offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
821		dwapb_write(gpio, offset, ctx->ext);
822
823		/* Only port A can provide interrupts */
824		if (idx == 0) {
825			dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
826			dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
827			dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
828			dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
829			dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
830
831			/* Clear out spurious interrupts */
832			dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
833		}
834	}
835
836	return 0;
837}
838
839static DEFINE_SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops,
840				dwapb_gpio_suspend, dwapb_gpio_resume);
841
842static struct platform_driver dwapb_gpio_driver = {
843	.driver		= {
844		.name	= DWAPB_DRIVER_NAME,
845		.pm	= pm_sleep_ptr(&dwapb_gpio_pm_ops),
846		.of_match_table = dwapb_of_match,
847		.acpi_match_table = dwapb_acpi_match,
848	},
849	.probe		= dwapb_gpio_probe,
850};
851
852module_platform_driver(dwapb_gpio_driver);
853
854MODULE_LICENSE("GPL");
855MODULE_AUTHOR("Jamie Iles");
856MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
857MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);