gpio-dln2.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Driver for the Diolan DLN-2 USB-GPIO adapter
  4 *
  5 * Copyright (c) 2014 Intel Corporation
  6 */
  7
  8#include <linux/kernel.h>
  9#include <linux/module.h>
 10#include <linux/slab.h>
 11#include <linux/types.h>
 12#include <linux/irqdomain.h>
 13#include <linux/irq.h>
 14#include <linux/irqchip/chained_irq.h>
 15#include <linux/gpio/driver.h>
 16#include <linux/platform_device.h>
 17#include <linux/mfd/dln2.h>
 18
 19#define DLN2_GPIO_ID			0x01
 20
 21#define DLN2_GPIO_GET_PIN_COUNT		DLN2_CMD(0x01, DLN2_GPIO_ID)
 22#define DLN2_GPIO_SET_DEBOUNCE		DLN2_CMD(0x04, DLN2_GPIO_ID)
 23#define DLN2_GPIO_GET_DEBOUNCE		DLN2_CMD(0x05, DLN2_GPIO_ID)
 24#define DLN2_GPIO_PORT_GET_VAL		DLN2_CMD(0x06, DLN2_GPIO_ID)
 25#define DLN2_GPIO_PIN_GET_VAL		DLN2_CMD(0x0B, DLN2_GPIO_ID)
 26#define DLN2_GPIO_PIN_SET_OUT_VAL	DLN2_CMD(0x0C, DLN2_GPIO_ID)
 27#define DLN2_GPIO_PIN_GET_OUT_VAL	DLN2_CMD(0x0D, DLN2_GPIO_ID)
 28#define DLN2_GPIO_CONDITION_MET_EV	DLN2_CMD(0x0F, DLN2_GPIO_ID)
 29#define DLN2_GPIO_PIN_ENABLE		DLN2_CMD(0x10, DLN2_GPIO_ID)
 30#define DLN2_GPIO_PIN_DISABLE		DLN2_CMD(0x11, DLN2_GPIO_ID)
 31#define DLN2_GPIO_PIN_SET_DIRECTION	DLN2_CMD(0x13, DLN2_GPIO_ID)
 32#define DLN2_GPIO_PIN_GET_DIRECTION	DLN2_CMD(0x14, DLN2_GPIO_ID)
 33#define DLN2_GPIO_PIN_SET_EVENT_CFG	DLN2_CMD(0x1E, DLN2_GPIO_ID)
 34#define DLN2_GPIO_PIN_GET_EVENT_CFG	DLN2_CMD(0x1F, DLN2_GPIO_ID)
 35
 36#define DLN2_GPIO_EVENT_NONE		0
 37#define DLN2_GPIO_EVENT_CHANGE		1
 38#define DLN2_GPIO_EVENT_LVL_HIGH	2
 39#define DLN2_GPIO_EVENT_LVL_LOW		3
 40#define DLN2_GPIO_EVENT_CHANGE_RISING	0x11
 41#define DLN2_GPIO_EVENT_CHANGE_FALLING  0x21
 42#define DLN2_GPIO_EVENT_MASK		0x0F
 43
 44#define DLN2_GPIO_MAX_PINS 32
 45
 46struct dln2_gpio {
 47	struct platform_device *pdev;
 48	struct gpio_chip gpio;
 49
 50	/*
 51	 * Cache pin direction to save us one transfer, since the hardware has
 52	 * separate commands to read the in and out values.
 53	 */
 54	DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);
 55
 56	/* active IRQs - not synced to hardware */
 57	DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS);
 58	/* active IRQS - synced to hardware */
 59	DECLARE_BITMAP(enabled_irqs, DLN2_GPIO_MAX_PINS);
 60	int irq_type[DLN2_GPIO_MAX_PINS];
 61	struct mutex irq_lock;
 62};
 63
 64struct dln2_gpio_pin {
 65	__le16 pin;
 66};
 67
 68struct dln2_gpio_pin_val {
 69	__le16 pin __packed;
 70	u8 value;
 71};
 72
 73static int dln2_gpio_get_pin_count(struct platform_device *pdev)
 74{
 75	int ret;
 76	__le16 count;
 77	int len = sizeof(count);
 78
 79	ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len);
 80	if (ret < 0)
 81		return ret;
 82	if (len < sizeof(count))
 83		return -EPROTO;
 84
 85	return le16_to_cpu(count);
 86}
 87
 88static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin)
 89{
 90	struct dln2_gpio_pin req = {
 91		.pin = cpu_to_le16(pin),
 92	};
 93
 94	return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req));
 95}
 96
 97static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin)
 98{
 99	int ret;
100	struct dln2_gpio_pin req = {
101		.pin = cpu_to_le16(pin),
102	};
103	struct dln2_gpio_pin_val rsp;
104	int len = sizeof(rsp);
105
106	ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len);
107	if (ret < 0)
108		return ret;
109	if (len < sizeof(rsp) || req.pin != rsp.pin)
110		return -EPROTO;
111
112	return rsp.value;
113}
114
115static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin)
116{
117	int ret;
118
119	ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin);
120	if (ret < 0)
121		return ret;
122	return !!ret;
123}
124
125static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
126{
127	int ret;
128
129	ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin);
130	if (ret < 0)
131		return ret;
132	return !!ret;
133}
134
135static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
136				     unsigned int pin, int value)
137{
138	struct dln2_gpio_pin_val req = {
139		.pin = cpu_to_le16(pin),
140		.value = value,
141	};
142
143	return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
144				sizeof(req));
145}
146
147#define DLN2_GPIO_DIRECTION_IN		0
148#define DLN2_GPIO_DIRECTION_OUT		1
149
150static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset)
151{
152	struct dln2_gpio *dln2 = gpiochip_get_data(chip);
153	struct dln2_gpio_pin req = {
154		.pin = cpu_to_le16(offset),
155	};
156	struct dln2_gpio_pin_val rsp;
157	int len = sizeof(rsp);
158	int ret;
159
160	ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset);
161	if (ret < 0)
162		return ret;
163
164	/* cache the pin direction */
165	ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION,
166			    &req, sizeof(req), &rsp, &len);
167	if (ret < 0)
168		return ret;
169	if (len < sizeof(rsp) || req.pin != rsp.pin) {
170		ret = -EPROTO;
171		goto out_disable;
172	}
173
174	switch (rsp.value) {
175	case DLN2_GPIO_DIRECTION_IN:
176		clear_bit(offset, dln2->output_enabled);
177		return 0;
178	case DLN2_GPIO_DIRECTION_OUT:
179		set_bit(offset, dln2->output_enabled);
180		return 0;
181	default:
182		ret = -EPROTO;
183		goto out_disable;
184	}
185
186out_disable:
187	dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
188	return ret;
189}
190
191static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset)
192{
193	struct dln2_gpio *dln2 = gpiochip_get_data(chip);
194
195	dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
196}
197
198static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
199{
200	struct dln2_gpio *dln2 = gpiochip_get_data(chip);
201
202	if (test_bit(offset, dln2->output_enabled))
203		return GPIO_LINE_DIRECTION_OUT;
204
205	return GPIO_LINE_DIRECTION_IN;
206}
207
208static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset)
209{
210	struct dln2_gpio *dln2 = gpiochip_get_data(chip);
211	int dir;
212
213	dir = dln2_gpio_get_direction(chip, offset);
214	if (dir < 0)
215		return dir;
216
217	if (dir == GPIO_LINE_DIRECTION_IN)
218		return dln2_gpio_pin_get_in_val(dln2, offset);
219
220	return dln2_gpio_pin_get_out_val(dln2, offset);
221}
222
223static int dln2_gpio_set(struct gpio_chip *chip, unsigned int offset,
224			 int value)
225{
226	struct dln2_gpio *dln2 = gpiochip_get_data(chip);
227
228	return dln2_gpio_pin_set_out_val(dln2, offset, value);
229}
230
231static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset,
232				   unsigned dir)
233{
234	struct dln2_gpio *dln2 = gpiochip_get_data(chip);
235	struct dln2_gpio_pin_val req = {
236		.pin = cpu_to_le16(offset),
237		.value = dir,
238	};
239	int ret;
240
241	ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION,
242			       &req, sizeof(req));
243	if (ret < 0)
244		return ret;
245
246	if (dir == DLN2_GPIO_DIRECTION_OUT)
247		set_bit(offset, dln2->output_enabled);
248	else
249		clear_bit(offset, dln2->output_enabled);
250
251	return ret;
252}
253
254static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
255{
256	return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN);
257}
258
259static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
260				      int value)
261{
262	struct dln2_gpio *dln2 = gpiochip_get_data(chip);
263	int ret;
264
265	ret = dln2_gpio_pin_set_out_val(dln2, offset, value);
266	if (ret < 0)
267		return ret;
268
269	return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
270}
271
272static int dln2_gpio_set_config(struct gpio_chip *chip, unsigned offset,
273				unsigned long config)
274{
275	struct dln2_gpio *dln2 = gpiochip_get_data(chip);
276	__le32 duration;
277
278	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
279		return -ENOTSUPP;
280
281	duration = cpu_to_le32(pinconf_to_config_argument(config));
282	return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE,
283				&duration, sizeof(duration));
284}
285
286static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
287				   unsigned type, unsigned period)
288{
289	struct {
290		__le16 pin;
291		u8 type;
292		__le16 period;
293	} __packed req = {
294		.pin = cpu_to_le16(pin),
295		.type = type,
296		.period = cpu_to_le16(period),
297	};
298
299	return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG,
300				&req, sizeof(req));
301}
302
303static void dln2_irq_unmask(struct irq_data *irqd)
304{
305	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
306	struct dln2_gpio *dln2 = gpiochip_get_data(gc);
307	int pin = irqd_to_hwirq(irqd);
308
309	gpiochip_enable_irq(gc, pin);
310	set_bit(pin, dln2->unmasked_irqs);
311}
312
313static void dln2_irq_mask(struct irq_data *irqd)
314{
315	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
316	struct dln2_gpio *dln2 = gpiochip_get_data(gc);
317	int pin = irqd_to_hwirq(irqd);
318
319	clear_bit(pin, dln2->unmasked_irqs);
320	gpiochip_disable_irq(gc, pin);
321}
322
323static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
324{
325	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
326	struct dln2_gpio *dln2 = gpiochip_get_data(gc);
327	int pin = irqd_to_hwirq(irqd);
328
329	switch (type) {
330	case IRQ_TYPE_LEVEL_HIGH:
331		dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH;
332		break;
333	case IRQ_TYPE_LEVEL_LOW:
334		dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW;
335		break;
336	case IRQ_TYPE_EDGE_BOTH:
337		dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE;
338		break;
339	case IRQ_TYPE_EDGE_RISING:
340		dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING;
341		break;
342	case IRQ_TYPE_EDGE_FALLING:
343		dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING;
344		break;
345	default:
346		return -EINVAL;
347	}
348
349	return 0;
350}
351
352static void dln2_irq_bus_lock(struct irq_data *irqd)
353{
354	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
355	struct dln2_gpio *dln2 = gpiochip_get_data(gc);
356
357	mutex_lock(&dln2->irq_lock);
358}
359
360static void dln2_irq_bus_unlock(struct irq_data *irqd)
361{
362	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
363	struct dln2_gpio *dln2 = gpiochip_get_data(gc);
364	int pin = irqd_to_hwirq(irqd);
365	int enabled, unmasked;
366	unsigned type;
367	int ret;
368
369	enabled = test_bit(pin, dln2->enabled_irqs);
370	unmasked = test_bit(pin, dln2->unmasked_irqs);
371
372	if (enabled != unmasked) {
373		if (unmasked) {
374			type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK;
375			set_bit(pin, dln2->enabled_irqs);
376		} else {
377			type = DLN2_GPIO_EVENT_NONE;
378			clear_bit(pin, dln2->enabled_irqs);
379		}
380
381		ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0);
382		if (ret)
383			dev_err(dln2->gpio.parent, "failed to set event\n");
384	}
385
386	mutex_unlock(&dln2->irq_lock);
387}
388
389static const struct irq_chip dln2_irqchip = {
390	.name = "dln2-irq",
391	.irq_mask = dln2_irq_mask,
392	.irq_unmask = dln2_irq_unmask,
393	.irq_set_type = dln2_irq_set_type,
394	.irq_bus_lock = dln2_irq_bus_lock,
395	.irq_bus_sync_unlock = dln2_irq_bus_unlock,
396	.flags = IRQCHIP_IMMUTABLE,
397	GPIOCHIP_IRQ_RESOURCE_HELPERS,
398};
399
400static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
401			    const void *data, int len)
402{
403	int pin, ret;
404
405	const struct {
406		__le16 count;
407		__u8 type;
408		__le16 pin;
409		__u8 value;
410	} __packed *event = data;
411	struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
412
413	if (len < sizeof(*event)) {
414		dev_err(dln2->gpio.parent, "short event message\n");
415		return;
416	}
417
418	pin = le16_to_cpu(event->pin);
419	if (pin >= dln2->gpio.ngpio) {
420		dev_err(dln2->gpio.parent, "out of bounds pin %d\n", pin);
421		return;
422	}
423
424	switch (dln2->irq_type[pin]) {
425	case DLN2_GPIO_EVENT_CHANGE_RISING:
426		if (!event->value)
427			return;
428		break;
429	case DLN2_GPIO_EVENT_CHANGE_FALLING:
430		if (event->value)
431			return;
432		break;
433	}
434
435	ret = generic_handle_domain_irq(dln2->gpio.irq.domain, pin);
436	if (unlikely(ret))
437		dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin);
438}
439
440static int dln2_gpio_probe(struct platform_device *pdev)
441{
442	struct dln2_gpio *dln2;
443	struct device *dev = &pdev->dev;
444	struct gpio_irq_chip *girq;
445	int pins;
446	int ret;
447
448	pins = dln2_gpio_get_pin_count(pdev);
449	if (pins < 0) {
450		dev_err(dev, "failed to get pin count: %d\n", pins);
451		return pins;
452	}
453	if (pins > DLN2_GPIO_MAX_PINS) {
454		pins = DLN2_GPIO_MAX_PINS;
455		dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS);
456	}
457
458	dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL);
459	if (!dln2)
460		return -ENOMEM;
461
462	mutex_init(&dln2->irq_lock);
463
464	dln2->pdev = pdev;
465
466	dln2->gpio.label = "dln2";
467	dln2->gpio.parent = dev;
468	dln2->gpio.owner = THIS_MODULE;
469	dln2->gpio.base = -1;
470	dln2->gpio.ngpio = pins;
471	dln2->gpio.can_sleep = true;
472	dln2->gpio.set = dln2_gpio_set;
473	dln2->gpio.get = dln2_gpio_get;
474	dln2->gpio.request = dln2_gpio_request;
475	dln2->gpio.free = dln2_gpio_free;
476	dln2->gpio.get_direction = dln2_gpio_get_direction;
477	dln2->gpio.direction_input = dln2_gpio_direction_input;
478	dln2->gpio.direction_output = dln2_gpio_direction_output;
479	dln2->gpio.set_config = dln2_gpio_set_config;
480
481	girq = &dln2->gpio.irq;
482	gpio_irq_chip_set_chip(girq, &dln2_irqchip);
483	/* The event comes from the outside so no parent handler */
484	girq->parent_handler = NULL;
485	girq->num_parents = 0;
486	girq->parents = NULL;
487	girq->default_type = IRQ_TYPE_NONE;
488	girq->handler = handle_simple_irq;
489
490	platform_set_drvdata(pdev, dln2);
491
492	ret = devm_gpiochip_add_data(dev, &dln2->gpio, dln2);
493	if (ret < 0) {
494		dev_err(dev, "failed to add gpio chip: %d\n", ret);
495		return ret;
496	}
497
498	ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV,
499				     dln2_gpio_event);
500	if (ret) {
501		dev_err(dev, "failed to register event cb: %d\n", ret);
502		return ret;
503	}
504
505	return 0;
506}
507
508static void dln2_gpio_remove(struct platform_device *pdev)
509{
510	dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
511}
512
513static struct platform_driver dln2_gpio_driver = {
514	.driver.name	= "dln2-gpio",
515	.probe		= dln2_gpio_probe,
516	.remove		= dln2_gpio_remove,
517};
518
519module_platform_driver(dln2_gpio_driver);
520
521MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
522MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface");
523MODULE_LICENSE("GPL v2");
524MODULE_ALIAS("platform:dln2-gpio");