gpio-davinci.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * TI DaVinci GPIO Support
  4 *
  5 * Copyright (c) 2006-2007 David Brownell
  6 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
  7 */
  8
  9#include <linux/cleanup.h>
 10#include <linux/gpio/driver.h>
 11#include <linux/errno.h>
 12#include <linux/kernel.h>
 13#include <linux/clk.h>
 14#include <linux/err.h>
 15#include <linux/io.h>
 16#include <linux/irq.h>
 17#include <linux/irqdomain.h>
 18#include <linux/module.h>
 19#include <linux/pinctrl/consumer.h>
 20#include <linux/platform_device.h>
 21#include <linux/property.h>
 22#include <linux/irqchip/chained_irq.h>
 23#include <linux/spinlock.h>
 24#include <linux/pm_runtime.h>
 25
 26#define MAX_REGS_BANKS 5
 27#define MAX_INT_PER_BANK 32
 28
 29struct davinci_gpio_regs {
 30	u32	dir;
 31	u32	out_data;
 32	u32	set_data;
 33	u32	clr_data;
 34	u32	in_data;
 35	u32	set_rising;
 36	u32	clr_rising;
 37	u32	set_falling;
 38	u32	clr_falling;
 39	u32	intstat;
 40};
 41
 42typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
 43
 44#define BINTEN	0x8 /* GPIO Interrupt Per-Bank Enable Register */
 45
 46static void __iomem *gpio_base;
 47static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
 48
 49struct davinci_gpio_irq_data {
 50	void __iomem			*regs;
 51	struct davinci_gpio_controller	*chip;
 52	int				bank_num;
 53};
 54
 55struct davinci_gpio_controller {
 56	struct gpio_chip	chip;
 57	struct irq_domain	*irq_domain;
 58	/* Serialize access to GPIO registers */
 59	spinlock_t		lock;
 60	void __iomem		*regs[MAX_REGS_BANKS];
 61	int			gpio_unbanked;
 62	int			irqs[MAX_INT_PER_BANK];
 63	struct davinci_gpio_regs context[MAX_REGS_BANKS];
 64	u32			binten_context;
 65};
 66
 67static inline u32 __gpio_mask(unsigned gpio)
 68{
 69	return 1 << (gpio % 32);
 70}
 71
 72static int davinci_gpio_irq_setup(struct platform_device *pdev);
 73
 74/*--------------------------------------------------------------------------*/
 75
 76/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
 77static inline int __davinci_direction(struct gpio_chip *chip,
 78			unsigned offset, bool out, int value)
 79{
 80	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
 81	struct davinci_gpio_regs __iomem *g;
 82	unsigned long flags;
 83	u32 temp;
 84	int bank = offset / 32;
 85	u32 mask = __gpio_mask(offset);
 86
 87	g = d->regs[bank];
 88	spin_lock_irqsave(&d->lock, flags);
 89	temp = readl_relaxed(&g->dir);
 90	if (out) {
 91		temp &= ~mask;
 92		writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
 93	} else {
 94		temp |= mask;
 95	}
 96	writel_relaxed(temp, &g->dir);
 97	spin_unlock_irqrestore(&d->lock, flags);
 98
 99	return 0;
100}
101
102static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
103{
104	return __davinci_direction(chip, offset, false, 0);
105}
106
107static int
108davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
109{
110	return __davinci_direction(chip, offset, true, value);
111}
112
113static int davinci_get_direction(struct gpio_chip *chip, unsigned int offset)
114{
115	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
116	struct davinci_gpio_regs __iomem *g;
117	u32 mask = __gpio_mask(offset), val;
118	int bank = offset / 32;
119
120	g = d->regs[bank];
121
122	guard(spinlock_irqsave)(&d->lock);
123
124	val = readl_relaxed(&g->dir);
125
126	return (val & mask) ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
127}
128
129/*
130 * Read the pin's value (works even if it's set up as output);
131 * returns zero/nonzero.
132 *
133 * Note that changes are synched to the GPIO clock, so reading values back
134 * right after you've set them may give old values.
135 */
136static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
137{
138	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
139	struct davinci_gpio_regs __iomem *g;
140	int bank = offset / 32;
141
142	g = d->regs[bank];
143
144	return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
145}
146
147/*
148 * Assuming the pin is muxed as a gpio output, set its output value.
149 */
150static int
151davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
152{
153	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
154	struct davinci_gpio_regs __iomem *g;
155	int bank = offset / 32;
156
157	g = d->regs[bank];
158
159	writel_relaxed(__gpio_mask(offset),
160		       value ? &g->set_data : &g->clr_data);
161
162	return 0;
163}
164
165static int davinci_gpio_probe(struct platform_device *pdev)
166{
167	int bank, i, ret = 0;
168	unsigned int ngpio, nbank, nirq, gpio_unbanked;
169	struct davinci_gpio_controller *chips;
170	struct device *dev = &pdev->dev;
171
172	/*
173	 * The gpio banks conceptually expose a segmented bitmap,
174	 * and "ngpio" is one more than the largest zero-based
175	 * bit index that's valid.
176	 */
177	ret = device_property_read_u32(dev, "ti,ngpio", &ngpio);
178	if (ret)
179		return dev_err_probe(dev, ret, "Failed to get the number of GPIOs\n");
180	if (ngpio == 0)
181		return dev_err_probe(dev, -EINVAL, "How many GPIOs?\n");
182
183	/*
184	 * If there are unbanked interrupts then the number of
185	 * interrupts is equal to number of gpios else all are banked so
186	 * number of interrupts is equal to number of banks(each with 16 gpios)
187	 */
188	ret = device_property_read_u32(dev, "ti,davinci-gpio-unbanked",
189				       &gpio_unbanked);
190	if (ret)
191		return dev_err_probe(dev, ret, "Failed to get the unbanked GPIOs property\n");
192
193	if (gpio_unbanked)
194		nirq = gpio_unbanked;
195	else
196		nirq = DIV_ROUND_UP(ngpio, 16);
197
198	if (nirq > MAX_INT_PER_BANK) {
199		dev_err(dev, "Too many IRQs!\n");
200		return -EINVAL;
201	}
202
203	chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
204	if (!chips)
205		return -ENOMEM;
206
207	gpio_base = devm_platform_ioremap_resource(pdev, 0);
208	if (IS_ERR(gpio_base))
209		return PTR_ERR(gpio_base);
210
211	for (i = 0; i < nirq; i++) {
212		chips->irqs[i] = platform_get_irq(pdev, i);
213		if (chips->irqs[i] < 0)
214			return chips->irqs[i];
215	}
216
217	chips->chip.label = dev_name(dev);
218
219	chips->chip.direction_input = davinci_direction_in;
220	chips->chip.get = davinci_gpio_get;
221	chips->chip.direction_output = davinci_direction_out;
222	chips->chip.set = davinci_gpio_set;
223	chips->chip.get_direction = davinci_get_direction;
224
225	chips->chip.ngpio = ngpio;
226	chips->chip.base = -1;
227
228#ifdef CONFIG_OF_GPIO
229	chips->chip.parent = dev;
230	chips->chip.request = gpiochip_generic_request;
231	chips->chip.free = gpiochip_generic_free;
232#endif
233	spin_lock_init(&chips->lock);
234
235	chips->gpio_unbanked = gpio_unbanked;
236
237	nbank = DIV_ROUND_UP(ngpio, 32);
238	for (bank = 0; bank < nbank; bank++)
239		chips->regs[bank] = gpio_base + offset_array[bank];
240
241	ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
242	if (ret)
243		return ret;
244
245	platform_set_drvdata(pdev, chips);
246	ret = davinci_gpio_irq_setup(pdev);
247	if (ret)
248		return ret;
249
250	return 0;
251}
252
253/*--------------------------------------------------------------------------*/
254/*
255 * We expect irqs will normally be set up as input pins, but they can also be
256 * used as output pins ... which is convenient for testing.
257 *
258 * NOTE:  The first few GPIOs also have direct INTC hookups in addition
259 * to their GPIOBNK0 irq, with a bit less overhead.
260 *
261 * All those INTC hookups (direct, plus several IRQ banks) can also
262 * serve as EDMA event triggers.
263 */
264
265static void gpio_irq_mask(struct irq_data *d)
266{
267	struct davinci_gpio_controller *chips = irq_data_get_irq_chip_data(d);
268	irq_hw_number_t hwirq = irqd_to_hwirq(d);
269	struct davinci_gpio_regs __iomem *g = chips->regs[hwirq / 32];
270	uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
271
272	writel_relaxed(mask, &g->clr_falling);
273	writel_relaxed(mask, &g->clr_rising);
274
275	gpiochip_disable_irq(&chips->chip, hwirq);
276}
277
278static void gpio_irq_unmask(struct irq_data *d)
279{
280	struct davinci_gpio_controller *chips = irq_data_get_irq_chip_data(d);
281	irq_hw_number_t hwirq = irqd_to_hwirq(d);
282	struct davinci_gpio_regs __iomem *g = chips->regs[hwirq / 32];
283	uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
284	unsigned status = irqd_get_trigger_type(d);
285
286	gpiochip_enable_irq(&chips->chip, hwirq);
287
288	status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
289	if (!status)
290		status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
291
292	if (status & IRQ_TYPE_EDGE_FALLING)
293		writel_relaxed(mask, &g->set_falling);
294	if (status & IRQ_TYPE_EDGE_RISING)
295		writel_relaxed(mask, &g->set_rising);
296}
297
298static int gpio_irq_type(struct irq_data *d, unsigned trigger)
299{
300	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
301		return -EINVAL;
302
303	return 0;
304}
305
306static const struct irq_chip gpio_irqchip = {
307	.name		= "GPIO",
308	.irq_unmask	= gpio_irq_unmask,
309	.irq_mask	= gpio_irq_mask,
310	.irq_set_type	= gpio_irq_type,
311	.flags		= IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE,
312	GPIOCHIP_IRQ_RESOURCE_HELPERS,
313};
314
315static void gpio_irq_handler(struct irq_desc *desc)
316{
317	struct davinci_gpio_regs __iomem *g;
318	u32 mask = 0xffff;
319	int bank_num;
320	struct davinci_gpio_controller *d;
321	struct davinci_gpio_irq_data *irqdata;
322
323	irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
324	bank_num = irqdata->bank_num;
325	g = irqdata->regs;
326	d = irqdata->chip;
327
328	/* we only care about one bank */
329	if ((bank_num % 2) == 1)
330		mask <<= 16;
331
332	/* temporarily mask (level sensitive) parent IRQ */
333	chained_irq_enter(irq_desc_get_chip(desc), desc);
334	while (1) {
335		u32		status;
336		int		bit;
337		irq_hw_number_t hw_irq;
338
339		/* ack any irqs */
340		status = readl_relaxed(&g->intstat) & mask;
341		if (!status)
342			break;
343		writel_relaxed(status, &g->intstat);
344
345		/* now demux them to the right lowlevel handler */
346
347		while (status) {
348			bit = __ffs(status);
349			status &= ~BIT(bit);
350			/* Max number of gpios per controller is 144 so
351			 * hw_irq will be in [0..143]
352			 */
353			hw_irq = (bank_num / 2) * 32 + bit;
354
355			generic_handle_domain_irq(d->irq_domain, hw_irq);
356		}
357	}
358	chained_irq_exit(irq_desc_get_chip(desc), desc);
359	/* now it may re-trigger */
360}
361
362static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
363{
364	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
365
366	if (d->irq_domain)
367		return irq_create_mapping(d->irq_domain, offset);
368	else
369		return -ENXIO;
370}
371
372static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
373{
374	struct davinci_gpio_controller *d = gpiochip_get_data(chip);
375
376	/*
377	 * NOTE:  we assume for now that only irqs in the first gpio_chip
378	 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
379	 */
380	if (offset < d->gpio_unbanked)
381		return d->irqs[offset];
382	else
383		return -ENODEV;
384}
385
386static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
387{
388	struct davinci_gpio_controller *d;
389	struct davinci_gpio_regs __iomem *g;
390	u32 mask, i;
391
392	d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
393	g = (struct davinci_gpio_regs __iomem *)d->regs[0];
394	for (i = 0; i < MAX_INT_PER_BANK; i++)
395		if (data->irq == d->irqs[i])
396			break;
397
398	if (i == MAX_INT_PER_BANK)
399		return -EINVAL;
400
401	mask = __gpio_mask(i);
402
403	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
404		return -EINVAL;
405
406	writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
407		     ? &g->set_falling : &g->clr_falling);
408	writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
409		     ? &g->set_rising : &g->clr_rising);
410
411	return 0;
412}
413
414static int
415davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
416		     irq_hw_number_t hw)
417{
418	struct davinci_gpio_controller *chips =
419				(struct davinci_gpio_controller *)d->host_data;
420
421	irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
422				"davinci_gpio");
423	irq_set_irq_type(irq, IRQ_TYPE_NONE);
424	irq_set_chip_data(irq, (__force void *)chips);
425	irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
426
427	return 0;
428}
429
430static const struct irq_domain_ops davinci_gpio_irq_ops = {
431	.map = davinci_gpio_irq_map,
432	.xlate = irq_domain_xlate_onetwocell,
433};
434
435static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
436{
437	static struct irq_chip_type gpio_unbanked;
438
439	gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
440
441	return &gpio_unbanked.chip;
442};
443
444static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
445{
446	static struct irq_chip gpio_unbanked;
447
448	gpio_unbanked = *irq_get_chip(irq);
449	return &gpio_unbanked;
450};
451
452static const struct of_device_id davinci_gpio_ids[];
453
454/*
455 * NOTE:  for suspend/resume, probably best to make a platform_device with
456 * suspend_late/resume_resume calls hooking into results of the set_wake()
457 * calls ... so if no gpios are wakeup events the clock can be disabled,
458 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
459 * (dm6446) can be set appropriately for GPIOV33 pins.
460 */
461
462static int davinci_gpio_irq_setup(struct platform_device *pdev)
463{
464	unsigned	gpio, bank;
465	int		irq;
466	struct clk	*clk;
467	u32		binten = 0;
468	unsigned	ngpio;
469	struct device *dev = &pdev->dev;
470	struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
471	struct davinci_gpio_regs __iomem *g;
472	struct irq_domain	*irq_domain = NULL;
473	struct irq_chip *irq_chip;
474	struct davinci_gpio_irq_data *irqdata;
475	gpio_get_irq_chip_cb_t gpio_get_irq_chip;
476
477	/*
478	 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
479	 */
480	gpio_get_irq_chip = davinci_gpio_get_irq_chip;
481	if (dev->of_node)
482		gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)device_get_match_data(dev);
483
484	ngpio = chips->chip.ngpio;
485
486	clk = devm_clk_get_enabled(dev, "gpio");
487	if (IS_ERR(clk)) {
488		dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
489		return PTR_ERR(clk);
490	}
491
492	if (!chips->gpio_unbanked) {
493		irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
494		if (irq < 0) {
495			dev_err(dev, "Couldn't allocate IRQ numbers\n");
496			return irq;
497		}
498
499		irq_domain = irq_domain_create_legacy(dev_fwnode(dev), ngpio, irq, 0,
500						      &davinci_gpio_irq_ops, chips);
501		if (!irq_domain) {
502			dev_err(dev, "Couldn't register an IRQ domain\n");
503			return -ENODEV;
504		}
505	}
506
507	/*
508	 * Arrange gpiod_to_irq() support, handling either direct IRQs or
509	 * banked IRQs.  Having GPIOs in the first GPIO bank use direct
510	 * IRQs, while the others use banked IRQs, would need some setup
511	 * tweaks to recognize hardware which can do that.
512	 */
513	chips->chip.to_irq = gpio_to_irq_banked;
514	chips->irq_domain = irq_domain;
515
516	/*
517	 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
518	 * controller only handling trigger modes.  We currently assume no
519	 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
520	 */
521	if (chips->gpio_unbanked) {
522		/* pass "bank 0" GPIO IRQs to AINTC */
523		chips->chip.to_irq = gpio_to_irq_unbanked;
524
525		binten = GENMASK(chips->gpio_unbanked / 16, 0);
526
527		/* AINTC handles mask/unmask; GPIO handles triggering */
528		irq = chips->irqs[0];
529		irq_chip = gpio_get_irq_chip(irq);
530		irq_chip->name = "GPIO-AINTC";
531		irq_chip->irq_set_type = gpio_irq_type_unbanked;
532
533		/* default trigger: both edges */
534		g = chips->regs[0];
535		writel_relaxed(~0, &g->set_falling);
536		writel_relaxed(~0, &g->set_rising);
537
538		/* set the direct IRQs up to use that irqchip */
539		for (gpio = 0; gpio < chips->gpio_unbanked; gpio++) {
540			irq_set_chip(chips->irqs[gpio], irq_chip);
541			irq_set_handler_data(chips->irqs[gpio], chips);
542			irq_set_status_flags(chips->irqs[gpio],
543					     IRQ_TYPE_EDGE_BOTH);
544		}
545
546		goto done;
547	}
548
549	/*
550	 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
551	 * then chain through our own handler.
552	 */
553	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
554		/* disabled by default, enabled only as needed
555		 * There are register sets for 32 GPIOs. 2 banks of 16
556		 * GPIOs are covered by each set of registers hence divide by 2
557		 */
558		g = chips->regs[bank / 2];
559		writel_relaxed(~0, &g->clr_falling);
560		writel_relaxed(~0, &g->clr_rising);
561
562		/*
563		 * Each chip handles 32 gpios, and each irq bank consists of 16
564		 * gpio irqs. Pass the irq bank's corresponding controller to
565		 * the chained irq handler.
566		 */
567		irqdata = devm_kzalloc(&pdev->dev,
568				       sizeof(struct
569					      davinci_gpio_irq_data),
570					      GFP_KERNEL);
571		if (!irqdata)
572			return -ENOMEM;
573
574		irqdata->regs = g;
575		irqdata->bank_num = bank;
576		irqdata->chip = chips;
577
578		irq_set_chained_handler_and_data(chips->irqs[bank],
579						 gpio_irq_handler, irqdata);
580
581		binten |= BIT(bank);
582	}
583
584done:
585	/*
586	 * BINTEN -- per-bank interrupt enable. genirq would also let these
587	 * bits be set/cleared dynamically.
588	 */
589	writel_relaxed(binten, gpio_base + BINTEN);
590
591	return 0;
592}
593
594static void davinci_gpio_save_context(struct davinci_gpio_controller *chips,
595				      u32 nbank)
596{
597	struct davinci_gpio_regs __iomem *g;
598	struct davinci_gpio_regs *context;
599	u32 bank;
600	void __iomem *base;
601
602	base = chips->regs[0] - offset_array[0];
603	chips->binten_context = readl_relaxed(base + BINTEN);
604
605	for (bank = 0; bank < nbank; bank++) {
606		g = chips->regs[bank];
607		context = &chips->context[bank];
608		context->dir = readl_relaxed(&g->dir);
609		context->set_data = readl_relaxed(&g->set_data);
610		context->set_rising = readl_relaxed(&g->set_rising);
611		context->set_falling = readl_relaxed(&g->set_falling);
612	}
613
614	/* Clear all interrupt status registers */
615	writel_relaxed(GENMASK(31, 0), &g->intstat);
616}
617
618static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips,
619					 u32 nbank)
620{
621	struct davinci_gpio_regs __iomem *g;
622	struct davinci_gpio_regs *context;
623	u32 bank;
624	void __iomem *base;
625
626	base = chips->regs[0] - offset_array[0];
627
628	if (readl_relaxed(base + BINTEN) != chips->binten_context)
629		writel_relaxed(chips->binten_context, base + BINTEN);
630
631	for (bank = 0; bank < nbank; bank++) {
632		g = chips->regs[bank];
633		context = &chips->context[bank];
634		if (readl_relaxed(&g->dir) != context->dir)
635			writel_relaxed(context->dir, &g->dir);
636		if (readl_relaxed(&g->set_data) != context->set_data)
637			writel_relaxed(context->set_data, &g->set_data);
638		if (readl_relaxed(&g->set_rising) != context->set_rising)
639			writel_relaxed(context->set_rising, &g->set_rising);
640		if (readl_relaxed(&g->set_falling) != context->set_falling)
641			writel_relaxed(context->set_falling, &g->set_falling);
642	}
643}
644
645static int davinci_gpio_suspend(struct device *dev)
646{
647	struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
648	u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32);
649
650	davinci_gpio_save_context(chips, nbank);
651
652	return 0;
653}
654
655static int davinci_gpio_resume(struct device *dev)
656{
657	struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
658	u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32);
659
660	davinci_gpio_restore_context(chips, nbank);
661
662	return 0;
663}
664
665static DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend,
666			 davinci_gpio_resume);
667
668static const struct of_device_id davinci_gpio_ids[] = {
669	{ .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
670	{ .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
671	{ .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
672	{ /* sentinel */ },
673};
674MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
675
676static struct platform_driver davinci_gpio_driver = {
677	.probe		= davinci_gpio_probe,
678	.driver		= {
679		.name		= "davinci_gpio",
680		.pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops),
681		.of_match_table	= davinci_gpio_ids,
682	},
683};
684
685/*
686 * GPIO driver registration needs to be done before machine_init functions
687 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
688 */
689static int __init davinci_gpio_drv_reg(void)
690{
691	return platform_driver_register(&davinci_gpio_driver);
692}
693postcore_initcall(davinci_gpio_drv_reg);
694
695static void __exit davinci_gpio_exit(void)
696{
697	platform_driver_unregister(&davinci_gpio_driver);
698}
699module_exit(davinci_gpio_exit);
700
701MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
702MODULE_DESCRIPTION("DAVINCI GPIO driver");
703MODULE_LICENSE("GPL");
704MODULE_ALIAS("platform:gpio-davinci");