mite.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2
  3/*
  4 *   Hardware driver for NI Mite PCI interface chip
  5 *
  6 *   Copyright (C) 1999 David A. Schleef <ds@stm.lbl.gov>
  7 */
  8
  9#ifndef _MITE_H_
 10#define _MITE_H_
 11
 12#include <linux/pci.h>
 13
 14#define PCI_VENDOR_ID_NATINST		0x1093
 15
 16//#define DEBUG_MITE
 17
 18#ifdef DEBUG_MITE
 19#define MDPRINTK(format, args...) pr_debug(format, ## args)
 20#else
 21#define MDPRINTK(args...)
 22#endif
 23
 24#define MITE_RING_SIZE 3000
 25struct mite_dma_chain {
 26	u32 count;
 27	u32 addr;
 28	u32 next;
 29};
 30
 31struct mite_struct {
 32	struct mite_struct *next;
 33	int used;
 34
 35	struct pci_dev *pcidev;
 36	unsigned long mite_phys_addr;
 37	void __iomem *mite_io_addr;
 38	unsigned long daq_phys_addr;
 39	void __iomem *daq_io_addr;
 40
 41	int DMA_CheckNearEnd;
 42
 43	struct mite_dma_chain ring[MITE_RING_SIZE];
 44};
 45
 46extern struct mite_struct *mite_devices;
 47
 48extern inline unsigned int mite_irq(struct mite_struct *mite)
 49{
 50	return mite->pcidev->irq;
 51};
 52
 53extern inline unsigned int mite_device_id(struct mite_struct *mite)
 54{
 55	return mite->pcidev->device;
 56};
 57
 58void mite_init(void);
 59void mite_cleanup(void);
 60int mite_setup(struct mite_struct *mite);
 61void mite_unsetup(struct mite_struct *mite);
 62void mite_list_devices(void);
 63
 64#define CHAN_OFFSET(x)			(0x100 * (x))
 65
 66/* DMA base for chan 0 is 0x500, chan 1 is 0x600 */
 67
 68#define MITE_CHOR		0x500
 69#define CHOR_DMARESET			BIT(31)
 70#define CHOR_SET_SEND_TC		BIT(11)
 71#define CHOR_CLR_SEND_TC		BIT(10)
 72#define CHOR_SET_LPAUSE			BIT(9)
 73#define CHOR_CLR_LPAUSE			BIT(8)
 74#define CHOR_CLRDONE			BIT(7)
 75#define CHOR_CLRRB			BIT(6)
 76#define CHOR_CLRLC			BIT(5)
 77#define CHOR_FRESET			BIT(4)
 78#define CHOR_ABORT			BIT(3)
 79#define CHOR_STOP			BIT(2)
 80#define CHOR_CONT			BIT(1)
 81#define CHOR_START			BIT(0)
 82#define CHOR_PON			(CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE)
 83
 84#define MITE_CHCR		0x504
 85#define CHCR_SET_DMA_IE			BIT(31)
 86#define CHCR_CLR_DMA_IE			BIT(30)
 87#define CHCR_SET_LINKP_IE		BIT(29)
 88#define CHCR_CLR_LINKP_IE		BIT(28)
 89#define CHCR_SET_SAR_IE			BIT(27)
 90#define CHCR_CLR_SAR_IE			BIT(26)
 91#define CHCR_SET_DONE_IE		BIT(25)
 92#define CHCR_CLR_DONE_IE		BIT(24)
 93#define CHCR_SET_MRDY_IE		BIT(23)
 94#define CHCR_CLR_MRDY_IE		BIT(22)
 95#define CHCR_SET_DRDY_IE		BIT(21)
 96#define CHCR_CLR_DRDY_IE		BIT(20)
 97#define CHCR_SET_LC_IE			BIT(19)
 98#define CHCR_CLR_LC_IE			BIT(18)
 99#define CHCR_SET_CONT_RB_IE		BIT(17)
100#define CHCR_CLR_CONT_RB_IE		BIT(16)
101#define CHCR_FIFODIS			BIT(15)
102#define CHCR_FIFO_ON			0
103#define CHCR_BURSTEN			BIT(14)
104#define CHCR_NO_BURSTEN			0
105#define CHCR_NFTP(x)			((x) << 11)
106#define CHCR_NFTP0			CHCR_NFTP(0)
107#define CHCR_NFTP1			CHCR_NFTP(1)
108#define CHCR_NFTP2			CHCR_NFTP(2)
109#define CHCR_NFTP4			CHCR_NFTP(3)
110#define CHCR_NFTP8			CHCR_NFTP(4)
111#define CHCR_NFTP16			CHCR_NFTP(5)
112#define CHCR_NETP(x)			((x) << 11)
113#define CHCR_NETP0			CHCR_NETP(0)
114#define CHCR_NETP1			CHCR_NETP(1)
115#define CHCR_NETP2			CHCR_NETP(2)
116#define CHCR_NETP4			CHCR_NETP(3)
117#define CHCR_NETP8			CHCR_NETP(4)
118#define CHCR_CHEND1			BIT(5)
119#define CHCR_CHEND0			BIT(4)
120#define CHCR_DIR			BIT(3)
121#define CHCR_DEV_TO_MEM			CHCR_DIR
122#define CHCR_MEM_TO_DEV			0
123#define CHCR_NORMAL			((0) << 0)
124#define CHCR_CONTINUE			((1) << 0)
125#define CHCR_RINGBUFF			((2) << 0)
126#define CHCR_LINKSHORT			((4) << 0)
127#define CHCR_LINKLONG			((5) << 0)
128#define CHCRPON				(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | \
129					 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | \
130					 CHCR_CLR_LC_IE | CHCR_CLR_CONT_IE)
131
132#define MITE_TCR		0x508
133
134/* CR bits */
135#define CR_RL(x)			((x) << 21)
136#define CR_RL0				CR_RL(0)
137#define CR_RL1				CR_RL(1)
138#define CR_RL2				CR_RL(2)
139#define CR_RL4				CR_RL(3)
140#define CR_RL8				CR_RL(4)
141#define CR_RL16				CR_RL(5)
142#define CR_RL32				CR_RL(6)
143#define CR_RL64				CR_RL(7)
144#define CR_RD(x)			((x) << 19)
145#define CR_RD0				CR_RD(0)
146#define CR_RD32				CR_RD(1)
147#define CR_RD512			CR_RD(2)
148#define CR_RD8192			CR_RD(3)
149#define CR_REQS(x)			((x) << 16)
150#define CR_REQSDRQ0			CR_REQS(4)
151#define CR_REQSDRQ1			CR_REQS(5)
152#define CR_REQSDRQ2			CR_REQS(6)
153#define CR_REQSDRQ3			CR_REQS(7)
154#define CR_ASEQX(x)			((x) << 10)
155#define CR_ASEQX0			CR_ASEQX(0)
156#define	CR_ASEQDONT			CR_ASEQX0
157#define CR_ASEQXP1			CR_ASEQX(1)
158#define CR_ASEQUP			CR_ASEQXP1
159#define CR_ASEQXP2			CR_ASEQX(2)
160#define CR_ASEQDOWN			CR_ASEQXP2
161#define CR_ASEQXP4			CR_ASEQX(3)
162#define CR_ASEQXP8			CR_ASEQX(4)
163#define CR_ASEQXP16			CR_ASEQX(5)
164#define CR_ASEQXP32			CR_ASEQX(6)
165#define CR_ASEQXP64			CR_ASEQX(7)
166#define CR_ASEQXM1			CR_ASEQX(9)
167#define CR_ASEQXM2			CR_ASEQX(10)
168#define CR_ASEQXM4			CR_ASEQX(11)
169#define CR_ASEQXM8			CR_ASEQX(12)
170#define CR_ASEQXM16			CR_ASEQX(13)
171#define CR_ASEQXM32			CR_ASEQX(14)
172#define CR_ASEQXM64			CR_ASEQX(15)
173#define CR_PSIZEBYTE			BIT(8)
174#define CR_PSIZEHALF			(2 << 8)
175#define CR_PSIZEWORD			(3 << 8)
176#define CR_PORTCPU			(0 << 6)
177#define CR_PORTIO			BIT(6)
178#define CR_PORTVXI			(2 << 6)
179#define CR_PORTMXI			(3 << 6)
180#define CR_AMDEVICE			BIT(0)
181
182#define CHSR_INT			0x80000000
183#define CHSR_DONE			0x02000000
184#define CHSR_LINKC			0x00080000
185
186#define MITE_MCR		0x50c
187#define	MCRPON				0
188
189#define MITE_MAR		0x510
190
191#define MITE_DCR		0x514
192#define DCR_NORMAL			BIT(29)
193#define DCRPON				0
194
195#define MITE_DAR		0x518
196
197#define MITE_LKCR		0x51c
198
199#define MITE_LKAR		0x520
200#define MITE_LLKAR		0x524
201#define MITE_BAR		0x528
202#define MITE_BCR		0x52c
203#define MITE_SAR		0x530
204#define MITE_WSCR		0x534
205#define MITE_WSER		0x538
206#define MITE_CHSR		0x53c
207#define MITE_FCR		0x540
208
209#define MITE_FIFO		0x80
210#define MITE_FIFOEND		0xff
211
212#define MITE_AMRAM		        0x00
213#define MITE_AMDEVICE		        0x01
214#define MITE_AMHOST_A32_SINGLE	        0x09
215#define MITE_AMHOST_A24_SINGLE	        0x39
216#define MITE_AMHOST_A16_SINGLE	        0x29
217#define MITE_AMHOST_A32_BLOCK	        0x0b
218#define MITE_AMHOST_A32D64_BLOCK	0x08
219#define MITE_AMHOST_A24_BLOCK	        0x3b
220
221enum mite_registers {
222	MITE_IODWBSR = 0xc0,	// IO Device Window Base Size Register
223	MITE_CSIGR = 0x460,	// chip signature
224	MITE_IODWBSR_1 = 0xc4,	// IO Device Window Base Size Register 1 (used by 6602 boards)
225	MITE_IODWCR_1 = 0xf4
226};
227
228enum MITE_IODWBSR_bits {
229	WENAB = 0x80,		// window enable
230	WENAB_6602 = 0x8c	// window enable for 6602 boards
231};
232
233#endif
234