amccs5933.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2
 3/***************************************************************************
 4 * Registers and bits for amccs5933 pci chip
 5 *    copyright            : (C) 2002 by Frank Mori Hess
 6 ***************************************************************************/
 7
 8// register offsets
 9enum {
10	MBEF_REG = 0x34,	// mailbux empty/full
11	INTCSR_REG = 0x38,	// interrupt control and status
12	BMCSR_REG = 0x3c,	// bus master control and status
13};
14
15// incoming mailbox 0-3  register offsets
16extern inline int INCOMING_MAILBOX_REG(unsigned int mailbox)
17{
18	return (0x10 + 4 * mailbox);
19};
20
21// bit definitions
22
23// INTCSR bits
24enum {
25	OUTBOX_EMPTY_INTR_BIT = 0x10,	// enable outbox empty interrupt
26	INBOX_FULL_INTR_BIT = 0x1000,	// enable inbox full interrupt
27	INBOX_INTR_CS_BIT = 0x20000,	// read, or write clear inbox full interrupt
28	INTR_ASSERTED_BIT = 0x800000,	// read only, interrupt asserted
29};
30
31// select byte 0 to 3 of incoming mailbox
32extern inline int INBOX_BYTE_BITS(unsigned int byte)
33{
34	return (byte & 0x3) << 8;
35};
36
37// select incoming mailbox 0 to 3
38extern inline int INBOX_SELECT_BITS(unsigned int mailbox)
39{
40	return (mailbox & 0x3) << 10;
41};
42
43// select byte 0 to 3 of outgoing mailbox
44extern inline int OUTBOX_BYTE_BITS(unsigned int byte)
45{
46	return (byte & 0x3);
47};
48
49// select outgoing mailbox 0 to 3
50extern inline int OUTBOX_SELECT_BITS(unsigned int mailbox)
51{
52	return (mailbox & 0x3) << 2;
53};
54
55// BMCSR bits
56enum {
57	MBOX_FLAGS_RESET_BIT = 0x08000000,	// resets mailbox empty/full flags
58};
59