hp_82341.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2
  3/***************************************************************************
  4 *    copyright            : (C) 2002, 2005 by Frank Mori Hess             *
  5 ***************************************************************************/
  6
  7#include "tms9914.h"
  8#include "gpibP.h"
  9
 10enum hp_82341_hardware_version {
 11	HW_VERSION_UNKNOWN,
 12	HW_VERSION_82341C,
 13	HW_VERSION_82341D,
 14};
 15
 16// struct which defines private_data for board
 17struct hp_82341_priv {
 18	struct tms9914_priv tms9914_priv;
 19	unsigned int irq;
 20	unsigned short config_control_bits;
 21	unsigned short mode_control_bits;
 22	unsigned short event_status_bits;
 23	struct pnp_dev *pnp_dev;
 24	unsigned long iobase[4];
 25	unsigned long io_region_offset;
 26	enum hp_82341_hardware_version hw_version;
 27};
 28
 29static const int hp_82341_region_iosize = 0x8;
 30static const int hp_82341_num_io_regions = 4;
 31static const int hp_82341_fifo_size = 0xffe;
 32static const int hp_82341c_firmware_length = 5764;
 33static const int hp_82341d_firmware_length = 5302;
 34
 35// hp 82341 register offsets
 36enum hp_82341_region_0_registers {
 37	CONFIG_CONTROL_STATUS_REG = 0x0,
 38	MODE_CONTROL_STATUS_REG = 0x1,
 39	MONITOR_REG = 0x2,	// after initialization
 40	XILINX_DATA_REG = 0x2,	// before initialization, write only
 41	INTERRUPT_ENABLE_REG = 0x3,
 42	EVENT_STATUS_REG = 0x4,
 43	EVENT_ENABLE_REG = 0x5,
 44	STREAM_STATUS_REG = 0x7,
 45};
 46
 47enum hp_82341_region_1_registers {
 48	ID0_REG = 0x2,
 49	ID1_REG = 0x3,
 50	TRANSFER_COUNT_LOW_REG = 0x4,
 51	TRANSFER_COUNT_MID_REG = 0x5,
 52	TRANSFER_COUNT_HIGH_REG = 0x6,
 53};
 54
 55enum hp_82341_region_3_registers {
 56	BUFFER_PORT_LOW_REG = 0x0,
 57	BUFFER_PORT_HIGH_REG = 0x1,
 58	ID2_REG = 0x2,
 59	ID3_REG = 0x3,
 60	BUFFER_FLUSH_REG = 0x4,
 61	BUFFER_CONTROL_REG = 0x7
 62};
 63
 64enum config_control_status_bits {
 65	IRQ_SELECT_MASK = 0x7,
 66	DMA_CONFIG_MASK = 0x18,
 67	ENABLE_DMA_CONFIG_BIT = 0x20,
 68	XILINX_READY_BIT = 0x40,	// read only
 69	DONE_PGL_BIT = 0x80
 70};
 71
 72static inline unsigned int IRQ_SELECT_BITS(int irq)
 73{
 74	switch (irq) {
 75	case 3:
 76		return 0x3;
 77	case 5:
 78		return 0x2;
 79	case 7:
 80		return 0x1;
 81	case 9:
 82		return 0x0;
 83	case 10:
 84		return 0x7;
 85	case 11:
 86		return 0x6;
 87	case 12:
 88		return 0x5;
 89	case 15:
 90		return 0x4;
 91	default:
 92		return 0x0;
 93	}
 94};
 95
 96enum mode_control_status_bits {
 97	SLOT8_BIT = 0x1,		// read only
 98	ACTIVE_CONTROLLER_BIT = 0x2,	// read only
 99	ENABLE_DMA_BIT = 0x4,
100	SYSTEM_CONTROLLER_BIT = 0x8,
101	MONITOR_BIT = 0x10,
102	ENABLE_IRQ_CONFIG_BIT = 0x20,
103	ENABLE_TI_STREAM_BIT = 0x40
104};
105
106enum monitor_bits {
107	MONITOR_INTERRUPT_PENDING_BIT = 0x1,	// read only
108	MONITOR_CLEAR_HOLDOFF_BIT = 0x2,	// write only
109	MONITOR_PPOLL_BIT = 0x4,		// write clear
110	MONITOR_SRQ_BIT = 0x8,			// write clear
111	MONITOR_IFC_BIT = 0x10,			// write clear
112	MONITOR_REN_BIT = 0x20,			// write clear
113	MONITOR_END_BIT = 0x40,			// write clear
114	MONITOR_DAV_BIT = 0x80			// write clear
115};
116
117enum interrupt_enable_bits {
118	ENABLE_TI_INTERRUPT_BIT = 0x1,
119	ENABLE_POINTERS_EQUAL_INTERRUPT_BIT = 0x4,
120	ENABLE_BUFFER_END_INTERRUPT_BIT = 0x10,
121	ENABLE_TERMINAL_COUNT_INTERRUPT_BIT = 0x20,
122	ENABLE_DMA_TERMINAL_COUNT_INTERRUPT_BIT = 0x80,
123};
124
125enum event_status_bits {
126	TI_INTERRUPT_EVENT_BIT = 0x1,		// write clear
127	INTERRUPT_PENDING_EVENT_BIT = 0x2,	// read only
128	POINTERS_EQUAL_EVENT_BIT = 0x4,		// write clear
129	BUFFER_END_EVENT_BIT = 0x10,		// write clear
130	TERMINAL_COUNT_EVENT_BIT = 0x20,	// write clear
131	DMA_TERMINAL_COUNT_EVENT_BIT = 0x80,	// write clear
132};
133
134enum event_enable_bits {
135	ENABLE_TI_INTERRUPT_EVENT_BIT = 0x1,		// write clear
136	ENABLE_POINTERS_EQUAL_EVENT_BIT = 0x4,		// write clear
137	ENABLE_BUFFER_END_EVENT_BIT = 0x10,		// write clear
138	ENABLE_TERMINAL_COUNT_EVENT_BIT = 0x20,		// write clear
139	ENABLE_DMA_TERMINAL_COUNT_EVENT_BIT = 0x80,	// write clear
140};
141
142enum stream_status_bits {
143	HALTED_STATUS_BIT = 0x1,	// read
144	RESTART_STREAM_BIT = 0x1	// write
145};
146
147enum buffer_control_bits {
148	DIRECTION_GPIB_TO_HOST_BIT = 0x20,	// transfer direction (set for gpib to host)
149	ENABLE_TI_BUFFER_BIT = 0x40,		// enable fifo
150	FAST_WR_EN_BIT = 0x80,			// 350 ns t1 delay?
151};
152
153// registers accessible through isapnp chip on 82341d
154enum hp_82341d_pnp_registers {
155	PIO_DATA_REG = 0x20,		// read/write pio data lines
156	PIO_DIRECTION_REG = 0x21,	// set pio data line directions (set for input)
157};
158
159enum hp_82341d_pnp_pio_bits {
160	HP_82341D_XILINX_READY_BIT = 0x1,
161	HP_82341D_XILINX_DONE_BIT = 0x2,
162	// use register layout compatible with C and older versions instead of 32 contiguous ioports
163	HP_82341D_LEGACY_MODE_BIT = 0x4,
164	HP_82341D_NOT_PROG_BIT = 0x8,	// clear to reinitialize xilinx
165};