fmh_gpib.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2
  3/***************************************************************************
  4 *    Author: Frank Mori Hess <fmh6jj@gmail.com>
  5 *   Copyright: (C) 2006, 2010, 2015 Fluke Corporation
  6 *	(C) 2017 Frank Mori Hess
  7 ***************************************************************************/
  8
  9#include <linux/dmaengine.h>
 10#include <linux/ioport.h>
 11#include <linux/pci.h>
 12#include <linux/io.h>
 13#include "nec7210.h"
 14
 15static const int fifo_reg_offset = 2;
 16
 17static const int gpib_control_status_pci_resource_index;
 18static const int gpib_fifo_pci_resource_index = 1;
 19
 20/* We don't have a real pci vendor/device id, the following will need to be
 21 * patched to match prototype hardware.
 22 */
 23#define BOGUS_PCI_VENDOR_ID_FLUKE 0xffff
 24#define BOGUS_PCI_DEVICE_ID_FLUKE_BLADERUNNER 0x0
 25
 26struct fmh_priv {
 27	struct nec7210_priv nec7210_priv;
 28	struct resource *gpib_iomem_res;
 29	struct resource *write_transfer_counter_res;
 30	struct resource *dma_port_res;
 31	int irq;
 32	struct dma_chan *dma_channel;
 33	u8 *dma_buffer;
 34	int dma_buffer_size;
 35	int dma_burst_length;
 36	void __iomem *fifo_base;
 37	unsigned supports_fifo_interrupts : 1;
 38};
 39
 40static inline int fmh_gpib_half_fifo_size(struct fmh_priv *priv)
 41{
 42	return priv->dma_burst_length;
 43}
 44
 45// registers beyond the nec7210 register set
 46enum fmh_gpib_regs {
 47	EXT_STATUS_1_REG = 0x9,
 48	STATE1_REG = 0xc,
 49	ISR0_IMR0_REG = 0xe,
 50	BUS_STATUS_REG = 0xf
 51};
 52
 53/* IMR0 -- Interrupt Mode Register 0 */
 54enum imr0_bits {
 55	ATN_INTERRUPT_ENABLE_BIT = 0x4,
 56	IFC_INTERRUPT_ENABLE_BIT = 0x8
 57};
 58
 59/* ISR0 -- Interrupt Status Register 0 */
 60enum isr0_bits {
 61	ATN_INTERRUPT_BIT = 0x4,
 62	IFC_INTERRUPT_BIT = 0x8
 63};
 64
 65enum state1_bits {
 66	SOURCE_HANDSHAKE_SIDS_BITS = 0x0, /* source idle state */
 67	SOURCE_HANDSHAKE_SGNS_BITS = 0x1, /* source generate state */
 68	SOURCE_HANDSHAKE_SDYS_BITS = 0x2, /* source delay state */
 69	SOURCE_HANDSHAKE_STRS_BITS = 0x5, /* source transfer state */
 70	SOURCE_HANDSHAKE_MASK = 0x7
 71};
 72
 73enum fmh_gpib_auxmr_bits {
 74	AUX_I_REG = 0xe0,
 75};
 76
 77enum aux_reg_i_bits {
 78	LOCAL_PPOLL_MODE_BIT = 0x4
 79};
 80
 81enum ext_status_1_bits {
 82	DATA_IN_STATUS_BIT = 0x01,
 83	DATA_OUT_STATUS_BIT = 0x02,
 84	COMMAND_OUT_STATUS_BIT = 0x04,
 85	RFD_HOLDOFF_STATUS_BIT = 0x08,
 86	END_STATUS_BIT = 0x10
 87};
 88
 89/* dma fifo reg and bits */
 90enum dma_fifo_regs {
 91	FIFO_DATA_REG = 0x0,
 92	FIFO_CONTROL_STATUS_REG = 0x1,
 93	FIFO_XFER_COUNTER_REG = 0x2,
 94	FIFO_MAX_BURST_LENGTH_REG = 0x3
 95};
 96
 97enum fifo_data_bits {
 98	FIFO_DATA_EOI_FLAG = 0x100
 99};
100
101enum fifo_control_bits {
102	TX_FIFO_DMA_REQUEST_ENABLE = 0x0001,
103	TX_FIFO_CLEAR = 0x0002,
104	TX_FIFO_HALF_EMPTY_INTERRUPT_ENABLE = 0x0008,
105	RX_FIFO_DMA_REQUEST_ENABLE = 0x0100,
106	RX_FIFO_CLEAR = 0x0200,
107	RX_FIFO_HALF_FULL_INTERRUPT_ENABLE = 0x0800
108};
109
110enum fifo_status_bits {
111	TX_FIFO_EMPTY = 0x0001,
112	TX_FIFO_FULL = 0x0002,
113	TX_FIFO_HALF_EMPTY = 0x0004,
114	TX_FIFO_HALF_EMPTY_INTERRUPT_IS_ENABLED = 0x0008,
115	TX_FIFO_DMA_REQUEST_IS_ENABLED = 0x0010,
116	RX_FIFO_EMPTY = 0x0100,
117	RX_FIFO_FULL = 0x0200,
118	RX_FIFO_HALF_FULL = 0x0400,
119	RX_FIFO_HALF_FULL_INTERRUPT_IS_ENABLED = 0x0800,
120	RX_FIFO_DMA_REQUEST_IS_ENABLED = 0x1000
121};
122
123static const unsigned int fifo_data_mask = 0x00ff;
124static const unsigned int fifo_xfer_counter_mask = 0x0fff;
125static const unsigned int fifo_max_burst_length_mask = 0x00ff;
126
127static inline u8 gpib_cs_read_byte(struct nec7210_priv *nec_priv,
128				   unsigned int register_num)
129{
130	return readb(nec_priv->mmiobase + register_num * nec_priv->offset);
131}
132
133static inline void gpib_cs_write_byte(struct nec7210_priv *nec_priv, u8 data,
134				      unsigned int register_num)
135{
136	writeb(data, nec_priv->mmiobase + register_num * nec_priv->offset);
137}
138
139static inline uint16_t fifos_read(struct fmh_priv *fmh_priv, int register_num)
140{
141	if (!fmh_priv->fifo_base)
142		return 0;
143	return readw(fmh_priv->fifo_base + register_num * fifo_reg_offset);
144}
145
146static inline void fifos_write(struct fmh_priv *fmh_priv, uint16_t data, int register_num)
147{
148	if (!fmh_priv->fifo_base)
149		return;
150	writew(data, fmh_priv->fifo_base + register_num * fifo_reg_offset);
151}
152
153enum bus_status_bits {
154	BSR_ATN_BIT = 0x01,
155	BSR_EOI_BIT = 0x02,
156	BSR_SRQ_BIT = 0x04,
157	BSR_IFC_BIT = 0x08,
158	BSR_REN_BIT = 0x10,
159	BSR_DAV_BIT = 0x20,
160	BSR_NRFD_BIT = 0x40,
161	BSR_NDAC_BIT = 0x80,
162};
163
164enum fmh_gpib_aux_cmds {
165	/* AUX_RTL2 is an auxiliary command which causes the cb7210 to assert
166	 * (and keep asserted) the local rtl message.  This is used in conjunction
167	 * with the normal nec7210 AUX_RTL command, which
168	 * pulses the rtl message, having the effect of clearing rtl if it was left
169	 * asserted by AUX_RTL2.
170	 */
171	AUX_RTL2 = 0x0d,
172	AUX_RFD_HOLDOFF_ASAP = 0x15,
173	AUX_REQT = 0x18,
174	AUX_REQF = 0x19,
175	AUX_LO_SPEED = 0x40,
176	AUX_HI_SPEED = 0x41
177};