fmh_gpib.c

   1// SPDX-License-Identifier: GPL-2.0
   2
   3/***************************************************************************
   4 * GPIB Driver for fmh_gpib_core, see
   5 * https://github.com/fmhess/fmh_gpib_core
   6 *
   7 * More specifically, it is a driver for the hardware arrangement described by
   8 *  src/examples/fmh_gpib_top.vhd in the fmh_gpib_core repository.
   9 *
  10 * Author: Frank Mori Hess <fmh6jj@gmail.com>
  11 * Copyright: (C) 2006, 2010, 2015 Fluke Corporation
  12 *	(C) 2017 Frank Mori Hess
  13 ***************************************************************************/
  14
  15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  16#define dev_fmt pr_fmt
  17#define DRV_NAME KBUILD_MODNAME
  18
  19#include "fmh_gpib.h"
  20
  21#include "gpibP.h"
  22#include <linux/delay.h>
  23#include <linux/device.h>
  24#include <linux/dma-mapping.h>
  25#include <linux/module.h>
  26#include <linux/of.h>
  27#include <linux/platform_device.h>
  28#include <linux/slab.h>
  29
  30MODULE_LICENSE("GPL");
  31MODULE_DESCRIPTION("GPIB Driver for fmh_gpib_core");
  32MODULE_AUTHOR("Frank Mori Hess <fmh6jj@gmail.com>");
  33
  34static irqreturn_t fmh_gpib_interrupt(int irq, void *arg);
  35static int fmh_gpib_attach_holdoff_all(struct gpib_board *board,
  36				       const struct gpib_board_config *config);
  37static int fmh_gpib_attach_holdoff_end(struct gpib_board *board,
  38				       const struct gpib_board_config *config);
  39static void fmh_gpib_detach(struct gpib_board *board);
  40static int fmh_gpib_pci_attach_holdoff_all(struct gpib_board *board,
  41					   const struct gpib_board_config *config);
  42static int fmh_gpib_pci_attach_holdoff_end(struct gpib_board *board,
  43					   const struct gpib_board_config *config);
  44static void fmh_gpib_pci_detach(struct gpib_board *board);
  45static int fmh_gpib_config_dma(struct gpib_board *board, int output);
  46static irqreturn_t fmh_gpib_internal_interrupt(struct gpib_board *board);
  47static struct platform_driver fmh_gpib_platform_driver;
  48static struct pci_driver fmh_gpib_pci_driver;
  49
  50// wrappers for interface functions
  51static int fmh_gpib_read(struct gpib_board *board, u8 *buffer, size_t length,
  52			 int *end, size_t *bytes_read)
  53{
  54	struct fmh_priv *priv = board->private_data;
  55
  56	return nec7210_read(board, &priv->nec7210_priv, buffer, length, end, bytes_read);
  57}
  58
  59static int fmh_gpib_write(struct gpib_board *board, u8 *buffer, size_t length,
  60			  int send_eoi, size_t *bytes_written)
  61{
  62	struct fmh_priv *priv = board->private_data;
  63
  64	return nec7210_write(board, &priv->nec7210_priv, buffer, length, send_eoi, bytes_written);
  65}
  66
  67static int fmh_gpib_command(struct gpib_board *board, u8 *buffer, size_t length,
  68			    size_t *bytes_written)
  69{
  70	struct fmh_priv *priv = board->private_data;
  71
  72	return nec7210_command(board, &priv->nec7210_priv, buffer, length, bytes_written);
  73}
  74
  75static int fmh_gpib_take_control(struct gpib_board *board, int synchronous)
  76{
  77	struct fmh_priv *priv = board->private_data;
  78
  79	return nec7210_take_control(board, &priv->nec7210_priv, synchronous);
  80}
  81
  82static int fmh_gpib_go_to_standby(struct gpib_board *board)
  83{
  84	struct fmh_priv *priv = board->private_data;
  85
  86	return nec7210_go_to_standby(board, &priv->nec7210_priv);
  87}
  88
  89static int fmh_gpib_request_system_control(struct gpib_board *board, int request_control)
  90{
  91	struct fmh_priv *priv = board->private_data;
  92	struct nec7210_priv *nec_priv = &priv->nec7210_priv;
  93
  94	return nec7210_request_system_control(board, nec_priv, request_control);
  95}
  96
  97static void fmh_gpib_interface_clear(struct gpib_board *board, int assert)
  98{
  99	struct fmh_priv *priv = board->private_data;
 100
 101	nec7210_interface_clear(board, &priv->nec7210_priv, assert);
 102}
 103
 104static void fmh_gpib_remote_enable(struct gpib_board *board, int enable)
 105{
 106	struct fmh_priv *priv = board->private_data;
 107
 108	nec7210_remote_enable(board, &priv->nec7210_priv, enable);
 109}
 110
 111static int fmh_gpib_enable_eos(struct gpib_board *board, u8 eos_byte, int compare_8_bits)
 112{
 113	struct fmh_priv *priv = board->private_data;
 114
 115	return nec7210_enable_eos(board, &priv->nec7210_priv, eos_byte, compare_8_bits);
 116}
 117
 118static void fmh_gpib_disable_eos(struct gpib_board *board)
 119{
 120	struct fmh_priv *priv = board->private_data;
 121
 122	nec7210_disable_eos(board, &priv->nec7210_priv);
 123}
 124
 125static unsigned int fmh_gpib_update_status(struct gpib_board *board, unsigned int clear_mask)
 126{
 127	struct fmh_priv *priv = board->private_data;
 128
 129	return nec7210_update_status(board, &priv->nec7210_priv, clear_mask);
 130}
 131
 132static int fmh_gpib_primary_address(struct gpib_board *board, unsigned int address)
 133{
 134	struct fmh_priv *priv = board->private_data;
 135
 136	return nec7210_primary_address(board, &priv->nec7210_priv, address);
 137}
 138
 139static int fmh_gpib_secondary_address(struct gpib_board *board, unsigned int address, int enable)
 140{
 141	struct fmh_priv *priv = board->private_data;
 142
 143	return nec7210_secondary_address(board, &priv->nec7210_priv, address, enable);
 144}
 145
 146static int fmh_gpib_parallel_poll(struct gpib_board *board, u8 *result)
 147{
 148	struct fmh_priv *priv = board->private_data;
 149
 150	return nec7210_parallel_poll(board, &priv->nec7210_priv, result);
 151}
 152
 153static void fmh_gpib_parallel_poll_configure(struct gpib_board *board, u8 configuration)
 154{
 155	struct fmh_priv *priv = board->private_data;
 156
 157	nec7210_parallel_poll_configure(board, &priv->nec7210_priv, configuration);
 158}
 159
 160static void fmh_gpib_parallel_poll_response(struct gpib_board *board, int ist)
 161{
 162	struct fmh_priv *priv = board->private_data;
 163
 164	nec7210_parallel_poll_response(board, &priv->nec7210_priv, ist);
 165}
 166
 167static void fmh_gpib_local_parallel_poll_mode(struct gpib_board *board, int local)
 168{
 169	struct fmh_priv *priv = board->private_data;
 170
 171	if (local) {
 172		write_byte(&priv->nec7210_priv, AUX_I_REG | LOCAL_PPOLL_MODE_BIT, AUXMR);
 173	} else	{
 174		/*
 175		 * For fmh_gpib_core, remote parallel poll config mode is unaffected by the
 176		 * state of the disable bit of the parallel poll register (unlike the tnt4882).
 177		 * So, we don't need to worry about that.
 178		 */
 179		write_byte(&priv->nec7210_priv, AUX_I_REG | 0x0, AUXMR);
 180	}
 181}
 182
 183static void fmh_gpib_serial_poll_response2(struct gpib_board *board, u8 status,
 184					   int new_reason_for_service)
 185{
 186	struct fmh_priv *priv = board->private_data;
 187	unsigned long flags;
 188	const int MSS = status & request_service_bit;
 189	const int reqt = MSS && new_reason_for_service;
 190	const int reqf = MSS == 0;
 191
 192	spin_lock_irqsave(&board->spinlock, flags);
 193	if (reqt) {
 194		priv->nec7210_priv.srq_pending = 1;
 195		clear_bit(SPOLL_NUM, &board->status);
 196	} else if (reqf) {
 197		priv->nec7210_priv.srq_pending = 0;
 198	}
 199
 200	if (reqt) {
 201		/*
 202		 * It may seem like a race to issue reqt before updating
 203		 * the status byte, but it is not.  The chip does not
 204		 * issue the reqt until the SPMR is written to at
 205		 * a later time.
 206		 */
 207		write_byte(&priv->nec7210_priv, AUX_REQT, AUXMR);
 208	} else if (reqf) {
 209		write_byte(&priv->nec7210_priv, AUX_REQF, AUXMR);
 210	}
 211	/*
 212	 * We need to always zero bit 6 of the status byte before writing it to
 213	 * the SPMR to insure we are using
 214	 * serial poll mode SP1, and not accidentally triggering mode SP3.
 215	 */
 216	write_byte(&priv->nec7210_priv, status & ~request_service_bit, SPMR);
 217	spin_unlock_irqrestore(&board->spinlock, flags);
 218}
 219
 220static u8 fmh_gpib_serial_poll_status(struct gpib_board *board)
 221{
 222	struct fmh_priv *priv = board->private_data;
 223
 224	return nec7210_serial_poll_status(board, &priv->nec7210_priv);
 225}
 226
 227static void fmh_gpib_return_to_local(struct gpib_board *board)
 228{
 229	struct fmh_priv *priv = board->private_data;
 230	struct nec7210_priv *nec_priv = &priv->nec7210_priv;
 231
 232	write_byte(nec_priv, AUX_RTL2, AUXMR);
 233	udelay(1);
 234	write_byte(nec_priv, AUX_RTL, AUXMR);
 235}
 236
 237static int fmh_gpib_line_status(const struct gpib_board *board)
 238{
 239	int status = VALID_ALL;
 240	int bsr_bits;
 241	struct fmh_priv *e_priv;
 242	struct nec7210_priv *nec_priv;
 243
 244	e_priv = board->private_data;
 245	nec_priv = &e_priv->nec7210_priv;
 246
 247	bsr_bits = read_byte(nec_priv, BUS_STATUS_REG);
 248
 249	if ((bsr_bits & BSR_REN_BIT) == 0)
 250		status |= BUS_REN;
 251	if ((bsr_bits & BSR_IFC_BIT) == 0)
 252		status |= BUS_IFC;
 253	if ((bsr_bits & BSR_SRQ_BIT) == 0)
 254		status |= BUS_SRQ;
 255	if ((bsr_bits & BSR_EOI_BIT) == 0)
 256		status |= BUS_EOI;
 257	if ((bsr_bits & BSR_NRFD_BIT) == 0)
 258		status |= BUS_NRFD;
 259	if ((bsr_bits & BSR_NDAC_BIT) == 0)
 260		status |= BUS_NDAC;
 261	if ((bsr_bits & BSR_DAV_BIT) == 0)
 262		status |= BUS_DAV;
 263	if ((bsr_bits & BSR_ATN_BIT) == 0)
 264		status |= BUS_ATN;
 265
 266	return status;
 267}
 268
 269static int fmh_gpib_t1_delay(struct gpib_board *board, unsigned int nano_sec)
 270{
 271	struct fmh_priv *e_priv = board->private_data;
 272	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 273	unsigned int retval;
 274
 275	retval = nec7210_t1_delay(board, nec_priv, nano_sec);
 276
 277	if (nano_sec <= 350) {
 278		write_byte(nec_priv, AUX_HI_SPEED, AUXMR);
 279		retval = 350;
 280	} else {
 281		write_byte(nec_priv, AUX_LO_SPEED, AUXMR);
 282	}
 283	return retval;
 284}
 285
 286static int lacs_or_read_ready(struct gpib_board *board)
 287{
 288	const struct fmh_priv *e_priv = board->private_data;
 289	const struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 290	int retval = 0;
 291	unsigned long flags;
 292
 293	spin_lock_irqsave(&board->spinlock, flags);
 294	retval = test_bit(LACS_NUM, &board->status) ||
 295		test_bit(READ_READY_BN, &nec_priv->state);
 296	spin_unlock_irqrestore(&board->spinlock, flags);
 297
 298	return retval;
 299}
 300
 301static int wait_for_read(struct gpib_board *board)
 302{
 303	struct fmh_priv *e_priv = board->private_data;
 304	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 305	int retval = 0;
 306
 307	if (wait_event_interruptible(board->wait,
 308				     lacs_or_read_ready(board) ||
 309				     test_bit(DEV_CLEAR_BN, &nec_priv->state) ||
 310				     test_bit(TIMO_NUM, &board->status)))
 311		retval = -ERESTARTSYS;
 312
 313	if (test_bit(TIMO_NUM, &board->status))
 314		retval = -ETIMEDOUT;
 315	if (test_and_clear_bit(DEV_CLEAR_BN, &nec_priv->state))
 316		retval = -EINTR;
 317	return retval;
 318}
 319
 320static int wait_for_rx_fifo_half_full_or_end(struct gpib_board *board)
 321{
 322	struct fmh_priv *e_priv = board->private_data;
 323	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 324	int retval = 0;
 325
 326	if (wait_event_interruptible(board->wait,
 327				     (fifos_read(e_priv, FIFO_CONTROL_STATUS_REG) &
 328				      RX_FIFO_HALF_FULL) ||
 329				     test_bit(RECEIVED_END_BN, &nec_priv->state) ||
 330				     test_bit(DEV_CLEAR_BN, &nec_priv->state) ||
 331				     test_bit(TIMO_NUM, &board->status)))
 332		retval = -ERESTARTSYS;
 333
 334	if (test_bit(TIMO_NUM, &board->status))
 335		retval = -ETIMEDOUT;
 336	if (test_and_clear_bit(DEV_CLEAR_BN, &nec_priv->state))
 337		retval = -EINTR;
 338	return retval;
 339}
 340
 341/*
 342 * Wait until the gpib chip is ready to accept a data out byte.
 343 */
 344static int wait_for_data_out_ready(struct gpib_board *board)
 345{
 346	struct fmh_priv *e_priv = board->private_data;
 347	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 348	int retval = 0;
 349
 350	if (wait_event_interruptible(board->wait,
 351				     (test_bit(TACS_NUM, &board->status) &&
 352				      (read_byte(nec_priv, EXT_STATUS_1_REG) &
 353				       DATA_OUT_STATUS_BIT)) ||
 354				     test_bit(DEV_CLEAR_BN, &nec_priv->state) ||
 355				     test_bit(TIMO_NUM, &board->status)))
 356		retval = -ERESTARTSYS;
 357
 358	if (test_bit(TIMO_NUM, &board->status))
 359		retval = -ETIMEDOUT;
 360	if (test_and_clear_bit(DEV_CLEAR_BN, &nec_priv->state))
 361		retval = -EINTR;
 362
 363	return retval;
 364}
 365
 366static void fmh_gpib_dma_callback(void *arg)
 367{
 368	struct gpib_board *board = arg;
 369	struct fmh_priv *e_priv = board->private_data;
 370	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 371	unsigned long flags;
 372
 373	spin_lock_irqsave(&board->spinlock, flags);
 374
 375	nec7210_set_reg_bits(nec_priv, IMR1, HR_DOIE | HR_DIIE, HR_DOIE | HR_DIIE);
 376	wake_up_interruptible(&board->wait);
 377
 378	fmh_gpib_internal_interrupt(board);
 379
 380	clear_bit(DMA_WRITE_IN_PROGRESS_BN, &nec_priv->state);
 381	clear_bit(DMA_READ_IN_PROGRESS_BN, &nec_priv->state);
 382
 383	spin_unlock_irqrestore(&board->spinlock, flags);
 384}
 385
 386/*
 387 * returns true when all the bytes of a write have been transferred to
 388 * the chip and successfully transferred out over the gpib bus.
 389 */
 390static int fmh_gpib_all_bytes_are_sent(struct fmh_priv *e_priv)
 391{
 392	if (fifos_read(e_priv, FIFO_XFER_COUNTER_REG) & fifo_xfer_counter_mask)
 393		return 0;
 394
 395	if ((read_byte(&e_priv->nec7210_priv, EXT_STATUS_1_REG) & DATA_OUT_STATUS_BIT) == 0)
 396		return 0;
 397
 398	return 1;
 399}
 400
 401static int fmh_gpib_dma_write(struct gpib_board *board, u8 *buffer, size_t length,
 402			      size_t *bytes_written)
 403{
 404	struct fmh_priv *e_priv = board->private_data;
 405	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 406	unsigned long flags;
 407	int retval = 0;
 408	dma_addr_t address;
 409	struct dma_async_tx_descriptor *tx_desc;
 410
 411	*bytes_written = 0;
 412	if (WARN_ON_ONCE(length > e_priv->dma_buffer_size))
 413		return -EFAULT;
 414	dmaengine_terminate_all(e_priv->dma_channel);
 415	memcpy(e_priv->dma_buffer, buffer, length);
 416	address = dma_map_single(board->dev, e_priv->dma_buffer, length, DMA_TO_DEVICE);
 417	if (dma_mapping_error(board->dev,  address))
 418		dev_err(board->gpib_dev, "dma mapping error in dma write!\n");
 419	/* program dma controller */
 420	retval = fmh_gpib_config_dma(board, 1);
 421	if (retval)
 422		goto cleanup;
 423
 424	tx_desc = dmaengine_prep_slave_single(e_priv->dma_channel, address, length, DMA_MEM_TO_DEV,
 425					      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 426	if (!tx_desc) {
 427		dev_err(board->gpib_dev, "failed to allocate dma transmit descriptor\n");
 428		retval = -ENOMEM;
 429		goto cleanup;
 430	}
 431	tx_desc->callback = fmh_gpib_dma_callback;
 432	tx_desc->callback_param = board;
 433
 434	spin_lock_irqsave(&board->spinlock, flags);
 435	fifos_write(e_priv, length & fifo_xfer_counter_mask, FIFO_XFER_COUNTER_REG);
 436	fifos_write(e_priv, TX_FIFO_DMA_REQUEST_ENABLE | TX_FIFO_CLEAR, FIFO_CONTROL_STATUS_REG);
 437	nec7210_set_reg_bits(nec_priv, IMR1, HR_DOIE, 0);
 438	nec7210_set_reg_bits(nec_priv, IMR2, HR_DMAO, HR_DMAO);
 439
 440	dmaengine_submit(tx_desc);
 441	dma_async_issue_pending(e_priv->dma_channel);
 442	clear_bit(WRITE_READY_BN, &nec_priv->state);
 443	set_bit(DMA_WRITE_IN_PROGRESS_BN, &nec_priv->state);
 444
 445	spin_unlock_irqrestore(&board->spinlock, flags);
 446
 447	// suspend until message is sent
 448	if (wait_event_interruptible(board->wait,
 449				     fmh_gpib_all_bytes_are_sent(e_priv) ||
 450				     test_bit(BUS_ERROR_BN, &nec_priv->state) ||
 451				     test_bit(DEV_CLEAR_BN, &nec_priv->state) ||
 452				     test_bit(TIMO_NUM, &board->status)))
 453		retval = -ERESTARTSYS;
 454
 455	if (test_bit(TIMO_NUM, &board->status))
 456		retval = -ETIMEDOUT;
 457	if (test_and_clear_bit(DEV_CLEAR_BN, &nec_priv->state))
 458		retval = -EINTR;
 459	if (test_and_clear_bit(BUS_ERROR_BN, &nec_priv->state))
 460		retval = -EIO;
 461	// disable board's dma
 462	nec7210_set_reg_bits(nec_priv, IMR2, HR_DMAO, 0);
 463	fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG);
 464
 465	dmaengine_terminate_all(e_priv->dma_channel);
 466	// make sure fmh_gpib_dma_callback got called
 467	if (test_bit(DMA_WRITE_IN_PROGRESS_BN, &nec_priv->state))
 468		fmh_gpib_dma_callback(board);
 469
 470	*bytes_written = length - (fifos_read(e_priv, FIFO_XFER_COUNTER_REG) &
 471				   fifo_xfer_counter_mask);
 472	if (WARN_ON_ONCE(*bytes_written > length))
 473		return -EFAULT;
 474cleanup:
 475	dma_unmap_single(board->dev, address, length, DMA_TO_DEVICE);
 476	return retval;
 477}
 478
 479static int fmh_gpib_accel_write(struct gpib_board *board, u8 *buffer,
 480				size_t length, int send_eoi, size_t *bytes_written)
 481{
 482	struct fmh_priv *e_priv = board->private_data;
 483	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 484	size_t remainder = length;
 485	size_t transfer_size;
 486	ssize_t retval = 0;
 487	size_t dma_remainder = remainder;
 488
 489	if (!e_priv->dma_channel) {
 490		dev_err(board->gpib_dev, "No dma channel available, cannot do accel write.");
 491		return -ENXIO;
 492	}
 493
 494	*bytes_written = 0;
 495	if (length < 1)
 496		return 0;
 497
 498	smp_mb__before_atomic();
 499	clear_bit(DEV_CLEAR_BN, &nec_priv->state); // XXX FIXME
 500	smp_mb__after_atomic();
 501
 502	if (send_eoi)
 503		--dma_remainder;
 504
 505	while (dma_remainder > 0) {
 506		size_t num_bytes;
 507
 508		retval = wait_for_data_out_ready(board);
 509		if (retval < 0)
 510			break;
 511
 512		transfer_size = (e_priv->dma_buffer_size < dma_remainder) ?
 513			e_priv->dma_buffer_size : dma_remainder;
 514		retval = fmh_gpib_dma_write(board, buffer, transfer_size, &num_bytes);
 515		*bytes_written += num_bytes;
 516		if (retval < 0)
 517			break;
 518		dma_remainder -= num_bytes;
 519		remainder -= num_bytes;
 520		buffer += num_bytes;
 521		if (need_resched())
 522			schedule();
 523	}
 524	if (retval < 0)
 525		return retval;
 526	// handle sending of last byte with eoi
 527	if (send_eoi) {
 528		size_t num_bytes;
 529
 530		if (WARN_ON_ONCE(remainder != 1))
 531			return -EFAULT;
 532
 533		/*
 534		 * wait until we are sure we will be able to write the data byte
 535		 * into the chip before we send AUX_SEOI.  This prevents a timeout
 536		 * scenario where we send AUX_SEOI but then timeout without getting
 537		 * any bytes into the gpib chip.  This will result in the first byte
 538		 * of the next write having a spurious EOI set on the first byte.
 539		 */
 540		retval = wait_for_data_out_ready(board);
 541		if (retval < 0)
 542			return retval;
 543
 544		write_byte(nec_priv, AUX_SEOI, AUXMR);
 545		retval = fmh_gpib_dma_write(board, buffer, remainder, &num_bytes);
 546		*bytes_written += num_bytes;
 547		if (retval < 0)
 548			return retval;
 549		remainder -= num_bytes;
 550	}
 551	return 0;
 552}
 553
 554static int fmh_gpib_get_dma_residue(struct dma_chan *chan, dma_cookie_t cookie)
 555{
 556	struct dma_tx_state state;
 557	int result;
 558
 559	result = dmaengine_pause(chan);
 560	if (result < 0)	{
 561		pr_err("dma pause failed?\n");
 562		return result;
 563	}
 564	dmaengine_tx_status(chan, cookie, &state);
 565	/*
 566	 * dma330 hardware doesn't support resume, so dont call this
 567	 * method unless the dma transfer is done.
 568	 */
 569	return state.residue;
 570}
 571
 572static int wait_for_tx_fifo_half_empty(struct gpib_board *board)
 573{
 574	struct fmh_priv *e_priv = board->private_data;
 575	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 576	int retval = 0;
 577
 578	if (wait_event_interruptible(board->wait,
 579				     (test_bit(TACS_NUM, &board->status) &&
 580				      (fifos_read(e_priv, FIFO_CONTROL_STATUS_REG) &
 581				       TX_FIFO_HALF_EMPTY)) ||
 582				     test_bit(DEV_CLEAR_BN, &nec_priv->state) ||
 583				     test_bit(TIMO_NUM, &board->status)))
 584		retval = -ERESTARTSYS;
 585
 586	if (test_bit(TIMO_NUM, &board->status))
 587		retval = -ETIMEDOUT;
 588	if (test_and_clear_bit(DEV_CLEAR_BN, &nec_priv->state))
 589		retval = -EINTR;
 590
 591	return retval;
 592}
 593
 594/*
 595 * supports writing a chunk of data whose length must fit into the hardware'd xfer counter,
 596 * called in a loop by fmh_gpib_fifo_write()
 597 */
 598static int fmh_gpib_fifo_write_countable(struct gpib_board *board, u8 *buffer,
 599					 size_t length, int send_eoi, size_t *bytes_written)
 600{
 601	struct fmh_priv *e_priv = board->private_data;
 602	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 603	int retval = 0;
 604	unsigned int remainder;
 605
 606	*bytes_written = 0;
 607	if (WARN_ON_ONCE(length > fifo_xfer_counter_mask))
 608		return -EFAULT;
 609
 610	fifos_write(e_priv, length & fifo_xfer_counter_mask, FIFO_XFER_COUNTER_REG);
 611	fifos_write(e_priv, TX_FIFO_CLEAR, FIFO_CONTROL_STATUS_REG);
 612	nec7210_set_reg_bits(nec_priv, IMR1, HR_DOIE, 0);
 613	nec7210_set_reg_bits(nec_priv, IMR2, HR_DMAO, HR_DMAO);
 614
 615	remainder = length;
 616	while (remainder > 0) {
 617		int i;
 618
 619		fifos_write(e_priv, TX_FIFO_HALF_EMPTY_INTERRUPT_ENABLE, FIFO_CONTROL_STATUS_REG);
 620		retval = wait_for_tx_fifo_half_empty(board);
 621		if (retval < 0)
 622			goto cleanup;
 623
 624		for (i = 0; i < fmh_gpib_half_fifo_size(e_priv) && remainder > 0; ++i) {
 625			unsigned int data_value = *buffer;
 626
 627			if (send_eoi && remainder == 1)
 628				data_value |= FIFO_DATA_EOI_FLAG;
 629			fifos_write(e_priv, data_value, FIFO_DATA_REG);
 630			++buffer;
 631			--remainder;
 632		}
 633	}
 634
 635	// suspend until last byte is sent
 636	nec7210_set_reg_bits(nec_priv, IMR1, HR_DOIE, HR_DOIE);
 637	if (wait_event_interruptible(board->wait,
 638				     fmh_gpib_all_bytes_are_sent(e_priv) ||
 639				     test_bit(BUS_ERROR_BN, &nec_priv->state) ||
 640				     test_bit(DEV_CLEAR_BN, &nec_priv->state) ||
 641				     test_bit(TIMO_NUM, &board->status)))
 642		retval = -ERESTARTSYS;
 643
 644	if (test_bit(TIMO_NUM, &board->status))
 645		retval = -ETIMEDOUT;
 646	if (test_and_clear_bit(DEV_CLEAR_BN, &nec_priv->state))
 647		retval = -EINTR;
 648	if (test_and_clear_bit(BUS_ERROR_BN, &nec_priv->state))
 649		retval = -EIO;
 650
 651cleanup:
 652	nec7210_set_reg_bits(nec_priv, IMR1, HR_DOIE, 0);
 653	nec7210_set_reg_bits(nec_priv, IMR2, HR_DMAO, 0);
 654	fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG);
 655
 656	*bytes_written = length - (fifos_read(e_priv, FIFO_XFER_COUNTER_REG) &
 657				   fifo_xfer_counter_mask);
 658	if (WARN_ON_ONCE(*bytes_written > length))
 659		return -EFAULT;
 660
 661	return retval;
 662}
 663
 664static int fmh_gpib_fifo_write(struct gpib_board *board, u8 *buffer, size_t length,
 665			       int send_eoi, size_t *bytes_written)
 666{
 667	struct fmh_priv *e_priv = board->private_data;
 668	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 669	size_t remainder = length;
 670	size_t transfer_size;
 671	ssize_t retval = 0;
 672
 673	*bytes_written = 0;
 674	if (length < 1)
 675		return 0;
 676
 677	clear_bit(DEV_CLEAR_BN, &nec_priv->state); // XXX FIXME
 678
 679	while (remainder > 0) {
 680		size_t num_bytes;
 681		int last_pass;
 682
 683		retval = wait_for_data_out_ready(board);
 684		if (retval < 0)
 685			break;
 686
 687		if (fifo_xfer_counter_mask < remainder)	{
 688			// round transfer size to a multiple of half fifo size
 689			transfer_size = (fifo_xfer_counter_mask /
 690					 fmh_gpib_half_fifo_size(e_priv)) *
 691				fmh_gpib_half_fifo_size(e_priv);
 692			last_pass = 0;
 693		} else {
 694			transfer_size = remainder;
 695			last_pass = 1;
 696		}
 697		retval = fmh_gpib_fifo_write_countable(board, buffer, transfer_size,
 698						       last_pass && send_eoi, &num_bytes);
 699		*bytes_written += num_bytes;
 700		if (retval < 0)
 701			break;
 702		remainder -= num_bytes;
 703		buffer += num_bytes;
 704		if (need_resched())
 705			schedule();
 706	}
 707
 708	return retval;
 709}
 710
 711static int fmh_gpib_dma_read(struct gpib_board *board, u8 *buffer,
 712			     size_t length, int *end, size_t *bytes_read)
 713{
 714	struct fmh_priv *e_priv = board->private_data;
 715	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 716	int retval = 0;
 717	unsigned long flags;
 718	int residue;
 719	int wait_retval;
 720	dma_addr_t bus_address;
 721	struct dma_async_tx_descriptor *tx_desc;
 722	dma_cookie_t dma_cookie;
 723
 724	*bytes_read = 0;
 725	*end = 0;
 726	if (length == 0)
 727		return 0;
 728
 729	bus_address = dma_map_single(board->dev, e_priv->dma_buffer,
 730				     length, DMA_FROM_DEVICE);
 731	if (dma_mapping_error(board->dev, bus_address))
 732		dev_err(board->gpib_dev, "dma mapping error in dma read!");
 733
 734	/* program dma controller */
 735	retval = fmh_gpib_config_dma(board, 0);
 736	if (retval) {
 737		dma_unmap_single(board->dev, bus_address, length, DMA_FROM_DEVICE);
 738		return retval;
 739	}
 740	tx_desc = dmaengine_prep_slave_single(e_priv->dma_channel, bus_address,
 741					      length, DMA_DEV_TO_MEM,
 742					      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 743	if (!tx_desc)  {
 744		dev_err(board->gpib_dev, "failed to allocate dma transmit descriptor\n");
 745		dma_unmap_single(board->dev, bus_address, length, DMA_FROM_DEVICE);
 746		return -EIO;
 747	}
 748	tx_desc->callback = fmh_gpib_dma_callback;
 749	tx_desc->callback_param = board;
 750
 751	spin_lock_irqsave(&board->spinlock, flags);
 752	// enable nec7210 dma
 753	fifos_write(e_priv, length & fifo_xfer_counter_mask, FIFO_XFER_COUNTER_REG);
 754	fifos_write(e_priv, RX_FIFO_DMA_REQUEST_ENABLE | RX_FIFO_CLEAR, FIFO_CONTROL_STATUS_REG);
 755	nec7210_set_reg_bits(nec_priv, IMR1, HR_DIIE, 0);
 756	nec7210_set_reg_bits(nec_priv, IMR2, HR_DMAI, HR_DMAI);
 757
 758	dma_cookie = dmaengine_submit(tx_desc);
 759	dma_async_issue_pending(e_priv->dma_channel);
 760
 761	set_bit(DMA_READ_IN_PROGRESS_BN, &nec_priv->state);
 762
 763	spin_unlock_irqrestore(&board->spinlock, flags);
 764
 765	// wait for data to transfer
 766	wait_retval = wait_event_interruptible(board->wait,
 767					       test_bit(DMA_READ_IN_PROGRESS_BN, &nec_priv->state)
 768					       == 0 ||
 769					       test_bit(RECEIVED_END_BN, &nec_priv->state) ||
 770					       test_bit(DEV_CLEAR_BN, &nec_priv->state) ||
 771					       test_bit(TIMO_NUM, &board->status));
 772	if (wait_retval)
 773		retval = -ERESTARTSYS;
 774
 775	if (test_bit(TIMO_NUM, &board->status))
 776		retval = -ETIMEDOUT;
 777	if (test_bit(DEV_CLEAR_BN, &nec_priv->state))
 778		retval = -EINTR;
 779	// stop the dma transfer
 780	nec7210_set_reg_bits(nec_priv, IMR2, HR_DMAI, 0);
 781	fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG);
 782	/*
 783	 * give time for pl330 to transfer any in-flight data, since
 784	 * pl330 will throw it away when dmaengine_pause is called.
 785	 */
 786	usleep_range(10, 15);
 787	residue = fmh_gpib_get_dma_residue(e_priv->dma_channel, dma_cookie);
 788	if (WARN_ON_ONCE(residue > length || residue < 0))
 789		return -EFAULT;
 790	*bytes_read += length - residue;
 791	dmaengine_terminate_all(e_priv->dma_channel);
 792	// make sure fmh_gpib_dma_callback got called
 793	if (test_bit(DMA_READ_IN_PROGRESS_BN, &nec_priv->state))
 794		fmh_gpib_dma_callback(board);
 795
 796	dma_unmap_single(board->dev, bus_address, length, DMA_FROM_DEVICE);
 797	memcpy(buffer, e_priv->dma_buffer, *bytes_read);
 798
 799	/* Manually read any dregs out of fifo. */
 800	while ((fifos_read(e_priv, FIFO_CONTROL_STATUS_REG) & RX_FIFO_EMPTY) == 0) {
 801		if ((*bytes_read) >= length) {
 802			dev_err(board->dev, "unexpected extra bytes in rx fifo, discarding!  bytes_read=%d length=%d residue=%d\n",
 803				(int)(*bytes_read), (int)length, (int)residue);
 804			break;
 805		}
 806		buffer[(*bytes_read)++] = fifos_read(e_priv, FIFO_DATA_REG) & fifo_data_mask;
 807	}
 808
 809	/*
 810	 * If we got an end interrupt, figure out if it was
 811	 * associated with the last byte we dma'd or with a
 812	 * byte still sitting on the cb7210.
 813	 */
 814	spin_lock_irqsave(&board->spinlock, flags);
 815	if (*bytes_read > 0 && test_bit(READ_READY_BN, &nec_priv->state) == 0) {
 816		/*
 817		 * If there is no byte sitting on the cb7210 and we
 818		 * saw an end, we need to deal with it now
 819		 */
 820		if (test_and_clear_bit(RECEIVED_END_BN, &nec_priv->state))
 821			*end = 1;
 822	}
 823	spin_unlock_irqrestore(&board->spinlock, flags);
 824
 825	return retval;
 826}
 827
 828static void fmh_gpib_release_rfd_holdoff(struct gpib_board *board, struct fmh_priv *e_priv)
 829{
 830	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 831	unsigned int ext_status_1;
 832	unsigned long flags;
 833
 834	spin_lock_irqsave(&board->spinlock, flags);
 835
 836	ext_status_1 = read_byte(nec_priv, EXT_STATUS_1_REG);
 837
 838	/*
 839	 * if there is an end byte sitting on the chip, don't release
 840	 * holdoff.  We want it left set after we read out the end
 841	 * byte.
 842	 */
 843	if ((ext_status_1 & (DATA_IN_STATUS_BIT | END_STATUS_BIT)) !=
 844	    (DATA_IN_STATUS_BIT | END_STATUS_BIT))	{
 845		if (ext_status_1 & RFD_HOLDOFF_STATUS_BIT)
 846			write_byte(nec_priv, AUX_FH, AUXMR);
 847
 848		/*
 849		 * Check if an end byte raced in before we executed the AUX_FH command.
 850		 * If it did, we want to make sure the rfd holdoff is in effect.  The end
 851		 * byte can arrive since
 852		 * AUX_RFD_HOLDOFF_ASAP doesn't immediately force the acceptor handshake
 853		 * to leave ACRS.
 854		 */
 855		if ((read_byte(nec_priv, EXT_STATUS_1_REG) &
 856		     (RFD_HOLDOFF_STATUS_BIT | DATA_IN_STATUS_BIT | END_STATUS_BIT)) ==
 857		    (DATA_IN_STATUS_BIT | END_STATUS_BIT)) {
 858			write_byte(nec_priv, AUX_RFD_HOLDOFF_ASAP, AUXMR);
 859			set_bit(RFD_HOLDOFF_BN, &nec_priv->state);
 860		} else {
 861			clear_bit(RFD_HOLDOFF_BN, &nec_priv->state);
 862		}
 863	}
 864	spin_unlock_irqrestore(&board->spinlock, flags);
 865}
 866
 867static int fmh_gpib_accel_read(struct gpib_board *board, u8 *buffer, size_t length,
 868			       int *end, size_t *bytes_read)
 869{
 870	struct fmh_priv *e_priv = board->private_data;
 871	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 872	size_t remain = length;
 873	size_t transfer_size;
 874	int retval = 0;
 875	size_t dma_nbytes;
 876	unsigned long flags;
 877
 878	smp_mb__before_atomic();
 879	clear_bit(DEV_CLEAR_BN, &nec_priv->state); // XXX FIXME
 880	smp_mb__after_atomic();
 881	*end = 0;
 882	*bytes_read = 0;
 883
 884	retval = wait_for_read(board);
 885	if (retval < 0)
 886		return retval;
 887
 888	fmh_gpib_release_rfd_holdoff(board, e_priv);
 889	while (remain > 0) {
 890		transfer_size = (e_priv->dma_buffer_size < remain) ?
 891			e_priv->dma_buffer_size : remain;
 892		retval = fmh_gpib_dma_read(board, buffer, transfer_size, end, &dma_nbytes);
 893		remain -= dma_nbytes;
 894		buffer += dma_nbytes;
 895		*bytes_read += dma_nbytes;
 896		if (*end)
 897			break;
 898		if (retval < 0)
 899			break;
 900		if (need_resched())
 901			schedule();
 902	}
 903
 904	spin_lock_irqsave(&board->spinlock, flags);
 905	if (test_bit(RFD_HOLDOFF_BN, &nec_priv->state) == 0) {
 906		write_byte(nec_priv, AUX_RFD_HOLDOFF_ASAP, AUXMR);
 907		set_bit(RFD_HOLDOFF_BN, &nec_priv->state);
 908	}
 909	spin_unlock_irqrestore(&board->spinlock, flags);
 910
 911	return retval;
 912}
 913
 914/*
 915 * Read a chunk of data whose length is within the limits of the hardware's
 916 * xfer counter.  Called in a loop from fmh_gpib_fifo_read().
 917 */
 918static int fmh_gpib_fifo_read_countable(struct gpib_board *board, u8 *buffer,
 919					size_t length, int *end, size_t *bytes_read)
 920{
 921	struct fmh_priv *e_priv = board->private_data;
 922	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 923	int retval = 0;
 924
 925	*bytes_read = 0;
 926	*end = 0;
 927	if (length == 0)
 928		return 0;
 929
 930	fifos_write(e_priv, length & fifo_xfer_counter_mask, FIFO_XFER_COUNTER_REG);
 931	fifos_write(e_priv, RX_FIFO_CLEAR, FIFO_CONTROL_STATUS_REG);
 932	nec7210_set_reg_bits(nec_priv, IMR1, HR_DIIE, 0);
 933	nec7210_set_reg_bits(nec_priv, IMR2, HR_DMAI, HR_DMAI);
 934
 935	while (*bytes_read < length && *end == 0) {
 936		int i;
 937
 938		fifos_write(e_priv, RX_FIFO_HALF_FULL_INTERRUPT_ENABLE, FIFO_CONTROL_STATUS_REG);
 939		retval = wait_for_rx_fifo_half_full_or_end(board);
 940		if (retval < 0)
 941			goto cleanup;
 942
 943		for (i = 0; i < fmh_gpib_half_fifo_size(e_priv) && *end == 0; ++i) {
 944			unsigned int data_value;
 945
 946			data_value = fifos_read(e_priv, FIFO_DATA_REG);
 947			buffer[(*bytes_read)++] = data_value & fifo_data_mask;
 948			if (data_value & FIFO_DATA_EOI_FLAG)
 949				*end = 1;
 950		}
 951	}
 952
 953cleanup:
 954	// stop the transfer
 955	nec7210_set_reg_bits(nec_priv, IMR2, HR_DMAI, 0);
 956	fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG);
 957
 958	/* Manually read any dregs out of fifo. */
 959	while ((fifos_read(e_priv, FIFO_CONTROL_STATUS_REG) & RX_FIFO_EMPTY) == 0) {
 960		unsigned int data_value;
 961
 962		if ((*bytes_read) >= length) {
 963			dev_err(board->dev, "unexpected extra bytes in rx fifo, discarding!  bytes_read=%d length=%d\n",
 964				(int)(*bytes_read), (int)length);
 965			break;
 966		}
 967		data_value = fifos_read(e_priv, FIFO_DATA_REG);
 968		buffer[(*bytes_read)++] = data_value & fifo_data_mask;
 969		if (data_value & FIFO_DATA_EOI_FLAG)
 970			*end = 1;
 971	}
 972
 973	return retval;
 974}
 975
 976static int fmh_gpib_fifo_read(struct gpib_board *board, u8 *buffer, size_t length,
 977			      int *end, size_t *bytes_read)
 978{
 979	struct fmh_priv *e_priv = board->private_data;
 980	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
 981	size_t remain = length;
 982	size_t transfer_size;
 983	int retval = 0;
 984	size_t nbytes;
 985	unsigned long flags;
 986
 987	clear_bit(DEV_CLEAR_BN, &nec_priv->state); // XXX FIXME
 988	*end = 0;
 989	*bytes_read = 0;
 990
 991	/*
 992	 * Do a little prep with data in interrupt so that following wait_for_read()
 993	 * will wake up if a data byte is received.
 994	 */
 995	nec7210_set_reg_bits(nec_priv, IMR1, HR_DIIE, HR_DIIE);
 996	fmh_gpib_interrupt(0, board);
 997
 998	retval = wait_for_read(board);
 999	if (retval < 0)
1000		return retval;
1001
1002	fmh_gpib_release_rfd_holdoff(board, e_priv);
1003	while (remain > 0) {
1004		if (fifo_xfer_counter_mask < remain) {
1005			// round transfer size to a multiple of half fifo size
1006			transfer_size = (fifo_xfer_counter_mask /
1007					 fmh_gpib_half_fifo_size(e_priv)) *
1008				fmh_gpib_half_fifo_size(e_priv);
1009		} else {
1010			transfer_size = remain;
1011		}
1012		retval = fmh_gpib_fifo_read_countable(board, buffer, transfer_size, end, &nbytes);
1013		remain -= nbytes;
1014		buffer += nbytes;
1015		*bytes_read += nbytes;
1016		if (*end)
1017			break;
1018		if (retval < 0)
1019			break;
1020		if (need_resched())
1021			schedule();
1022	}
1023
1024	if (*end == 0)	{
1025		spin_lock_irqsave(&board->spinlock, flags);
1026		write_byte(nec_priv, AUX_RFD_HOLDOFF_ASAP, AUXMR);
1027		set_bit(RFD_HOLDOFF_BN, &nec_priv->state);
1028		spin_unlock_irqrestore(&board->spinlock, flags);
1029	}
1030
1031	return retval;
1032}
1033
1034static struct gpib_interface fmh_gpib_unaccel_interface = {
1035	.name = "fmh_gpib_unaccel",
1036	.attach = fmh_gpib_attach_holdoff_all,
1037	.detach = fmh_gpib_detach,
1038	.read = fmh_gpib_read,
1039	.write = fmh_gpib_write,
1040	.command = fmh_gpib_command,
1041	.take_control = fmh_gpib_take_control,
1042	.go_to_standby = fmh_gpib_go_to_standby,
1043	.request_system_control = fmh_gpib_request_system_control,
1044	.interface_clear = fmh_gpib_interface_clear,
1045	.remote_enable = fmh_gpib_remote_enable,
1046	.enable_eos = fmh_gpib_enable_eos,
1047	.disable_eos = fmh_gpib_disable_eos,
1048	.parallel_poll = fmh_gpib_parallel_poll,
1049	.parallel_poll_configure = fmh_gpib_parallel_poll_configure,
1050	.parallel_poll_response = fmh_gpib_parallel_poll_response,
1051	.local_parallel_poll_mode = fmh_gpib_local_parallel_poll_mode,
1052	.line_status = fmh_gpib_line_status,
1053	.update_status = fmh_gpib_update_status,
1054	.primary_address = fmh_gpib_primary_address,
1055	.secondary_address = fmh_gpib_secondary_address,
1056	.serial_poll_response2 = fmh_gpib_serial_poll_response2,
1057	.serial_poll_status = fmh_gpib_serial_poll_status,
1058	.t1_delay = fmh_gpib_t1_delay,
1059	.return_to_local = fmh_gpib_return_to_local,
1060};
1061
1062static struct gpib_interface fmh_gpib_interface = {
1063	.name = "fmh_gpib",
1064	.attach = fmh_gpib_attach_holdoff_end,
1065	.detach = fmh_gpib_detach,
1066	.read = fmh_gpib_accel_read,
1067	.write = fmh_gpib_accel_write,
1068	.command = fmh_gpib_command,
1069	.take_control = fmh_gpib_take_control,
1070	.go_to_standby = fmh_gpib_go_to_standby,
1071	.request_system_control = fmh_gpib_request_system_control,
1072	.interface_clear = fmh_gpib_interface_clear,
1073	.remote_enable = fmh_gpib_remote_enable,
1074	.enable_eos = fmh_gpib_enable_eos,
1075	.disable_eos = fmh_gpib_disable_eos,
1076	.parallel_poll = fmh_gpib_parallel_poll,
1077	.parallel_poll_configure = fmh_gpib_parallel_poll_configure,
1078	.parallel_poll_response = fmh_gpib_parallel_poll_response,
1079	.local_parallel_poll_mode = fmh_gpib_local_parallel_poll_mode,
1080	.line_status = fmh_gpib_line_status,
1081	.update_status = fmh_gpib_update_status,
1082	.primary_address = fmh_gpib_primary_address,
1083	.secondary_address = fmh_gpib_secondary_address,
1084	.serial_poll_response2 = fmh_gpib_serial_poll_response2,
1085	.serial_poll_status = fmh_gpib_serial_poll_status,
1086	.t1_delay = fmh_gpib_t1_delay,
1087	.return_to_local = fmh_gpib_return_to_local,
1088};
1089
1090static struct gpib_interface fmh_gpib_pci_interface = {
1091	.name = "fmh_gpib_pci",
1092	.attach = fmh_gpib_pci_attach_holdoff_end,
1093	.detach = fmh_gpib_pci_detach,
1094	.read = fmh_gpib_fifo_read,
1095	.write = fmh_gpib_fifo_write,
1096	.command = fmh_gpib_command,
1097	.take_control = fmh_gpib_take_control,
1098	.go_to_standby = fmh_gpib_go_to_standby,
1099	.request_system_control = fmh_gpib_request_system_control,
1100	.interface_clear = fmh_gpib_interface_clear,
1101	.remote_enable = fmh_gpib_remote_enable,
1102	.enable_eos = fmh_gpib_enable_eos,
1103	.disable_eos = fmh_gpib_disable_eos,
1104	.parallel_poll = fmh_gpib_parallel_poll,
1105	.parallel_poll_configure = fmh_gpib_parallel_poll_configure,
1106	.parallel_poll_response = fmh_gpib_parallel_poll_response,
1107	.local_parallel_poll_mode = fmh_gpib_local_parallel_poll_mode,
1108	.line_status = fmh_gpib_line_status,
1109	.update_status = fmh_gpib_update_status,
1110	.primary_address = fmh_gpib_primary_address,
1111	.secondary_address = fmh_gpib_secondary_address,
1112	.serial_poll_response2 = fmh_gpib_serial_poll_response2,
1113	.serial_poll_status = fmh_gpib_serial_poll_status,
1114	.t1_delay = fmh_gpib_t1_delay,
1115	.return_to_local = fmh_gpib_return_to_local,
1116};
1117
1118static struct gpib_interface fmh_gpib_pci_unaccel_interface = {
1119	.name = "fmh_gpib_pci_unaccel",
1120	.attach = fmh_gpib_pci_attach_holdoff_all,
1121	.detach = fmh_gpib_pci_detach,
1122	.read = fmh_gpib_read,
1123	.write = fmh_gpib_write,
1124	.command = fmh_gpib_command,
1125	.take_control = fmh_gpib_take_control,
1126	.go_to_standby = fmh_gpib_go_to_standby,
1127	.request_system_control = fmh_gpib_request_system_control,
1128	.interface_clear = fmh_gpib_interface_clear,
1129	.remote_enable = fmh_gpib_remote_enable,
1130	.enable_eos = fmh_gpib_enable_eos,
1131	.disable_eos = fmh_gpib_disable_eos,
1132	.parallel_poll = fmh_gpib_parallel_poll,
1133	.parallel_poll_configure = fmh_gpib_parallel_poll_configure,
1134	.parallel_poll_response = fmh_gpib_parallel_poll_response,
1135	.local_parallel_poll_mode = fmh_gpib_local_parallel_poll_mode,
1136	.line_status = fmh_gpib_line_status,
1137	.update_status = fmh_gpib_update_status,
1138	.primary_address = fmh_gpib_primary_address,
1139	.secondary_address = fmh_gpib_secondary_address,
1140	.serial_poll_response2 = fmh_gpib_serial_poll_response2,
1141	.serial_poll_status = fmh_gpib_serial_poll_status,
1142	.t1_delay = fmh_gpib_t1_delay,
1143	.return_to_local = fmh_gpib_return_to_local,
1144};
1145
1146irqreturn_t fmh_gpib_internal_interrupt(struct gpib_board *board)
1147{
1148	unsigned int status0, status1, status2, ext_status_1, fifo_status;
1149	struct fmh_priv *priv = board->private_data;
1150	struct nec7210_priv *nec_priv = &priv->nec7210_priv;
1151	int retval = IRQ_NONE;
1152
1153	status0 = read_byte(nec_priv, ISR0_IMR0_REG);
1154	status1 = read_byte(nec_priv, ISR1);
1155	status2 = read_byte(nec_priv, ISR2);
1156	fifo_status = fifos_read(priv, FIFO_CONTROL_STATUS_REG);
1157
1158	if (status0 & IFC_INTERRUPT_BIT) {
1159		push_gpib_event(board, EVENT_IFC);
1160		retval = IRQ_HANDLED;
1161	}
1162
1163	if (nec7210_interrupt_have_status(board, nec_priv, status1, status2) == IRQ_HANDLED)
1164		retval = IRQ_HANDLED;
1165
1166	ext_status_1 = read_byte(nec_priv, EXT_STATUS_1_REG);
1167
1168	if (ext_status_1 & DATA_IN_STATUS_BIT)
1169		set_bit(READ_READY_BN, &nec_priv->state);
1170	else
1171		clear_bit(READ_READY_BN, &nec_priv->state);
1172
1173	if (ext_status_1 & DATA_OUT_STATUS_BIT)
1174		set_bit(WRITE_READY_BN, &nec_priv->state);
1175	else
1176		clear_bit(WRITE_READY_BN, &nec_priv->state);
1177
1178	if (ext_status_1 & COMMAND_OUT_STATUS_BIT)
1179		set_bit(COMMAND_READY_BN, &nec_priv->state);
1180	else
1181		clear_bit(COMMAND_READY_BN, &nec_priv->state);
1182
1183	if (ext_status_1 & RFD_HOLDOFF_STATUS_BIT)
1184		set_bit(RFD_HOLDOFF_BN, &nec_priv->state);
1185	else
1186		clear_bit(RFD_HOLDOFF_BN, &nec_priv->state);
1187
1188	if (ext_status_1 & END_STATUS_BIT) {
1189		/*
1190		 * only set RECEIVED_END while there is still a data
1191		 * byte sitting in the chip, to avoid spuriously
1192		 * setting it multiple times after it has been cleared
1193		 * during a read.
1194		 */
1195		if (ext_status_1 & DATA_IN_STATUS_BIT)
1196			set_bit(RECEIVED_END_BN, &nec_priv->state);
1197	} else {
1198		clear_bit(RECEIVED_END_BN, &nec_priv->state);
1199	}
1200
1201	if ((fifo_status & TX_FIFO_HALF_EMPTY_INTERRUPT_IS_ENABLED) &&
1202	    (fifo_status & TX_FIFO_HALF_EMPTY)) {
1203		/*
1204		 * We really only want to clear the
1205		 * TX_FIFO_HALF_EMPTY_INTERRUPT_ENABLE bit in the
1206		 * FIFO_CONTROL_STATUS_REG.  Since we are not being
1207		 * careful, this also has a side effect of disabling
1208		 * DMA requests and the RX fifo interrupt.  That is
1209		 * fine though, since they should never be in use at
1210		 * the same time as the TX fifo interrupt.
1211		 */
1212		fifos_write(priv, 0x0, FIFO_CONTROL_STATUS_REG);
1213		retval = IRQ_HANDLED;
1214	}
1215
1216	if ((fifo_status & RX_FIFO_HALF_FULL_INTERRUPT_IS_ENABLED) &&
1217	    (fifo_status & RX_FIFO_HALF_FULL)) {
1218		/*
1219		 * We really only want to clear the
1220		 * RX_FIFO_HALF_FULL_INTERRUPT_ENABLE bit in the
1221		 * FIFO_CONTROL_STATUS_REG.  Since we are not being
1222		 * careful, this also has a side effect of disabling
1223		 * DMA requests and the TX fifo interrupt.  That is
1224		 * fine though, since they should never be in use at
1225		 * the same time as the RX fifo interrupt.
1226		 */
1227		fifos_write(priv, 0x0, FIFO_CONTROL_STATUS_REG);
1228		retval = IRQ_HANDLED;
1229	}
1230
1231	if (retval == IRQ_HANDLED)
1232		wake_up_interruptible(&board->wait);
1233
1234	return retval;
1235}
1236
1237irqreturn_t fmh_gpib_interrupt(int irq, void *arg)
1238{
1239	struct gpib_board *board = arg;
1240	unsigned long flags;
1241	irqreturn_t retval;
1242
1243	spin_lock_irqsave(&board->spinlock, flags);
1244	retval = fmh_gpib_internal_interrupt(board);
1245	spin_unlock_irqrestore(&board->spinlock, flags);
1246	return retval;
1247}
1248
1249static int fmh_gpib_allocate_private(struct gpib_board *board)
1250{
1251	struct fmh_priv *priv;
1252
1253	board->private_data = kmalloc(sizeof(struct fmh_priv), GFP_KERNEL);
1254	if (!board->private_data)
1255		return -ENOMEM;
1256	priv = board->private_data;
1257	memset(priv, 0, sizeof(struct fmh_priv));
1258	init_nec7210_private(&priv->nec7210_priv);
1259	priv->dma_buffer_size = 0x800;
1260	priv->dma_buffer = kmalloc(priv->dma_buffer_size, GFP_KERNEL);
1261	if (!priv->dma_buffer)
1262		return -ENOMEM;
1263	return 0;
1264}
1265
1266static void fmh_gpib_generic_detach(struct gpib_board *board)
1267{
1268	if (board->private_data) {
1269		struct fmh_priv *e_priv = board->private_data;
1270
1271		kfree(e_priv->dma_buffer);
1272		kfree(board->private_data);
1273		board->private_data = NULL;
1274	}
1275	if (board->dev)
1276		dev_set_drvdata(board->dev, NULL);
1277}
1278
1279// generic part of attach functions
1280static int fmh_gpib_generic_attach(struct gpib_board *board)
1281{
1282	struct fmh_priv *e_priv;
1283	struct nec7210_priv *nec_priv;
1284	int retval;
1285
1286	board->status = 0;
1287
1288	retval = fmh_gpib_allocate_private(board);
1289	if (retval < 0)
1290		return retval;
1291	e_priv = board->private_data;
1292	nec_priv = &e_priv->nec7210_priv;
1293	nec_priv->read_byte = gpib_cs_read_byte;
1294	nec_priv->write_byte = gpib_cs_write_byte;
1295	nec_priv->offset = 1;
1296	nec_priv->type = CB7210;
1297	return 0;
1298}
1299
1300static int fmh_gpib_config_dma(struct gpib_board *board, int output)
1301{
1302	struct fmh_priv *e_priv = board->private_data;
1303	struct dma_slave_config config;
1304
1305	config.device_fc = true;
1306
1307	if (e_priv->dma_burst_length < 1) {
1308		config.src_maxburst = 1;
1309		config.dst_maxburst = 1;
1310	} else {
1311		config.src_maxburst = e_priv->dma_burst_length;
1312		config.dst_maxburst = e_priv->dma_burst_length;
1313	}
1314
1315	config.src_addr_width = 1;
1316	config.dst_addr_width = 1;
1317
1318	if (output) {
1319		config.direction = DMA_MEM_TO_DEV;
1320		config.src_addr = 0;
1321		config.dst_addr = e_priv->dma_port_res->start + FIFO_DATA_REG * fifo_reg_offset;
1322	} else {
1323		config.direction = DMA_DEV_TO_MEM;
1324		config.src_addr = e_priv->dma_port_res->start + FIFO_DATA_REG * fifo_reg_offset;
1325		config.dst_addr = 0;
1326	}
1327	return dmaengine_slave_config(e_priv->dma_channel, &config);
1328}
1329
1330static int fmh_gpib_init(struct fmh_priv *e_priv, struct gpib_board *board, int handshake_mode)
1331{
1332	struct nec7210_priv *nec_priv = &e_priv->nec7210_priv;
1333	unsigned long flags;
1334	unsigned int fifo_status_bits;
1335
1336	fifos_write(e_priv, RX_FIFO_CLEAR | TX_FIFO_CLEAR, FIFO_CONTROL_STATUS_REG);
1337
1338	nec7210_board_reset(nec_priv, board);
1339	write_byte(nec_priv, AUX_LO_SPEED, AUXMR);
1340	nec7210_set_handshake_mode(board, nec_priv, handshake_mode);
1341
1342	/* Hueristically check if hardware supports fifo half full/empty interrupts */
1343	fifo_status_bits = fifos_read(e_priv, FIFO_CONTROL_STATUS_REG);
1344	e_priv->supports_fifo_interrupts = (fifo_status_bits & TX_FIFO_EMPTY) &&
1345		(fifo_status_bits & TX_FIFO_HALF_EMPTY);
1346
1347	nec7210_board_online(nec_priv, board);
1348
1349	write_byte(nec_priv, IFC_INTERRUPT_ENABLE_BIT | ATN_INTERRUPT_ENABLE_BIT, ISR0_IMR0_REG);
1350
1351	spin_lock_irqsave(&board->spinlock, flags);
1352	write_byte(nec_priv, AUX_RFD_HOLDOFF_ASAP, AUXMR);
1353	set_bit(RFD_HOLDOFF_BN, &nec_priv->state);
1354	spin_unlock_irqrestore(&board->spinlock, flags);
1355	return 0;
1356}
1357
1358/* Match callback for driver_find_device */
1359static int fmh_gpib_device_match(struct device *dev, const void *data)
1360{
1361	const struct gpib_board_config *config = data;
1362
1363	if (dev_get_drvdata(dev))
1364		return 0;
1365
1366	if (gpib_match_device_path(dev, config->device_path) == 0)
1367		return 0;
1368
1369	// driver doesn't support selection by serial number
1370	if (config->serial_number)
1371		return 0;
1372
1373	dev_dbg(dev, "matched: %s\n", of_node_full_name(dev_of_node((dev))));
1374	return 1;
1375}
1376
1377static int fmh_gpib_attach_impl(struct gpib_board *board, const struct gpib_board_config *config,
1378				unsigned int handshake_mode, int acquire_dma)
1379{
1380	struct fmh_priv *e_priv;
1381	struct nec7210_priv *nec_priv;
1382	int retval;
1383	int irq;
1384	struct resource *res;
1385	struct platform_device *pdev;
1386
1387	board->dev = driver_find_device(&fmh_gpib_platform_driver.driver,
1388					NULL, (const void *)config, &fmh_gpib_device_match);
1389	if (!board->dev)	{
1390		dev_err(board->gpib_dev, "No matching fmh_gpib_core device was found, attach failed.");
1391		return -ENODEV;
1392	}
1393	// currently only used to mark the device as already attached
1394	dev_set_drvdata(board->dev, board);
1395	pdev = to_platform_device(board->dev);
1396
1397	retval = fmh_gpib_generic_attach(board);
1398	if (retval)
1399		return retval;
1400
1401	e_priv = board->private_data;
1402	nec_priv = &e_priv->nec7210_priv;
1403
1404	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpib_control_status");
1405	if (!res) {
1406		dev_err(board->dev, "Unable to locate mmio resource\n");
1407		return -ENODEV;
1408	}
1409
1410	if (request_mem_region(res->start,
1411			       resource_size(res),
1412			       pdev->name) == NULL) {
1413		dev_err(board->dev, "cannot claim registers\n");
1414		return -ENXIO;
1415	}
1416	e_priv->gpib_iomem_res = res;
1417
1418	nec_priv->mmiobase = ioremap(e_priv->gpib_iomem_res->start,
1419				     resource_size(e_priv->gpib_iomem_res));
1420	if (!nec_priv->mmiobase) {
1421		dev_err(board->dev, "Could not map I/O memory\n");
1422		return -ENOMEM;
1423	}
1424	dev_dbg(board->dev, "iobase %pr remapped to %p\n",
1425		e_priv->gpib_iomem_res, nec_priv->mmiobase);
1426
1427	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma_fifos");
1428	if (!res) {
1429		dev_err(board->dev, "Unable to locate mmio resource for gpib dma port\n");
1430		return -ENODEV;
1431	}
1432	if (request_mem_region(res->start,
1433			       resource_size(res),
1434			       pdev->name) == NULL) {
1435		dev_err(board->dev, "cannot claim registers\n");
1436		return -ENXIO;
1437	}
1438	e_priv->dma_port_res = res;
1439	e_priv->fifo_base = ioremap(e_priv->dma_port_res->start,
1440				    resource_size(e_priv->dma_port_res));
1441	if (!e_priv->fifo_base) {
1442		dev_err(board->dev, "Could not map I/O memory for fifos\n");
1443		return -ENOMEM;
1444	}
1445	dev_dbg(board->dev, "dma fifos 0x%lx remapped to %p, length=%ld\n",
1446		(unsigned long)e_priv->dma_port_res->start, e_priv->fifo_base,
1447		(unsigned long)resource_size(e_priv->dma_port_res));
1448
1449	irq = platform_get_irq(pdev, 0);
1450	if (irq < 0)
1451		return -EBUSY;
1452	retval = request_irq(irq, fmh_gpib_interrupt, IRQF_SHARED, pdev->name, board);
1453	if (retval) {
1454		dev_err(board->dev,
1455			"cannot register interrupt handler err=%d\n",
1456			retval);
1457		return retval;
1458	}
1459	e_priv->irq = irq;
1460
1461	if (acquire_dma) {
1462		e_priv->dma_channel = dma_request_slave_channel(board->dev, "rxtx");
1463		if (!e_priv->dma_channel) {
1464			dev_err(board->dev, "failed to acquire dma channel \"rxtx\".\n");
1465			return -EIO;
1466		}
1467	}
1468	/*
1469	 * in the future we might want to know the half-fifo size
1470	 * (dma_burst_length) even when not using dma, so go ahead an
1471	 * initialize it unconditionally.
1472	 */
1473	e_priv->dma_burst_length = fifos_read(e_priv, FIFO_MAX_BURST_LENGTH_REG) &
1474		fifo_max_burst_length_mask;
1475
1476	return fmh_gpib_init(e_priv, board, handshake_mode);
1477}
1478
1479int fmh_gpib_attach_holdoff_all(struct gpib_board *board, const struct gpib_board_config *config)
1480{
1481	return fmh_gpib_attach_impl(board, config, HR_HLDA, 0);
1482}
1483
1484int fmh_gpib_attach_holdoff_end(struct gpib_board *board, const struct gpib_board_config *config)
1485{
1486	return fmh_gpib_attach_impl(board, config, HR_HLDE, 1);
1487}
1488
1489void fmh_gpib_detach(struct gpib_board *board)
1490{
1491	struct fmh_priv *e_priv = board->private_data;
1492	struct nec7210_priv *nec_priv;
1493
1494	if (e_priv) {
1495		if (e_priv->dma_channel)
1496			dma_release_channel(e_priv->dma_channel);
1497		nec_priv = &e_priv->nec7210_priv;
1498
1499		if (e_priv->irq)
1500			free_irq(e_priv->irq, board);
1501		if (e_priv->fifo_base)
1502			fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG);
1503		if (nec_priv->mmiobase) {
1504			write_byte(nec_priv, 0, ISR0_IMR0_REG);
1505			nec7210_board_reset(nec_priv, board);
1506		}
1507		if (e_priv->fifo_base)
1508			iounmap(e_priv->fifo_base);
1509		if (nec_priv->mmiobase)
1510			iounmap(nec_priv->mmiobase);
1511		if (e_priv->dma_port_res) {
1512			release_mem_region(e_priv->dma_port_res->start,
1513					   resource_size(e_priv->dma_port_res));
1514		}
1515		if (e_priv->gpib_iomem_res)
1516			release_mem_region(e_priv->gpib_iomem_res->start,
1517					   resource_size(e_priv->gpib_iomem_res));
1518	}
1519	fmh_gpib_generic_detach(board);
1520
1521	if (board->dev) {
1522		put_device(board->dev);
1523		board->dev = NULL;
1524	}
1525}
1526
1527static int fmh_gpib_pci_attach_impl(struct gpib_board *board,
1528				    const struct gpib_board_config *config,
1529				    unsigned int handshake_mode)
1530{
1531	struct fmh_priv *e_priv;
1532	struct nec7210_priv *nec_priv;
1533	int retval;
1534	struct pci_dev *pci_device;
1535
1536	retval = fmh_gpib_generic_attach(board);
1537	if (retval)
1538		return retval;
1539
1540	e_priv = board->private_data;
1541	nec_priv = &e_priv->nec7210_priv;
1542
1543	// find board
1544	pci_device = gpib_pci_get_device(config, BOGUS_PCI_VENDOR_ID_FLUKE,
1545					 BOGUS_PCI_DEVICE_ID_FLUKE_BLADERUNNER, NULL);
1546	if (!pci_device)	{
1547		dev_err(board->gpib_dev, "No matching fmh_gpib_core pci device was found, attach failed.");
1548		return -ENODEV;
1549	}
1550	board->dev = &pci_device->dev;
1551
1552	// bladerunner prototype has offset of 4 between gpib control/status registers
1553	nec_priv->offset = 4;
1554
1555	if (pci_enable_device(pci_device)) {
1556		dev_err(board->dev, "error enabling pci device\n");
1557		return -EIO;
1558	}
1559	if (pci_request_regions(pci_device, KBUILD_MODNAME)) {
1560		dev_err(board->dev, "pci_request_regions failed\n");
1561		return -EIO;
1562	}
1563	e_priv->gpib_iomem_res = &pci_device->resource[gpib_control_status_pci_resource_index];
1564	e_priv->dma_port_res =	&pci_device->resource[gpib_fifo_pci_resource_index];
1565
1566	nec_priv->mmiobase = ioremap(pci_resource_start(pci_device,
1567							gpib_control_status_pci_resource_index),
1568				     pci_resource_len(pci_device,
1569						      gpib_control_status_pci_resource_index));
1570	dev_dbg(board->dev, "base address for gpib control/status registers remapped to 0x%p\n",
1571		nec_priv->mmiobase);
1572
1573	if (e_priv->dma_port_res->flags & IORESOURCE_MEM) {
1574		e_priv->fifo_base = ioremap(pci_resource_start(pci_device,
1575							       gpib_fifo_pci_resource_index),
1576					    pci_resource_len(pci_device,
1577							     gpib_fifo_pci_resource_index));
1578		dev_dbg(board->dev, "base address for gpib fifo registers remapped to 0x%p\n",
1579			e_priv->fifo_base);
1580	} else {
1581		e_priv->fifo_base = NULL;
1582		dev_dbg(board->dev, "hardware has no gpib fifo registers.\n");
1583	}
1584
1585	if (pci_device->irq) {
1586		retval = request_irq(pci_device->irq, fmh_gpib_interrupt, IRQF_SHARED,
1587				     KBUILD_MODNAME, board);
1588		if (retval) {
1589			dev_err(board->dev, "cannot register interrupt handler err=%d\n", retval);
1590			return retval;
1591		}
1592	}
1593	e_priv->irq = pci_device->irq;
1594
1595	e_priv->dma_burst_length = fifos_read(e_priv, FIFO_MAX_BURST_LENGTH_REG) &
1596		fifo_max_burst_length_mask;
1597
1598	return fmh_gpib_init(e_priv, board, handshake_mode);
1599}
1600
1601int fmh_gpib_pci_attach_holdoff_all(struct gpib_board *board,
1602				    const struct gpib_board_config *config)
1603{
1604	return fmh_gpib_pci_attach_impl(board, config, HR_HLDA);
1605}
1606
1607int fmh_gpib_pci_attach_holdoff_end(struct gpib_board *board,
1608				    const struct gpib_board_config *config)
1609{
1610	int retval;
1611	struct fmh_priv *e_priv;
1612
1613	retval = fmh_gpib_pci_attach_impl(board, config, HR_HLDE);
1614	e_priv = board->private_data;
1615	if (retval == 0 && e_priv && e_priv->supports_fifo_interrupts == 0) {
1616		dev_err(board->gpib_dev, "your fmh_gpib_core does not appear to support fifo interrupts.  Try the fmh_gpib_pci_unaccel board type instead.");
1617		return -EIO;
1618	}
1619	return retval;
1620}
1621
1622void fmh_gpib_pci_detach(struct gpib_board *board)
1623{
1624	struct fmh_priv *e_priv = board->private_data;
1625	struct nec7210_priv *nec_priv;
1626
1627	if (e_priv)	{
1628		nec_priv = &e_priv->nec7210_priv;
1629
1630		if (e_priv->irq)
1631			free_irq(e_priv->irq, board);
1632		if (e_priv->fifo_base)
1633			fifos_write(e_priv, 0, FIFO_CONTROL_STATUS_REG);
1634		if (nec_priv->mmiobase) {
1635			write_byte(nec_priv, 0, ISR0_IMR0_REG);
1636			nec7210_board_reset(nec_priv, board);
1637		}
1638		if (e_priv->fifo_base)
1639			iounmap(e_priv->fifo_base);
1640		if (nec_priv->mmiobase)
1641			iounmap(nec_priv->mmiobase);
1642		if (e_priv->dma_port_res || e_priv->gpib_iomem_res)
1643			pci_release_regions(to_pci_dev(board->dev));
1644		if (board->dev)
1645			pci_dev_put(to_pci_dev(board->dev));
1646	}
1647	fmh_gpib_generic_detach(board);
1648}
1649
1650static int fmh_gpib_platform_probe(struct platform_device *pdev)
1651{
1652	return 0;
1653}
1654
1655static const struct of_device_id fmh_gpib_of_match[] = {
1656	{ .compatible = "fmhess,fmh_gpib_core"},
1657	{ {0} }
1658};
1659MODULE_DEVICE_TABLE(of, fmh_gpib_of_match);
1660
1661static struct platform_driver fmh_gpib_platform_driver = {
1662	.driver = {
1663		.name = DRV_NAME,
1664		.of_match_table = fmh_gpib_of_match,
1665	},
1666	.probe = &fmh_gpib_platform_probe
1667};
1668
1669static int fmh_gpib_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1670{
1671	return 0;
1672}
1673
1674static const struct pci_device_id fmh_gpib_pci_match[] = {
1675	{ BOGUS_PCI_VENDOR_ID_FLUKE, BOGUS_PCI_DEVICE_ID_FLUKE_BLADERUNNER, 0, 0, 0 },
1676	{ 0 }
1677};
1678MODULE_DEVICE_TABLE(pci, fmh_gpib_pci_match);
1679
1680static struct pci_driver fmh_gpib_pci_driver = {
1681	.name = DRV_NAME,
1682	.id_table = fmh_gpib_pci_match,
1683	.probe = &fmh_gpib_pci_probe
1684};
1685
1686static int __init fmh_gpib_init_module(void)
1687{
1688	int result;
1689
1690	result = platform_driver_register(&fmh_gpib_platform_driver);
1691	if (result) {
1692		pr_err("platform_driver_register failed: error = %d\n", result);
1693		return result;
1694	}
1695
1696	result = pci_register_driver(&fmh_gpib_pci_driver);
1697	if (result) {
1698		pr_err("pci_register_driver failed: error = %d\n", result);
1699		goto err_pci_driver;
1700	}
1701
1702	result = gpib_register_driver(&fmh_gpib_unaccel_interface, THIS_MODULE);
1703	if (result) {
1704		pr_err("gpib_register_driver failed: error = %d\n", result);
1705		goto err_unaccel;
1706	}
1707
1708	result = gpib_register_driver(&fmh_gpib_interface, THIS_MODULE);
1709	if (result) {
1710		pr_err("gpib_register_driver failed: error = %d\n", result);
1711		goto err_interface;
1712	}
1713
1714	result = gpib_register_driver(&fmh_gpib_pci_unaccel_interface, THIS_MODULE);
1715	if (result) {
1716		pr_err("gpib_register_driver failed: error = %d\n", result);
1717		goto err_pci_unaccel;
1718	}
1719
1720	result = gpib_register_driver(&fmh_gpib_pci_interface, THIS_MODULE);
1721	if (result) {
1722		pr_err("gpib_register_driver failed: error = %d\n", result);
1723		goto err_pci;
1724	}
1725
1726	return 0;
1727
1728err_pci:
1729	gpib_unregister_driver(&fmh_gpib_pci_unaccel_interface);
1730err_pci_unaccel:
1731	gpib_unregister_driver(&fmh_gpib_interface);
1732err_interface:
1733	gpib_unregister_driver(&fmh_gpib_unaccel_interface);
1734err_unaccel:
1735	pci_unregister_driver(&fmh_gpib_pci_driver);
1736err_pci_driver:
1737	platform_driver_unregister(&fmh_gpib_platform_driver);
1738
1739	return result;
1740}
1741
1742static void __exit fmh_gpib_exit_module(void)
1743{
1744	gpib_unregister_driver(&fmh_gpib_pci_interface);
1745	gpib_unregister_driver(&fmh_gpib_pci_unaccel_interface);
1746	gpib_unregister_driver(&fmh_gpib_unaccel_interface);
1747	gpib_unregister_driver(&fmh_gpib_interface);
1748
1749	pci_unregister_driver(&fmh_gpib_pci_driver);
1750	platform_driver_unregister(&fmh_gpib_platform_driver);
1751}
1752
1753module_init(fmh_gpib_init_module);
1754module_exit(fmh_gpib_exit_module);