agilent_82350b.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2
  3/***************************************************************************
  4 *    copyright            : (C) 2002, 2004 by Frank Mori Hess             *
  5 ***************************************************************************/
  6
  7#include "gpibP.h"
  8#include "plx9050.h"
  9#include "tms9914.h"
 10
 11enum pci_vendor_ids {
 12	PCI_VENDOR_ID_AGILENT = 0x15bc,
 13};
 14
 15enum pci_device_ids {
 16	PCI_DEVICE_ID_82350B = 0x0b01,
 17	PCI_DEVICE_ID_82351A = 0x1218
 18};
 19
 20enum pci_subdevice_ids {
 21	PCI_SUBDEVICE_ID_82350A = 0x10b0,
 22};
 23
 24enum pci_regions_82350a {
 25	PLX_MEM_REGION  = 0,
 26	PLX_IO_REGION   = 1,
 27	GPIB_82350A_REGION = 2,
 28	SRAM_82350A_REGION = 3,
 29	BORG_82350A_REGION = 4
 30};
 31
 32enum pci_regions_82350b {
 33	GPIB_REGION = 0,
 34	SRAM_REGION = 1,
 35	MISC_REGION = 2,
 36};
 37
 38enum board_model {
 39	MODEL_82350A,
 40	MODEL_82350B,
 41	MODEL_82351A
 42};
 43
 44/* struct which defines private_data for board */
 45struct agilent_82350b_priv {
 46	struct tms9914_priv tms9914_priv;
 47	struct pci_dev *pci_device;
 48	void __iomem *plx_base;	/* 82350a only */
 49	void __iomem *gpib_base;
 50	void __iomem *sram_base;
 51	void __iomem *misc_base;
 52	void __iomem *borg_base;
 53	int irq;
 54	unsigned short card_mode_bits;
 55	unsigned short event_status_bits;
 56	enum board_model model;
 57	bool using_fifos;
 58};
 59
 60/* registers */
 61enum agilent_82350b_gpib_registers
 62
 63{
 64	CARD_MODE_REG = 0x1,
 65	CONFIG_DATA_REG = 0x2, /* 82350A specific */
 66	INTERRUPT_ENABLE_REG = 0x3,
 67	EVENT_STATUS_REG = 0x4,
 68	EVENT_ENABLE_REG = 0x5,
 69	STREAM_STATUS_REG = 0x7,
 70	DEBUG_RAM0_REG = 0x8,
 71	DEBUG_RAM1_REG = 0x9,
 72	DEBUG_RAM2_REG = 0xa,
 73	DEBUG_RAM3_REG = 0xb,
 74	XFER_COUNT_LO_REG = 0xc,
 75	XFER_COUNT_MID_REG = 0xd,
 76	XFER_COUNT_HI_REG = 0xe,
 77	TMS9914_BASE_REG = 0x10,
 78	INTERNAL_CONFIG_REG = 0x18,
 79	IMR0_READ_REG = 0x19, /* read */
 80	T1_DELAY_REG = 0x19, /* write */
 81	IMR1_READ_REG = 0x1a,
 82	ADR_READ_REG = 0x1b,
 83	SPMR_READ_REG = 0x1c,
 84	PPR_READ_REG = 0x1d,
 85	CDOR_READ_REG = 0x1e,
 86	SRAM_ACCESS_CONTROL_REG = 0x1f,
 87};
 88
 89enum card_mode_bits
 90
 91{
 92	ACTIVE_CONTROLLER_BIT = 0x2, /* read-only */
 93	CM_SYSTEM_CONTROLLER_BIT = 0x8,
 94	ENABLE_BUS_MONITOR_BIT = 0x10,
 95	ENABLE_PCI_IRQ_BIT = 0x20,
 96};
 97
 98enum interrupt_enable_bits
 99
100{
101	ENABLE_TMS9914_INTERRUPTS_BIT = 0x1,
102	ENABLE_BUFFER_END_INTERRUPT_BIT = 0x10,
103	ENABLE_TERM_COUNT_INTERRUPT_BIT = 0x20,
104};
105
106enum event_enable_bits
107
108{
109	ENABLE_BUFFER_END_EVENTS_BIT = 0x10,
110	ENABLE_TERM_COUNT_EVENTS_BIT = 0x20,
111};
112
113enum event_status_bits
114
115{
116	TMS9914_IRQ_STATUS_BIT = 0x1,
117	IRQ_STATUS_BIT = 0x2,
118	BUFFER_END_STATUS_BIT = 0x10, /* write-clear */
119	TERM_COUNT_STATUS_BIT = 0x20, /* write-clear */
120};
121
122enum stream_status_bits
123
124{
125	HALTED_STATUS_BIT = 0x1, /* read */
126	RESTART_STREAM_BIT = 0x1, /* write */
127};
128
129enum internal_config_bits
130
131{
132	IC_SYSTEM_CONTROLLER_BIT = 0x80,
133};
134
135enum sram_access_control_bits
136
137{
138	DIRECTION_GPIB_TO_HOST = 0x20, /* transfer direction */
139	ENABLE_TI_TO_SRAM = 0x40, /* enable fifo */
140	ENABLE_FAST_TALKER = 0x80 /* added for 82350A (not used) */
141};
142
143enum borg_bits
144
145{
146	BORG_READY_BIT = 0x40,
147	BORG_DONE_BIT = 0x80
148};
149
150static const int agilent_82350b_fifo_size = 0x8000;
151
152static inline int agilent_82350b_fifo_is_halted(struct agilent_82350b_priv *a_priv)
153
154{
155	return readb(a_priv->gpib_base + STREAM_STATUS_REG) & HALTED_STATUS_BIT;
156}
157