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ti_sci.h
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linux-6.19.14/drivers/firmware/ti_sci.h
1/* SPDX-License-Identifier: BSD-3-Clause */ 2/* 3 * Texas Instruments System Control Interface (TISCI) Protocol 4 * 5 * Communication protocol with TI SCI hardware 6 * The system works in a message response protocol 7 * See: https://software-dl.ti.com/tisci/esd/latest/index.html for details 8 * 9 * Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/ 10 */ 11 12#ifndef __TI_SCI_H 13#define __TI_SCI_H 14 15/* Generic Messages */ 16#define TI_SCI_MSG_ENABLE_WDT 0x0000 17#define TI_SCI_MSG_WAKE_RESET 0x0001 18#define TI_SCI_MSG_VERSION 0x0002 19#define TI_SCI_MSG_WAKE_REASON 0x0003 20#define TI_SCI_MSG_GOODBYE 0x0004 21#define TI_SCI_MSG_SYS_RESET 0x0005 22#define TI_SCI_MSG_QUERY_FW_CAPS 0x0022 23 24/* Device requests */ 25#define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 26#define TI_SCI_MSG_GET_DEVICE_STATE 0x0201 27#define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202 28 29/* Clock requests */ 30#define TI_SCI_MSG_SET_CLOCK_STATE 0x0100 31#define TI_SCI_MSG_GET_CLOCK_STATE 0x0101 32#define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102 33#define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103 34#define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104 35#define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c 36#define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d 37#define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e 38 39/* Low Power Mode Requests */ 40#define TI_SCI_MSG_PREPARE_SLEEP 0x0300 41#define TI_SCI_MSG_LPM_WAKE_REASON 0x0306 42#define TI_SCI_MSG_SET_IO_ISOLATION 0x0307 43#define TI_SCI_MSG_LPM_SET_DEVICE_CONSTRAINT 0x0309 44#define TI_SCI_MSG_LPM_SET_LATENCY_CONSTRAINT 0x030A 45#define TI_SCI_MSG_LPM_ABORT 0x0311 46 47/* Resource Management Requests */ 48#define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500 49 50/* IRQ requests */ 51#define TI_SCI_MSG_SET_IRQ 0x1000 52#define TI_SCI_MSG_FREE_IRQ 0x1001 53 54/* NAVSS resource management */ 55/* Ringacc requests */ 56#define TI_SCI_MSG_RM_RING_ALLOCATE 0x1100 57#define TI_SCI_MSG_RM_RING_FREE 0x1101 58#define TI_SCI_MSG_RM_RING_RECONFIG 0x1102 59#define TI_SCI_MSG_RM_RING_RESET 0x1103 60#define TI_SCI_MSG_RM_RING_CFG 0x1110 61 62/* PSI-L requests */ 63#define TI_SCI_MSG_RM_PSIL_PAIR 0x1280 64#define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281 65 66#define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200 67#define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201 68#define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210 69#define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211 70#define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220 71#define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221 72 73#define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205 74#define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206 75#define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215 76#define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216 77#define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230 78#define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231 79#define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232 80#define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233 81 82/* Processor Control requests */ 83#define TI_SCI_MSG_PROC_REQUEST 0xc000 84#define TI_SCI_MSG_PROC_RELEASE 0xc001 85#define TI_SCI_MSG_PROC_HANDOVER 0xc005 86#define TI_SCI_MSG_SET_CONFIG 0xc100 87#define TI_SCI_MSG_SET_CTRL 0xc101 88#define TI_SCI_MSG_GET_STATUS 0xc400 89 90/** 91 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses 92 * @type: Type of messages: One of TI_SCI_MSG* values 93 * @host: Host of the message 94 * @seq: Message identifier indicating a transfer sequence 95 * @flags: Flag for the message 96 */ 97struct ti_sci_msg_hdr { 98 u16 type; 99 u8 host; 100 u8 seq; 101#define TI_SCI_MSG_FLAG(val) (1 << (val)) 102#define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0 103#define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0) 104#define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1) 105#define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0 106#define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1) 107 /* Additional Flags */ 108 u32 flags; 109} __packed; 110 111/** 112 * struct ti_sci_msg_resp_version - Response for a message 113 * @hdr: Generic header 114 * @firmware_description: String describing the firmware 115 * @firmware_revision: Firmware revision 116 * @abi_major: Major version of the ABI that firmware supports 117 * @abi_minor: Minor version of the ABI that firmware supports 118 * 119 * In general, ABI version changes follow the rule that minor version increments 120 * are backward compatible. Major revision changes in ABI may not be 121 * backward compatible. 122 * 123 * Response to a generic message with message type TI_SCI_MSG_VERSION 124 */ 125struct ti_sci_msg_resp_version { 126 struct ti_sci_msg_hdr hdr; 127 char firmware_description[32]; 128 u16 firmware_revision; 129 u8 abi_major; 130 u8 abi_minor; 131} __packed; 132 133/** 134 * struct ti_sci_msg_req_reboot - Reboot the SoC 135 * @hdr: Generic Header 136 * 137 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic 138 * ACK/NACK message. 139 */ 140struct ti_sci_msg_req_reboot { 141 struct ti_sci_msg_hdr hdr; 142} __packed; 143 144/** 145 * struct ti_sci_msg_resp_query_fw_caps - Response for query firmware caps 146 * @hdr: Generic header 147 * @fw_caps: Each bit in fw_caps indicating one FW/SOC capability 148 * MSG_FLAG_CAPS_GENERIC: Generic capability (LPM not supported) 149 * MSG_FLAG_CAPS_LPM_PARTIAL_IO: Partial IO in LPM 150 * MSG_FLAG_CAPS_LPM_DM_MANAGED: LPM can be managed by DM 151 * MSG_FLAG_CAPS_LPM_ABORT: Abort entry to LPM 152 * MSG_FLAG_CAPS_IO_ISOLATION: IO Isolation support 153 * 154 * Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS 155 * providing currently available SOC/firmware capabilities. SoC that don't 156 * support low power modes return only MSG_FLAG_CAPS_GENERIC capability. 157 */ 158struct ti_sci_msg_resp_query_fw_caps { 159 struct ti_sci_msg_hdr hdr; 160#define MSG_FLAG_CAPS_GENERIC TI_SCI_MSG_FLAG(0) 161#define MSG_FLAG_CAPS_LPM_PARTIAL_IO TI_SCI_MSG_FLAG(4) 162#define MSG_FLAG_CAPS_LPM_DM_MANAGED TI_SCI_MSG_FLAG(5) 163#define MSG_FLAG_CAPS_LPM_ABORT TI_SCI_MSG_FLAG(9) 164#define MSG_FLAG_CAPS_IO_ISOLATION TI_SCI_MSG_FLAG(7) 165#define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1) 166 u64 fw_caps; 167} __packed; 168 169/** 170 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device 171 * @hdr: Generic header 172 * @id: Indicates which device to modify 173 * @reserved: Reserved space in message, must be 0 for backward compatibility 174 * @state: The desired state of the device. 175 * 176 * Certain flags can also be set to alter the device state: 177 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source. 178 * The meaning of this flag will vary slightly from device to device and from 179 * SoC to SoC but it generally allows the device to wake the SoC out of deep 180 * suspend states. 181 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device. 182 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed 183 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively. 184 * If another host already has this device set to STATE_RETENTION or STATE_ON, 185 * the message will fail. Once successful, other hosts attempting to set 186 * STATE_RETENTION or STATE_ON will fail. 187 * 188 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic 189 * ACK/NACK message. 190 */ 191struct ti_sci_msg_req_set_device_state { 192 /* Additional hdr->flags options */ 193#define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8) 194#define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9) 195#define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10) 196 struct ti_sci_msg_hdr hdr; 197 u32 id; 198 u32 reserved; 199 200#define MSG_DEVICE_SW_STATE_AUTO_OFF 0 201#define MSG_DEVICE_SW_STATE_RETENTION 1 202#define MSG_DEVICE_SW_STATE_ON 2 203 u8 state; 204} __packed; 205 206/** 207 * struct ti_sci_msg_req_get_device_state - Request to get device. 208 * @hdr: Generic header 209 * @id: Device Identifier 210 * 211 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state 212 * information 213 */ 214struct ti_sci_msg_req_get_device_state { 215 struct ti_sci_msg_hdr hdr; 216 u32 id; 217} __packed; 218 219/** 220 * struct ti_sci_msg_resp_get_device_state - Response to get device request. 221 * @hdr: Generic header 222 * @context_loss_count: Indicates how many times the device has lost context. A 223 * driver can use this monotonic counter to determine if the device has 224 * lost context since the last time this message was exchanged. 225 * @resets: Programmed state of the reset lines. 226 * @programmed_state: The state as programmed by set_device. 227 * - Uses the MSG_DEVICE_SW_* macros 228 * @current_state: The actual state of the hardware. 229 * 230 * Response to request TI_SCI_MSG_GET_DEVICE_STATE. 231 */ 232struct ti_sci_msg_resp_get_device_state { 233 struct ti_sci_msg_hdr hdr; 234 u32 context_loss_count; 235 u32 resets; 236 u8 programmed_state; 237#define MSG_DEVICE_HW_STATE_OFF 0 238#define MSG_DEVICE_HW_STATE_ON 1 239#define MSG_DEVICE_HW_STATE_TRANS 2 240 u8 current_state; 241} __packed; 242 243/** 244 * struct ti_sci_msg_req_set_device_resets - Set the desired resets 245 * configuration of the device 246 * @hdr: Generic header 247 * @id: Indicates which device to modify 248 * @resets: A bit field of resets for the device. The meaning, behavior, 249 * and usage of the reset flags are device specific. 0 for a bit 250 * indicates releasing the reset represented by that bit while 1 251 * indicates keeping it held. 252 * 253 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic 254 * ACK/NACK message. 255 */ 256struct ti_sci_msg_req_set_device_resets { 257 struct ti_sci_msg_hdr hdr; 258 u32 id; 259 u32 resets; 260} __packed; 261 262/** 263 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state 264 * @hdr: Generic Header, Certain flags can be set specific to the clocks: 265 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified 266 * via spread spectrum clocking. 267 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's 268 * frequency to be changed while it is running so long as it 269 * is within the min/max limits. 270 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this 271 * is only applicable to clock inputs on the SoC pseudo-device. 272 * @dev_id: Device identifier this request is for 273 * @clk_id: Clock identifier for the device for this request. 274 * Each device has it's own set of clock inputs. This indexes 275 * which clock input to modify. Set to 255 if clock ID is 276 * greater than or equal to 255. 277 * @request_state: Request the state for the clock to be set to. 278 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock, 279 * it can be disabled, regardless of the state of the device 280 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to 281 * automatically manage the state of this clock. If the device 282 * is enabled, then the clock is enabled. If the device is set 283 * to off or retention, then the clock is internally set as not 284 * being required by the device.(default) 285 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled, 286 * regardless of the state of the device. 287 * @clk_id_32: Clock identifier for the device for this request. 288 * Only to be used if the clock ID is greater than or equal to 289 * 255. 290 * 291 * Normally, all required clocks are managed by TISCI entity, this is used 292 * only for specific control *IF* required. Auto managed state is 293 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote 294 * will explicitly control. 295 * 296 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic 297 * ACK or NACK message. 298 */ 299struct ti_sci_msg_req_set_clock_state { 300 /* Additional hdr->flags options */ 301#define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8) 302#define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9) 303#define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10) 304 struct ti_sci_msg_hdr hdr; 305 u32 dev_id; 306 u8 clk_id; 307#define MSG_CLOCK_SW_STATE_UNREQ 0 308#define MSG_CLOCK_SW_STATE_AUTO 1 309#define MSG_CLOCK_SW_STATE_REQ 2 310 u8 request_state; 311 u32 clk_id_32; 312} __packed; 313 314/** 315 * struct ti_sci_msg_req_get_clock_state - Request for clock state 316 * @hdr: Generic Header 317 * @dev_id: Device identifier this request is for 318 * @clk_id: Clock identifier for the device for this request. 319 * Each device has it's own set of clock inputs. This indexes 320 * which clock input to get state of. Set to 255 if the clock 321 * ID is greater than or equal to 255. 322 * @clk_id_32: Clock identifier for the device for the request. 323 * Only to be used if the clock ID is greater than or equal to 324 * 255. 325 * 326 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state 327 * of the clock 328 */ 329struct ti_sci_msg_req_get_clock_state { 330 struct ti_sci_msg_hdr hdr; 331 u32 dev_id; 332 u8 clk_id; 333 u32 clk_id_32; 334} __packed; 335 336/** 337 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state 338 * @hdr: Generic Header 339 * @programmed_state: Any programmed state of the clock. This is one of 340 * MSG_CLOCK_SW_STATE* values. 341 * @current_state: Current state of the clock. This is one of: 342 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready 343 * MSG_CLOCK_HW_STATE_READY: Clock is ready 344 * 345 * Response to TI_SCI_MSG_GET_CLOCK_STATE. 346 */ 347struct ti_sci_msg_resp_get_clock_state { 348 struct ti_sci_msg_hdr hdr; 349 u8 programmed_state; 350#define MSG_CLOCK_HW_STATE_NOT_READY 0 351#define MSG_CLOCK_HW_STATE_READY 1 352 u8 current_state; 353} __packed; 354 355/** 356 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent 357 * @hdr: Generic Header 358 * @dev_id: Device identifier this request is for 359 * @clk_id: Clock identifier for the device for this request. 360 * Each device has it's own set of clock inputs. This indexes 361 * which clock input to modify. Set to 255 if clock ID is 362 * greater than or equal to 255. 363 * @parent_id: The new clock parent is selectable by an index via this 364 * parameter. Set to 255 if clock ID is greater than or 365 * equal to 255. 366 * @clk_id_32: Clock identifier if @clk_id field is 255. 367 * @parent_id_32: Parent identifier if @parent_id is 255. 368 * 369 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic 370 * ACK / NACK message. 371 */ 372struct ti_sci_msg_req_set_clock_parent { 373 struct ti_sci_msg_hdr hdr; 374 u32 dev_id; 375 u8 clk_id; 376 u8 parent_id; 377 u32 clk_id_32; 378 u32 parent_id_32; 379} __packed; 380 381/** 382 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent 383 * @hdr: Generic Header 384 * @dev_id: Device identifier this request is for 385 * @clk_id: Clock identifier for the device for this request. 386 * Each device has it's own set of clock inputs. This indexes 387 * which clock input to get the parent for. If this field 388 * contains 255, the actual clock identifier is stored in 389 * @clk_id_32. 390 * @clk_id_32: Clock identifier if the @clk_id field contains 255. 391 * 392 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information 393 */ 394struct ti_sci_msg_req_get_clock_parent { 395 struct ti_sci_msg_hdr hdr; 396 u32 dev_id; 397 u8 clk_id; 398 u32 clk_id_32; 399} __packed; 400 401/** 402 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent 403 * @hdr: Generic Header 404 * @parent_id: The current clock parent. If set to 255, the current parent 405 * ID can be found from the @parent_id_32 field. 406 * @parent_id_32: Current clock parent if @parent_id field is set to 407 * 255. 408 * 409 * Response to TI_SCI_MSG_GET_CLOCK_PARENT. 410 */ 411struct ti_sci_msg_resp_get_clock_parent { 412 struct ti_sci_msg_hdr hdr; 413 u8 parent_id; 414 u32 parent_id_32; 415} __packed; 416 417/** 418 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents 419 * @hdr: Generic header 420 * @dev_id: Device identifier this request is for 421 * @clk_id: Clock identifier for the device for this request. Set to 422 * 255 if clock ID is greater than or equal to 255. 423 * @clk_id_32: Clock identifier if the @clk_id field contains 255. 424 * 425 * This request provides information about how many clock parent options 426 * are available for a given clock to a device. This is typically used 427 * for input clocks. 428 * 429 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate 430 * message, or NACK in case of inability to satisfy request. 431 */ 432struct ti_sci_msg_req_get_clock_num_parents { 433 struct ti_sci_msg_hdr hdr; 434 u32 dev_id; 435 u8 clk_id; 436 u32 clk_id_32; 437} __packed; 438 439/** 440 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents 441 * @hdr: Generic header 442 * @num_parents: Number of clock parents. If set to 255, the actual 443 * number of parents is stored into @num_parents_32 444 * field instead. 445 * @num_parents_32: Number of clock parents if @num_parents field is 446 * set to 255. 447 * 448 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 449 */ 450struct ti_sci_msg_resp_get_clock_num_parents { 451 struct ti_sci_msg_hdr hdr; 452 u8 num_parents; 453 u32 num_parents_32; 454} __packed; 455 456/** 457 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency 458 * @hdr: Generic Header 459 * @dev_id: Device identifier this request is for 460 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 461 * allowable programmed frequency and does not account for clock 462 * tolerances and jitter. 463 * @target_freq_hz: The target clock frequency. A frequency will be found 464 * as close to this target frequency as possible. 465 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 466 * allowable programmed frequency and does not account for clock 467 * tolerances and jitter. 468 * @clk_id: Clock identifier for the device for this request. Set to 469 * 255 if clock identifier is greater than or equal to 255. 470 * @clk_id_32: Clock identifier if @clk_id is set to 255. 471 * 472 * NOTE: Normally clock frequency management is automatically done by TISCI 473 * entity. In case of specific requests, TISCI evaluates capability to achieve 474 * requested frequency within provided range and responds with 475 * result message. 476 * 477 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message, 478 * or NACK in case of inability to satisfy request. 479 */ 480struct ti_sci_msg_req_query_clock_freq { 481 struct ti_sci_msg_hdr hdr; 482 u32 dev_id; 483 u64 min_freq_hz; 484 u64 target_freq_hz; 485 u64 max_freq_hz; 486 u8 clk_id; 487 u32 clk_id_32; 488} __packed; 489 490/** 491 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query 492 * @hdr: Generic Header 493 * @freq_hz: Frequency that is the best match in Hz. 494 * 495 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request 496 * cannot be satisfied, the message will be of type NACK. 497 */ 498struct ti_sci_msg_resp_query_clock_freq { 499 struct ti_sci_msg_hdr hdr; 500 u64 freq_hz; 501} __packed; 502 503/** 504 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency 505 * @hdr: Generic Header 506 * @dev_id: Device identifier this request is for 507 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 508 * allowable programmed frequency and does not account for clock 509 * tolerances and jitter. 510 * @target_freq_hz: The target clock frequency. The clock will be programmed 511 * at a rate as close to this target frequency as possible. 512 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 513 * allowable programmed frequency and does not account for clock 514 * tolerances and jitter. 515 * @clk_id: Clock identifier for the device for this request. Set to 516 * 255 if clock ID is greater than or equal to 255. 517 * @clk_id_32: Clock identifier if @clk_id field is set to 255. 518 * 519 * NOTE: Normally clock frequency management is automatically done by TISCI 520 * entity. In case of specific requests, TISCI evaluates capability to achieve 521 * requested range and responds with success/failure message. 522 * 523 * This sets the desired frequency for a clock within an allowable 524 * range. This message will fail on an enabled clock unless 525 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally, 526 * if other clocks have their frequency modified due to this message, 527 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled. 528 * 529 * Calling set frequency on a clock input to the SoC pseudo-device will 530 * inform the PMMC of that clock's frequency. Setting a frequency of 531 * zero will indicate the clock is disabled. 532 * 533 * Calling set frequency on clock outputs from the SoC pseudo-device will 534 * function similarly to setting the clock frequency on a device. 535 * 536 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK 537 * message. 538 */ 539struct ti_sci_msg_req_set_clock_freq { 540 struct ti_sci_msg_hdr hdr; 541 u32 dev_id; 542 u64 min_freq_hz; 543 u64 target_freq_hz; 544 u64 max_freq_hz; 545 u8 clk_id; 546 u32 clk_id_32; 547} __packed; 548 549/** 550 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency 551 * @hdr: Generic Header 552 * @dev_id: Device identifier this request is for 553 * @clk_id: Clock identifier for the device for this request. Set to 554 * 255 if clock ID is greater than or equal to 255. 555 * @clk_id_32: Clock identifier if @clk_id field is set to 255. 556 * 557 * NOTE: Normally clock frequency management is automatically done by TISCI 558 * entity. In some cases, clock frequencies are configured by host. 559 * 560 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency 561 * that the clock is currently at. 562 */ 563struct ti_sci_msg_req_get_clock_freq { 564 struct ti_sci_msg_hdr hdr; 565 u32 dev_id; 566 u8 clk_id; 567 u32 clk_id_32; 568} __packed; 569 570/** 571 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request 572 * @hdr: Generic Header 573 * @freq_hz: Frequency that the clock is currently on, in Hz. 574 * 575 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ. 576 */ 577struct ti_sci_msg_resp_get_clock_freq { 578 struct ti_sci_msg_hdr hdr; 579 u64 freq_hz; 580} __packed; 581 582/** 583 * struct tisci_msg_req_prepare_sleep - Request for TISCI_MSG_PREPARE_SLEEP. 584 * 585 * @hdr TISCI header to provide ACK/NAK flags to the host. 586 * @mode Low power mode to enter. 587 * @ctx_lo Low 32-bits of physical pointer to address to use for context save. 588 * @ctx_hi High 32-bits of physical pointer to address to use for context save. 589 * @debug_flags Flags that can be set to halt the sequence during suspend or 590 * resume to allow JTAG connection and debug. 591 * 592 * This message is used as the first step of entering a low power mode. It 593 * allows configurable information, including which state to enter to be 594 * easily shared from the application, as this is a non-secure message and 595 * therefore can be sent by anyone. 596 */ 597struct ti_sci_msg_req_prepare_sleep { 598 struct ti_sci_msg_hdr hdr; 599 600/* 601 * When sending prepare_sleep with MODE_PARTIAL_IO no response will be sent, 602 * no further steps are required. 603 */ 604#define TISCI_MSG_VALUE_SLEEP_MODE_PARTIAL_IO 0x03 605#define TISCI_MSG_VALUE_SLEEP_MODE_DM_MANAGED 0xfd 606 u8 mode; 607 u32 ctx_lo; 608 u32 ctx_hi; 609 u32 debug_flags; 610} __packed; 611 612/** 613 * struct tisci_msg_set_io_isolation_req - Request for TI_SCI_MSG_SET_IO_ISOLATION. 614 * 615 * @hdr: Generic header 616 * @state: The deseared state of the IO isolation. 617 * 618 * This message is used to enable/disable IO isolation for low power modes. 619 * Response is generic ACK / NACK message. 620 */ 621struct ti_sci_msg_req_set_io_isolation { 622 struct ti_sci_msg_hdr hdr; 623 u8 state; 624} __packed; 625 626/** 627 * struct ti_sci_msg_resp_lpm_wake_reason - Response for TI_SCI_MSG_LPM_WAKE_REASON. 628 * 629 * @hdr: Generic header. 630 * @wake_source: The wake up source that woke soc from LPM. 631 * @wake_timestamp: Timestamp at which soc woke. 632 * @wake_pin: The pin that has triggered wake up. 633 * @mode: The last entered low power mode. 634 * @rsvd: Reserved for future use. 635 * 636 * Response to a generic message with message type TI_SCI_MSG_LPM_WAKE_REASON, 637 * used to query the wake up source, pin and entered low power mode. 638 */ 639struct ti_sci_msg_resp_lpm_wake_reason { 640 struct ti_sci_msg_hdr hdr; 641 u32 wake_source; 642 u64 wake_timestamp; 643 u8 wake_pin; 644 u8 mode; 645 u32 rsvd[2]; 646} __packed; 647 648/** 649 * struct ti_sci_msg_req_lpm_set_device_constraint - Request for 650 * TISCI_MSG_LPM_SET_DEVICE_CONSTRAINT. 651 * 652 * @hdr: TISCI header to provide ACK/NAK flags to the host. 653 * @id: Device ID of device whose constraint has to be modified. 654 * @state: The desired state of device constraint: set or clear. 655 * @rsvd: Reserved for future use. 656 * 657 * This message is used by host to set constraint on the device. This can be 658 * sent anytime after boot before prepare sleep message. Any device can set a 659 * constraint on the low power mode that the SoC can enter. It allows 660 * configurable information to be easily shared from the application, as this 661 * is a non-secure message and therefore can be sent by anyone. By setting a 662 * constraint, the device ensures that it will not be powered off or reset in 663 * the selected mode. Note: Access Restriction: Exclusivity flag of Device will 664 * be honored. If some other host already has constraint on this device ID, 665 * NACK will be returned. 666 */ 667struct ti_sci_msg_req_lpm_set_device_constraint { 668 struct ti_sci_msg_hdr hdr; 669 u32 id; 670 u8 state; 671 u32 rsvd[2]; 672} __packed; 673 674/** 675 * struct ti_sci_msg_req_lpm_set_latency_constraint - Request for 676 * TISCI_MSG_LPM_SET_LATENCY_CONSTRAINT. 677 * 678 * @hdr: TISCI header to provide ACK/NAK flags to the host. 679 * @wkup_latency: The maximum acceptable latency to wake up from low power mode 680 * in milliseconds. The deeper the state, the higher the latency. 681 * @state: The desired state of wakeup latency constraint: set or clear. 682 * @rsvd: Reserved for future use. 683 * 684 * This message is used by host to set wakeup latency from low power mode. This can 685 * be sent anytime after boot before prepare sleep message, and can be sent after 686 * current low power mode is exited. Any device can set a constraint on the low power 687 * mode that the SoC can enter. It allows configurable information to be easily shared 688 * from the application, as this is a non-secure message and therefore can be sent by 689 * anyone. By setting a wakeup latency constraint, the host ensures that the resume time 690 * from selected low power mode will be less than the constraint value. 691 */ 692struct ti_sci_msg_req_lpm_set_latency_constraint { 693 struct ti_sci_msg_hdr hdr; 694 u16 latency; 695 u8 state; 696 u32 rsvd; 697} __packed; 698 699#define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff 700 701/** 702 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned 703 * range of resources. 704 * @hdr: Generic Header 705 * @type: Unique resource assignment type 706 * @subtype: Resource assignment subtype within the resource type. 707 * @secondary_host: Host processing entity to which the resources are 708 * allocated. This is required only when the destination 709 * host id id different from ti sci interface host id, 710 * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed. 711 * 712 * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested 713 * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE. 714 */ 715struct ti_sci_msg_req_get_resource_range { 716 struct ti_sci_msg_hdr hdr; 717#define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0) 718#define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0) 719 u16 type; 720 u8 subtype; 721 u8 secondary_host; 722} __packed; 723 724/** 725 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range. 726 * @hdr: Generic Header 727 * @range_start: Start index of the first resource range. 728 * @range_num: Number of resources in the first range. 729 * @range_start_sec: Start index of the second resource range. 730 * @range_num_sec: Number of resources in the second range. 731 * 732 * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE. 733 */ 734struct ti_sci_msg_resp_get_resource_range { 735 struct ti_sci_msg_hdr hdr; 736 u16 range_start; 737 u16 range_num; 738 u16 range_start_sec; 739 u16 range_num_sec; 740} __packed; 741 742/** 743 * struct ti_sci_msg_req_manage_irq - Request to configure/release the route 744 * between the dev and the host. 745 * @hdr: Generic Header 746 * @valid_params: Bit fields defining the validity of interrupt source 747 * parameters. If a bit is not set, then corresponding 748 * field is not valid and will not be used for route set. 749 * Bit field definitions: 750 * 0 - Valid bit for @dst_id 751 * 1 - Valid bit for @dst_host_irq 752 * 2 - Valid bit for @ia_id 753 * 3 - Valid bit for @vint 754 * 4 - Valid bit for @global_event 755 * 5 - Valid bit for @vint_status_bit_index 756 * 31 - Valid bit for @secondary_host 757 * @src_id: IRQ source peripheral ID. 758 * @src_index: IRQ source index within the peripheral 759 * @dst_id: IRQ Destination ID. Based on the architecture it can be 760 * IRQ controller or host processor ID. 761 * @dst_host_irq: IRQ number of the destination host IRQ controller 762 * @ia_id: Device ID of the interrupt aggregator in which the 763 * vint resides. 764 * @vint: Virtual interrupt number if the interrupt route 765 * is through an interrupt aggregator. 766 * @global_event: Global event that is to be mapped to interrupt 767 * aggregator virtual interrupt status bit. 768 * @vint_status_bit: Virtual interrupt status bit if the interrupt route 769 * utilizes an interrupt aggregator status bit. 770 * @secondary_host: Host ID of the IRQ destination computing entity. This is 771 * required only when destination host id is different 772 * from ti sci interface host id. 773 * 774 * Request type is TI_SCI_MSG_SET/RELEASE_IRQ. 775 * Response is generic ACK / NACK message. 776 */ 777struct ti_sci_msg_req_manage_irq { 778 struct ti_sci_msg_hdr hdr; 779#define MSG_FLAG_DST_ID_VALID TI_SCI_MSG_FLAG(0) 780#define MSG_FLAG_DST_HOST_IRQ_VALID TI_SCI_MSG_FLAG(1) 781#define MSG_FLAG_IA_ID_VALID TI_SCI_MSG_FLAG(2) 782#define MSG_FLAG_VINT_VALID TI_SCI_MSG_FLAG(3) 783#define MSG_FLAG_GLB_EVNT_VALID TI_SCI_MSG_FLAG(4) 784#define MSG_FLAG_VINT_STS_BIT_VALID TI_SCI_MSG_FLAG(5) 785#define MSG_FLAG_SHOST_VALID TI_SCI_MSG_FLAG(31) 786 u32 valid_params; 787 u16 src_id; 788 u16 src_index; 789 u16 dst_id; 790 u16 dst_host_irq; 791 u16 ia_id; 792 u16 vint; 793 u16 global_event; 794 u8 vint_status_bit; 795 u8 secondary_host; 796} __packed; 797 798/** 799 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring 800 * 801 * Configures the non-real-time registers of a Navigator Subsystem ring. 802 * @hdr: Generic Header 803 * @valid_params: Bitfield defining validity of ring configuration parameters. 804 * The ring configuration fields are not valid, and will not be used for 805 * ring configuration, if their corresponding valid bit is zero. 806 * Valid bit usage: 807 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo 808 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi 809 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count 810 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode 811 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size 812 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id 813 * 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid 814 * 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL 815 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated 816 * @index: ring index to be configured. 817 * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's 818 * RING_BA_LO register 819 * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's 820 * RING_BA_HI register. 821 * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM 822 * modes. 823 * @mode: Specifies the mode the ring is to be configured. 824 * @size: Specifies encoded ring element size. To calculate the encoded size use 825 * the formula (log2(size_bytes) - 2), where size_bytes cannot be 826 * greater than 256. 827 * @order_id: Specifies the ring's bus order ID. 828 * @virtid: Ring virt ID value 829 * @asel: Ring ASEL (address select) value to be set into the ASEL field of the 830 * ring's RING_BA_HI register. 831 */ 832struct ti_sci_msg_rm_ring_cfg_req { 833 struct ti_sci_msg_hdr hdr; 834 u32 valid_params; 835 u16 nav_id; 836 u16 index; 837 u32 addr_lo; 838 u32 addr_hi; 839 u32 count; 840 u8 mode; 841 u8 size; 842 u8 order_id; 843 u16 virtid; 844 u8 asel; 845} __packed; 846 847/** 848 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination 849 * thread 850 * @hdr: Generic Header 851 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 852 * used to pair the source and destination threads. 853 * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 854 * 855 * UDMAP transmit channels mapped to source threads will have their 856 * TCHAN_THRD_ID register programmed with the destination thread if the pairing 857 * is successful. 858 859 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 860 * PSI-L destination threads start at index 0x8000. The request is NACK'd if 861 * the destination thread is not greater than or equal to 0x8000. 862 * 863 * UDMAP receive channels mapped to destination threads will have their 864 * RCHAN_THRD_ID register programmed with the source thread if the pairing 865 * is successful. 866 * 867 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK 868 * message. 869 */ 870struct ti_sci_msg_psil_pair { 871 struct ti_sci_msg_hdr hdr; 872 u32 nav_id; 873 u32 src_thread; 874 u32 dst_thread; 875} __packed; 876 877/** 878 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a 879 * destination thread 880 * @hdr: Generic Header 881 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 882 * used to unpair the source and destination threads. 883 * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 884 * 885 * UDMAP transmit channels mapped to source threads will have their 886 * TCHAN_THRD_ID register cleared if the unpairing is successful. 887 * 888 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 889 * PSI-L destination threads start at index 0x8000. The request is NACK'd if 890 * the destination thread is not greater than or equal to 0x8000. 891 * 892 * UDMAP receive channels mapped to destination threads will have their 893 * RCHAN_THRD_ID register cleared if the unpairing is successful. 894 * 895 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK 896 * message. 897 */ 898struct ti_sci_msg_psil_unpair { 899 struct ti_sci_msg_hdr hdr; 900 u32 nav_id; 901 u32 src_thread; 902 u32 dst_thread; 903} __packed; 904 905/** 906 * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration 907 * message 908 * @hdr: Generic Header 909 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is 910 * allocated 911 * @flow_index: UDMAP receive flow index for non-optional configuration. 912 * @rx_ch_index: Specifies the index of the receive channel using the flow_index 913 * @rx_einfo_present: UDMAP receive flow extended packet info present. 914 * @rx_psinfo_present: UDMAP receive flow PS words present. 915 * @rx_error_handling: UDMAP receive flow error handling configuration. Valid 916 * values are TI_SCI_RM_UDMAP_RX_FLOW_ERR_DROP/RETRY. 917 * @rx_desc_type: UDMAP receive flow descriptor type. It can be one of 918 * TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST/MONO. 919 * @rx_sop_offset: UDMAP receive flow start of packet offset. 920 * @rx_dest_qnum: UDMAP receive flow destination queue number. 921 * @rx_ps_location: UDMAP receive flow PS words location. 922 * 0 - end of packet descriptor 923 * 1 - Beginning of the data buffer 924 * @rx_src_tag_hi: UDMAP receive flow source tag high byte constant 925 * @rx_src_tag_lo: UDMAP receive flow source tag low byte constant 926 * @rx_dest_tag_hi: UDMAP receive flow destination tag high byte constant 927 * @rx_dest_tag_lo: UDMAP receive flow destination tag low byte constant 928 * @rx_src_tag_hi_sel: UDMAP receive flow source tag high byte selector 929 * @rx_src_tag_lo_sel: UDMAP receive flow source tag low byte selector 930 * @rx_dest_tag_hi_sel: UDMAP receive flow destination tag high byte selector 931 * @rx_dest_tag_lo_sel: UDMAP receive flow destination tag low byte selector 932 * @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue 933 * enable. If enabled, the ti_sci_rm_udmap_rx_flow_opt_cfg also need to be 934 * configured and sent. 935 * @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0. 936 * @rx_fdq1_qnum: UDMAP receive flow free descriptor queue 1. 937 * @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2. 938 * @rx_fdq3_qnum: UDMAP receive flow free descriptor queue 3. 939 * 940 * For detailed information on the settings, see the UDMAP section of the TRM. 941 */ 942struct ti_sci_msg_udmap_rx_flow_cfg { 943 struct ti_sci_msg_hdr hdr; 944 u32 nav_id; 945 u32 flow_index; 946 u32 rx_ch_index; 947 u8 rx_einfo_present; 948 u8 rx_psinfo_present; 949 u8 rx_error_handling; 950 u8 rx_desc_type; 951 u16 rx_sop_offset; 952 u16 rx_dest_qnum; 953 u8 rx_ps_location; 954 u8 rx_src_tag_hi; 955 u8 rx_src_tag_lo; 956 u8 rx_dest_tag_hi; 957 u8 rx_dest_tag_lo; 958 u8 rx_src_tag_hi_sel; 959 u8 rx_src_tag_lo_sel; 960 u8 rx_dest_tag_hi_sel; 961 u8 rx_dest_tag_lo_sel; 962 u8 rx_size_thresh_en; 963 u16 rx_fdq0_sz0_qnum; 964 u16 rx_fdq1_qnum; 965 u16 rx_fdq2_qnum; 966 u16 rx_fdq3_qnum; 967} __packed; 968 969/** 970 * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive 971 * flow optional configuration 972 * @hdr: Generic Header 973 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is 974 * allocated 975 * @flow_index: UDMAP receive flow index for optional configuration. 976 * @rx_ch_index: Specifies the index of the receive channel using the flow_index 977 * @rx_size_thresh0: UDMAP receive flow packet size threshold 0. 978 * @rx_size_thresh1: UDMAP receive flow packet size threshold 1. 979 * @rx_size_thresh2: UDMAP receive flow packet size threshold 2. 980 * @rx_fdq0_sz1_qnum: UDMAP receive flow free descriptor queue for size 981 * threshold 1. 982 * @rx_fdq0_sz2_qnum: UDMAP receive flow free descriptor queue for size 983 * threshold 2. 984 * @rx_fdq0_sz3_qnum: UDMAP receive flow free descriptor queue for size 985 * threshold 3. 986 * 987 * For detailed information on the settings, see the UDMAP section of the TRM. 988 */ 989struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg { 990 struct ti_sci_msg_hdr hdr; 991 u32 nav_id; 992 u32 flow_index; 993 u32 rx_ch_index; 994 u16 rx_size_thresh0; 995 u16 rx_size_thresh1; 996 u16 rx_size_thresh2; 997 u16 rx_fdq0_sz1_qnum; 998 u16 rx_fdq0_sz2_qnum; 999 u16 rx_fdq0_sz3_qnum; 1000} __packed; 1001 1002/** 1003 * Configures a Navigator Subsystem UDMAP transmit channel 1004 * 1005 * Configures the non-real-time registers of a Navigator Subsystem UDMAP 1006 * transmit channel. The channel index must be assigned to the host defined 1007 * in the TISCI header via the RM board configuration resource assignment 1008 * range list. 1009 * 1010 * @hdr: Generic Header 1011 * 1012 * @valid_params: Bitfield defining validity of tx channel configuration 1013 * parameters. The tx channel configuration fields are not valid, and will not 1014 * be used for ch configuration, if their corresponding valid bit is zero. 1015 * Valid bit usage: 1016 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err 1017 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype 1018 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type 1019 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size 1020 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum 1021 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority 1022 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos 1023 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid 1024 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority 1025 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo 1026 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords 1027 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt 1028 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count 1029 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth 1030 * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size 1031 * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype 1032 * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type 1033 * 1034 * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located 1035 * 1036 * @index: UDMAP transmit channel index. 1037 * 1038 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to 1039 * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG 1040 * register. 1041 * 1042 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing 1043 * configuration to be programmed into the tx_filt_einfo field of the 1044 * channel's TCHAN_TCFG register. 1045 * 1046 * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing 1047 * configuration to be programmed into the tx_filt_pswords field of the 1048 * channel's TCHAN_TCFG register. 1049 * 1050 * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer 1051 * interpretation configuration to be programmed into the tx_atype field of 1052 * the channel's TCHAN_TCFG register. 1053 * 1054 * @tx_chan_type: UDMAP transmit channel functional channel type and work 1055 * passing mechanism configuration to be programmed into the tx_chan_type 1056 * field of the channel's TCHAN_TCFG register. 1057 * 1058 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression 1059 * configuration to be programmed into the tx_supr_tdpkt field of the channel's 1060 * TCHAN_TCFG register. 1061 * 1062 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to 1063 * fetch configuration to be programmed into the tx_fetch_size field of the 1064 * channel's TCHAN_TCFG register. The user must make sure to set the maximum 1065 * word count that can pass through the channel for any allowed descriptor type. 1066 * 1067 * @tx_credit_count: UDMAP transmit channel transfer request credit count 1068 * configuration to be programmed into the count field of the TCHAN_TCREDIT 1069 * register. Specifies how many credits for complete TRs are available. 1070 * 1071 * @txcq_qnum: UDMAP transmit channel completion queue configuration to be 1072 * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified 1073 * completion queue must be assigned to the host, or a subordinate of the host, 1074 * requesting configuration of the transmit channel. 1075 * 1076 * @tx_priority: UDMAP transmit channel transmit priority value to be programmed 1077 * into the priority field of the channel's TCHAN_TPRI_CTRL register. 1078 * 1079 * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the 1080 * qos field of the channel's TCHAN_TPRI_CTRL register. 1081 * 1082 * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into 1083 * the orderid field of the channel's TCHAN_TPRI_CTRL register. 1084 * 1085 * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed 1086 * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of 1087 * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP 1088 * section of the TRM for restrictions regarding this parameter. 1089 * 1090 * @tx_sched_priority: UDMAP transmit channel tx scheduling priority 1091 * configuration to be programmed into the priority field of the channel's 1092 * TCHAN_TST_SCHED register. 1093 * 1094 * @tx_burst_size: UDMAP transmit channel burst size configuration to be 1095 * programmed into the tx_burst_size field of the TCHAN_TCFG register. 1096 * 1097 * @tx_tdtype: UDMAP transmit channel teardown type configuration to be 1098 * programmed into the tdtype field of the TCHAN_TCFG register: 1099 * 0 - Return immediately 1100 * 1 - Wait for completion message from remote peer 1101 * 1102 * @extended_ch_type: Valid for BCDMA. 1103 * 0 - the channel is split tx channel (tchan) 1104 * 1 - the channel is block copy channel (bchan) 1105 */ 1106struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { 1107 struct ti_sci_msg_hdr hdr; 1108 u32 valid_params; 1109 u16 nav_id; 1110 u16 index; 1111 u8 tx_pause_on_err; 1112 u8 tx_filt_einfo; 1113 u8 tx_filt_pswords; 1114 u8 tx_atype; 1115 u8 tx_chan_type; 1116 u8 tx_supr_tdpkt; 1117 u16 tx_fetch_size; 1118 u8 tx_credit_count; 1119 u16 txcq_qnum; 1120 u8 tx_priority; 1121 u8 tx_qos; 1122 u8 tx_orderid; 1123 u16 fdepth; 1124 u8 tx_sched_priority; 1125 u8 tx_burst_size; 1126 u8 tx_tdtype; 1127 u8 extended_ch_type; 1128} __packed; 1129 1130/** 1131 * Configures a Navigator Subsystem UDMAP receive channel 1132 * 1133 * Configures the non-real-time registers of a Navigator Subsystem UDMAP 1134 * receive channel. The channel index must be assigned to the host defined 1135 * in the TISCI header via the RM board configuration resource assignment 1136 * range list. 1137 * 1138 * @hdr: Generic Header 1139 * 1140 * @valid_params: Bitfield defining validity of rx channel configuration 1141 * parameters. 1142 * The rx channel configuration fields are not valid, and will not be used for 1143 * ch configuration, if their corresponding valid bit is zero. 1144 * Valid bit usage: 1145 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err 1146 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype 1147 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type 1148 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size 1149 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum 1150 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority 1151 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos 1152 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid 1153 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority 1154 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start 1155 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt 1156 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short 1157 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long 1158 * 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size 1159 * 1160 * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located 1161 * 1162 * @index: UDMAP receive channel index. 1163 * 1164 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to 1165 * fetch configuration to be programmed into the rx_fetch_size field of the 1166 * channel's RCHAN_RCFG register. 1167 * 1168 * @rxcq_qnum: UDMAP receive channel completion queue configuration to be 1169 * programmed into the rxcq_qnum field of the RCHAN_RCQ register. 1170 * The specified completion queue must be assigned to the host, or a subordinate 1171 * of the host, requesting configuration of the receive channel. 1172 * 1173 * @rx_priority: UDMAP receive channel receive priority value to be programmed 1174 * into the priority field of the channel's RCHAN_RPRI_CTRL register. 1175 * 1176 * @rx_qos: UDMAP receive channel receive qos value to be programmed into the 1177 * qos field of the channel's RCHAN_RPRI_CTRL register. 1178 * 1179 * @rx_orderid: UDMAP receive channel bus order id value to be programmed into 1180 * the orderid field of the channel's RCHAN_RPRI_CTRL register. 1181 * 1182 * @rx_sched_priority: UDMAP receive channel rx scheduling priority 1183 * configuration to be programmed into the priority field of the channel's 1184 * RCHAN_RST_SCHED register. 1185 * 1186 * @flowid_start: UDMAP receive channel additional flows starting index 1187 * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG 1188 * register. Specifies the starting index for flow IDs the receive channel is to 1189 * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be 1190 * set as valid and configured together. The starting flow ID set by 1191 * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset 1192 * of flows beyond the default flows statically mapped to receive channels. 1193 * The additional flows must be assigned to the host, or a subordinate of the 1194 * host, requesting configuration of the receive channel. 1195 * 1196 * @flowid_cnt: UDMAP receive channel additional flows count configuration to 1197 * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register. 1198 * This field specifies how many flow IDs are in the additional contiguous range 1199 * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be 1200 * set as valid and configured together. Disabling the valid_params field bit 1201 * for flowid_cnt indicates no flow IDs other than the default are to be 1202 * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt 1203 * cannot be greater than the number of receive flows in the receive channel's 1204 * Navigator Subsystem. The additional flows must be assigned to the host, or a 1205 * subordinate of the host, requesting configuration of the receive channel. 1206 * 1207 * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be 1208 * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG 1209 * register. 1210 * 1211 * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer 1212 * interpretation configuration to be programmed into the rx_atype field of the 1213 * channel's RCHAN_RCFG register. 1214 * 1215 * @rx_chan_type: UDMAP receive channel functional channel type and work passing 1216 * mechanism configuration to be programmed into the rx_chan_type field of the 1217 * channel's RCHAN_RCFG register. 1218 * 1219 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration 1220 * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register. 1221 * 1222 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to 1223 * be programmed into the rx_ignore_long field of the RCHAN_RCFG register. 1224 * 1225 * @rx_burst_size: UDMAP receive channel burst size configuration to be 1226 * programmed into the rx_burst_size field of the RCHAN_RCFG register. 1227 */ 1228struct ti_sci_msg_rm_udmap_rx_ch_cfg_req { 1229 struct ti_sci_msg_hdr hdr; 1230 u32 valid_params; 1231 u16 nav_id; 1232 u16 index; 1233 u16 rx_fetch_size; 1234 u16 rxcq_qnum; 1235 u8 rx_priority; 1236 u8 rx_qos; 1237 u8 rx_orderid; 1238 u8 rx_sched_priority; 1239 u16 flowid_start; 1240 u16 flowid_cnt; 1241 u8 rx_pause_on_err; 1242 u8 rx_atype; 1243 u8 rx_chan_type; 1244 u8 rx_ignore_short; 1245 u8 rx_ignore_long; 1246 u8 rx_burst_size; 1247} __packed; 1248 1249/** 1250 * Configures a Navigator Subsystem UDMAP receive flow 1251 * 1252 * Configures a Navigator Subsystem UDMAP receive flow's registers. 1253 * Configuration does not include the flow registers which handle size-based 1254 * free descriptor queue routing. 1255 * 1256 * The flow index must be assigned to the host defined in the TISCI header via 1257 * the RM board configuration resource assignment range list. 1258 * 1259 * @hdr: Standard TISCI header 1260 * 1261 * @valid_params 1262 * Bitfield defining validity of rx flow configuration parameters. The 1263 * rx flow configuration fields are not valid, and will not be used for flow 1264 * configuration, if their corresponding valid bit is zero. Valid bit usage: 1265 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present 1266 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present 1267 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling 1268 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type 1269 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset 1270 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum 1271 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi 1272 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo 1273 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi 1274 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo 1275 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel 1276 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel 1277 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel 1278 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel 1279 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum 1280 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum 1281 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum 1282 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum 1283 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location 1284 * 1285 * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is 1286 * allocated 1287 * 1288 * @flow_index: UDMAP receive flow index for non-optional configuration. 1289 * 1290 * @rx_einfo_present: 1291 * UDMAP receive flow extended packet info present configuration to be 1292 * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register. 1293 * 1294 * @rx_psinfo_present: 1295 * UDMAP receive flow PS words present configuration to be programmed into the 1296 * rx_psinfo_present field of the flow's RFLOW_RFA register. 1297 * 1298 * @rx_error_handling: 1299 * UDMAP receive flow error handling configuration to be programmed into the 1300 * rx_error_handling field of the flow's RFLOW_RFA register. 1301 * 1302 * @rx_desc_type: 1303 * UDMAP receive flow descriptor type configuration to be programmed into the 1304 * rx_desc_type field field of the flow's RFLOW_RFA register. 1305 * 1306 * @rx_sop_offset: 1307 * UDMAP receive flow start of packet offset configuration to be programmed 1308 * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP 1309 * section of the TRM for more information on this setting. Valid values for 1310 * this field are 0-255 bytes. 1311 * 1312 * @rx_dest_qnum: 1313 * UDMAP receive flow destination queue configuration to be programmed into the 1314 * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified 1315 * destination queue must be valid within the Navigator Subsystem and must be 1316 * owned by the host, or a subordinate of the host, requesting allocation and 1317 * configuration of the receive flow. 1318 * 1319 * @rx_src_tag_hi: 1320 * UDMAP receive flow source tag high byte constant configuration to be 1321 * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register. 1322 * See the UDMAP section of the TRM for more information on this setting. 1323 * 1324 * @rx_src_tag_lo: 1325 * UDMAP receive flow source tag low byte constant configuration to be 1326 * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register. 1327 * See the UDMAP section of the TRM for more information on this setting. 1328 * 1329 * @rx_dest_tag_hi: 1330 * UDMAP receive flow destination tag high byte constant configuration to be 1331 * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register. 1332 * See the UDMAP section of the TRM for more information on this setting. 1333 * 1334 * @rx_dest_tag_lo: 1335 * UDMAP receive flow destination tag low byte constant configuration to be 1336 * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register. 1337 * See the UDMAP section of the TRM for more information on this setting. 1338 * 1339 * @rx_src_tag_hi_sel: 1340 * UDMAP receive flow source tag high byte selector configuration to be 1341 * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See 1342 * the UDMAP section of the TRM for more information on this setting. 1343 * 1344 * @rx_src_tag_lo_sel: 1345 * UDMAP receive flow source tag low byte selector configuration to be 1346 * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See 1347 * the UDMAP section of the TRM for more information on this setting. 1348 * 1349 * @rx_dest_tag_hi_sel: 1350 * UDMAP receive flow destination tag high byte selector configuration to be 1351 * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See 1352 * the UDMAP section of the TRM for more information on this setting. 1353 * 1354 * @rx_dest_tag_lo_sel: 1355 * UDMAP receive flow destination tag low byte selector configuration to be 1356 * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See 1357 * the UDMAP section of the TRM for more information on this setting. 1358 * 1359 * @rx_fdq0_sz0_qnum: 1360 * UDMAP receive flow free descriptor queue 0 configuration to be programmed 1361 * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the 1362 * UDMAP section of the TRM for more information on this setting. The specified 1363 * free queue must be valid within the Navigator Subsystem and must be owned 1364 * by the host, or a subordinate of the host, requesting allocation and 1365 * configuration of the receive flow. 1366 * 1367 * @rx_fdq1_qnum: 1368 * UDMAP receive flow free descriptor queue 1 configuration to be programmed 1369 * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the 1370 * UDMAP section of the TRM for more information on this setting. The specified 1371 * free queue must be valid within the Navigator Subsystem and must be owned 1372 * by the host, or a subordinate of the host, requesting allocation and 1373 * configuration of the receive flow. 1374 * 1375 * @rx_fdq2_qnum: 1376 * UDMAP receive flow free descriptor queue 2 configuration to be programmed 1377 * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the 1378 * UDMAP section of the TRM for more information on this setting. The specified 1379 * free queue must be valid within the Navigator Subsystem and must be owned 1380 * by the host, or a subordinate of the host, requesting allocation and 1381 * configuration of the receive flow. 1382 * 1383 * @rx_fdq3_qnum: 1384 * UDMAP receive flow free descriptor queue 3 configuration to be programmed 1385 * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the 1386 * UDMAP section of the TRM for more information on this setting. The specified 1387 * free queue must be valid within the Navigator Subsystem and must be owned 1388 * by the host, or a subordinate of the host, requesting allocation and 1389 * configuration of the receive flow. 1390 * 1391 * @rx_ps_location: 1392 * UDMAP receive flow PS words location configuration to be programmed into the 1393 * rx_ps_location field of the flow's RFLOW_RFA register. 1394 */ 1395struct ti_sci_msg_rm_udmap_flow_cfg_req { 1396 struct ti_sci_msg_hdr hdr; 1397 u32 valid_params; 1398 u16 nav_id; 1399 u16 flow_index; 1400 u8 rx_einfo_present; 1401 u8 rx_psinfo_present; 1402 u8 rx_error_handling; 1403 u8 rx_desc_type; 1404 u16 rx_sop_offset; 1405 u16 rx_dest_qnum; 1406 u8 rx_src_tag_hi; 1407 u8 rx_src_tag_lo; 1408 u8 rx_dest_tag_hi; 1409 u8 rx_dest_tag_lo; 1410 u8 rx_src_tag_hi_sel; 1411 u8 rx_src_tag_lo_sel; 1412 u8 rx_dest_tag_hi_sel; 1413 u8 rx_dest_tag_lo_sel; 1414 u16 rx_fdq0_sz0_qnum; 1415 u16 rx_fdq1_qnum; 1416 u16 rx_fdq2_qnum; 1417 u16 rx_fdq3_qnum; 1418 u8 rx_ps_location; 1419} __packed; 1420 1421/** 1422 * struct ti_sci_msg_req_proc_request - Request a processor 1423 * @hdr: Generic Header 1424 * @processor_id: ID of processor being requested 1425 * 1426 * Request type is TI_SCI_MSG_PROC_REQUEST, response is a generic ACK/NACK 1427 * message. 1428 */ 1429struct ti_sci_msg_req_proc_request { 1430 struct ti_sci_msg_hdr hdr; 1431 u8 processor_id; 1432} __packed; 1433 1434/** 1435 * struct ti_sci_msg_req_proc_release - Release a processor 1436 * @hdr: Generic Header 1437 * @processor_id: ID of processor being released 1438 * 1439 * Request type is TI_SCI_MSG_PROC_RELEASE, response is a generic ACK/NACK 1440 * message. 1441 */ 1442struct ti_sci_msg_req_proc_release { 1443 struct ti_sci_msg_hdr hdr; 1444 u8 processor_id; 1445} __packed; 1446 1447/** 1448 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host 1449 * @hdr: Generic Header 1450 * @processor_id: ID of processor being handed over 1451 * @host_id: Host ID the control needs to be transferred to 1452 * 1453 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 1454 * message. 1455 */ 1456struct ti_sci_msg_req_proc_handover { 1457 struct ti_sci_msg_hdr hdr; 1458 u8 processor_id; 1459 u8 host_id; 1460} __packed; 1461 1462/* Boot Vector masks */ 1463#define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0) 1464#define TI_SCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32) 1465#define TI_SCI_ADDR_HIGH_SHIFT 32 1466 1467/** 1468 * struct ti_sci_msg_req_set_config - Set Processor boot configuration 1469 * @hdr: Generic Header 1470 * @processor_id: ID of processor being configured 1471 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector 1472 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector 1473 * @config_flags_set: Optional Processor specific Config Flags to set. 1474 * Setting a bit here implies the corresponding mode 1475 * will be set 1476 * @config_flags_clear: Optional Processor specific Config Flags to clear. 1477 * Setting a bit here implies the corresponding mode 1478 * will be cleared 1479 * 1480 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 1481 * message. 1482 */ 1483struct ti_sci_msg_req_set_config { 1484 struct ti_sci_msg_hdr hdr; 1485 u8 processor_id; 1486 u32 bootvector_low; 1487 u32 bootvector_high; 1488 u32 config_flags_set; 1489 u32 config_flags_clear; 1490} __packed; 1491 1492/** 1493 * struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags 1494 * @hdr: Generic Header 1495 * @processor_id: ID of processor being configured 1496 * @control_flags_set: Optional Processor specific Control Flags to set. 1497 * Setting a bit here implies the corresponding mode 1498 * will be set 1499 * @control_flags_clear:Optional Processor specific Control Flags to clear. 1500 * Setting a bit here implies the corresponding mode 1501 * will be cleared 1502 * 1503 * Request type is TI_SCI_MSG_SET_CTRL, response is a generic ACK/NACK 1504 * message. 1505 */ 1506struct ti_sci_msg_req_set_ctrl { 1507 struct ti_sci_msg_hdr hdr; 1508 u8 processor_id; 1509 u32 control_flags_set; 1510 u32 control_flags_clear; 1511} __packed; 1512 1513/** 1514 * struct ti_sci_msg_req_get_status - Processor boot status request 1515 * @hdr: Generic Header 1516 * @processor_id: ID of processor whose status is being requested 1517 * 1518 * Request type is TI_SCI_MSG_GET_STATUS, response is an appropriate 1519 * message, or NACK in case of inability to satisfy request. 1520 */ 1521struct ti_sci_msg_req_get_status { 1522 struct ti_sci_msg_hdr hdr; 1523 u8 processor_id; 1524} __packed; 1525 1526/** 1527 * struct ti_sci_msg_resp_get_status - Processor boot status response 1528 * @hdr: Generic Header 1529 * @processor_id: ID of processor whose status is returned 1530 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector 1531 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector 1532 * @config_flags: Optional Processor specific Config Flags set currently 1533 * @control_flags: Optional Processor specific Control Flags set currently 1534 * @status_flags: Optional Processor specific Status Flags set currently 1535 * 1536 * Response structure to a TI_SCI_MSG_GET_STATUS request. 1537 */ 1538struct ti_sci_msg_resp_get_status { 1539 struct ti_sci_msg_hdr hdr; 1540 u8 processor_id; 1541 u32 bootvector_low; 1542 u32 bootvector_high; 1543 u32 config_flags; 1544 u32 control_flags; 1545 u32 status_flags; 1546} __packed; 1547 1548#endif /* __TI_SCI_H */
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