init_ohci1394_dma.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * init_ohci1394_dma.c - Initializes physical DMA on all OHCI 1394 controllers
  4 *
  5 * Copyright (C) 2006-2007      Bernhard Kaindl <bk@suse.de>
  6 *
  7 * Derived from drivers/ieee1394/ohci1394.c and arch/x86/kernel/early-quirks.c
  8 * this file has functions to:
  9 * - scan the PCI very early on boot for all OHCI 1394-compliant controllers
 10 * - reset and initialize them and make them join the IEEE1394 bus and
 11 * - enable physical DMA on them to allow remote debugging
 12 *
 13 * All code and data is marked as __init and __initdata, respective as
 14 * during boot, all OHCI1394 controllers may be claimed by the firewire
 15 * stack and at this point, this code should not touch them anymore.
 16 *
 17 * To use physical DMA after the initialization of the firewire stack,
 18 * be sure that the stack enables it and (re-)attach after the bus reset
 19 * which may be caused by the firewire stack initialization.
 20 */
 21
 22#include <linux/delay.h>
 23#include <linux/io.h>
 24#include <linux/kernel.h>
 25#include <linux/pci.h>		/* for PCI defines */
 26#include <linux/string.h>
 27
 28#include <asm/pci-direct.h>	/* for direct PCI config space access */
 29#include <asm/fixmap.h>
 30
 31#include <linux/init_ohci1394_dma.h>
 32#include "ohci.h"
 33
 34int __initdata init_ohci1394_dma_early;
 35
 36struct ohci {
 37	void __iomem *registers;
 38};
 39
 40static inline void reg_write(const struct ohci *ohci, int offset, u32 data)
 41{
 42	writel(data, ohci->registers + offset);
 43}
 44
 45static inline u32 reg_read(const struct ohci *ohci, int offset)
 46{
 47	return readl(ohci->registers + offset);
 48}
 49
 50#define OHCI_LOOP_COUNT		100	/* Number of loops for reg read waits */
 51
 52/* Reads a PHY register of an OHCI-1394 controller */
 53static inline u8 __init get_phy_reg(struct ohci *ohci, u8 addr)
 54{
 55	int i;
 56	u32 r;
 57
 58	reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
 59
 60	for (i = 0; i < OHCI_LOOP_COUNT; i++) {
 61		if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
 62			break;
 63		mdelay(1);
 64	}
 65	r = reg_read(ohci, OHCI1394_PhyControl);
 66
 67	return (r & 0x00ff0000) >> 16;
 68}
 69
 70/* Writes to a PHY register of an OHCI-1394 controller */
 71static inline void __init set_phy_reg(struct ohci *ohci, u8 addr, u8 data)
 72{
 73	int i;
 74
 75	reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
 76
 77	for (i = 0; i < OHCI_LOOP_COUNT; i++) {
 78		if (!(reg_read(ohci, OHCI1394_PhyControl) & 0x00004000))
 79			break;
 80		mdelay(1);
 81	}
 82}
 83
 84/* Resets an OHCI-1394 controller (for sane state before initialization) */
 85static inline void __init init_ohci1394_soft_reset(struct ohci *ohci)
 86{
 87	int i;
 88
 89	reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
 90
 91	for (i = 0; i < OHCI_LOOP_COUNT; i++) {
 92		if (!(reg_read(ohci, OHCI1394_HCControlSet)
 93				   & OHCI1394_HCControl_softReset))
 94			break;
 95		mdelay(1);
 96	}
 97}
 98
 99#define OHCI1394_MAX_AT_REQ_RETRIES	0xf
100#define OHCI1394_MAX_AT_RESP_RETRIES	0x2
101#define OHCI1394_MAX_PHYS_RESP_RETRIES	0x8
102
103/* Basic OHCI-1394 register and port inititalization */
104static inline void __init init_ohci1394_initialize(struct ohci *ohci)
105{
106	u32 bus_options;
107	int num_ports, i;
108
109	/* Put some defaults to these undefined bus options */
110	bus_options = reg_read(ohci, OHCI1394_BusOptions);
111	bus_options |=  0x60000000; /* Enable CMC and ISC */
112	bus_options &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
113	bus_options &= ~0x18000000; /* Disable PMC and BMC */
114	reg_write(ohci, OHCI1394_BusOptions, bus_options);
115
116	/* Set the bus number */
117	reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
118
119	/* Enable posted writes */
120	reg_write(ohci, OHCI1394_HCControlSet,
121			OHCI1394_HCControl_postedWriteEnable);
122
123	/* Clear link control register */
124	reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
125
126	/* enable phys */
127	reg_write(ohci, OHCI1394_LinkControlSet,
128			OHCI1394_LinkControl_rcvPhyPkt);
129
130	/* Don't accept phy packets into AR request context */
131	reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
132
133	/* Clear the Isochonouys interrupt masks */
134	reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
135	reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
136	reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
137	reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
138
139	/* Accept asynchronous transfer requests from all nodes for now */
140	reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
141
142	/* Specify asynchronous transfer retries */
143	reg_write(ohci, OHCI1394_ATRetries,
144		  OHCI1394_MAX_AT_REQ_RETRIES |
145		  (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
146		  (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
147
148	/* We don't want hardware swapping */
149	reg_write(ohci, OHCI1394_HCControlClear,
150		  OHCI1394_HCControl_noByteSwapData);
151
152	/* Enable link */
153	reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
154
155	/* If anything is connected to a port, make sure it is enabled */
156	num_ports = get_phy_reg(ohci, 2) & 0xf;
157	for (i = 0; i < num_ports; i++) {
158		unsigned int status;
159
160		set_phy_reg(ohci, 7, i);
161		status = get_phy_reg(ohci, 8);
162
163		if (status & 0x20)
164			set_phy_reg(ohci, 8, status & ~1);
165	}
166}
167
168/**
169 * init_ohci1394_wait_for_busresets - wait until bus resets are completed
170 * @ohci: Pointer to the OHCI-1394 controller structure
171 *
172 * OHCI1394 initialization itself and any device going on- or offline
173 * and any cable issue cause a IEEE1394 bus reset. The OHCI1394 spec
174 * specifies that physical DMA is disabled on each bus reset and it
175 * has to be enabled after each bus reset when needed. We resort
176 * to polling here because on early boot, we have no interrupts.
177 */
178static inline void __init init_ohci1394_wait_for_busresets(struct ohci *ohci)
179{
180	int i, events;
181
182	for (i = 0; i < 9; i++) {
183		mdelay(200);
184		events = reg_read(ohci, OHCI1394_IntEventSet);
185		if (events & OHCI1394_busReset)
186			reg_write(ohci, OHCI1394_IntEventClear,
187					OHCI1394_busReset);
188	}
189}
190
191/**
192 * init_ohci1394_enable_physical_dma - Enable physical DMA for remote debugging
193 * @ohci: Pointer to the OHCI-1394 controller structure
194 *
195 * This enables remote DMA access over IEEE1394 from every host for the low
196 * 4GB of address space. DMA accesses above 4GB are not available currently.
197 */
198static inline void __init init_ohci1394_enable_physical_dma(struct ohci *ohci)
199{
200	reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 0xffffffff);
201	reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 0xffffffff);
202	reg_write(ohci, OHCI1394_PhyUpperBound, 0xffff0000);
203}
204
205/**
206 * init_ohci1394_reset_and_init_dma - init controller and enable DMA
207 * @ohci: Pointer to the OHCI-1394 controller structure
208 *
209 * This initializes the given controller and enables physical DMA engine in it.
210 */
211static inline void __init init_ohci1394_reset_and_init_dma(struct ohci *ohci)
212{
213	/* Start off with a soft reset, clears everything to a sane state. */
214	init_ohci1394_soft_reset(ohci);
215
216	/* Accessing some registers without LPS enabled may cause lock up */
217	reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
218
219	/* Disable and clear interrupts */
220	reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
221	reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
222
223	mdelay(50); /* Wait 50msec to make sure we have full link enabled */
224
225	init_ohci1394_initialize(ohci);
226	/*
227	 * The initialization causes at least one IEEE1394 bus reset. Enabling
228	 * physical DMA only works *after* *all* bus resets have calmed down:
229	 */
230	init_ohci1394_wait_for_busresets(ohci);
231
232	/* We had to wait and do this now if we want to debug early problems */
233	init_ohci1394_enable_physical_dma(ohci);
234}
235
236/**
237 * init_ohci1394_controller - Map the registers of the controller and init DMA
238 * @num: PCI bus number
239 * @slot: PCI device number
240 * @func: PCI function number
241 *
242 * This maps the registers of the specified controller and initializes it
243 */
244static inline void __init init_ohci1394_controller(int num, int slot, int func)
245{
246	unsigned long ohci_base;
247	struct ohci ohci;
248
249	printk(KERN_INFO "init_ohci1394_dma: initializing OHCI-1394"
250			 " at %02x:%02x.%x\n", num, slot, func);
251
252	ohci_base = read_pci_config(num, slot, func, PCI_BASE_ADDRESS_0+(0<<2))
253						   & PCI_BASE_ADDRESS_MEM_MASK;
254
255	set_fixmap_nocache(FIX_OHCI1394_BASE, ohci_base);
256
257	ohci.registers = (void __iomem *)fix_to_virt(FIX_OHCI1394_BASE);
258
259	init_ohci1394_reset_and_init_dma(&ohci);
260}
261
262/**
263 * init_ohci1394_dma_on_all_controllers - scan for OHCI1394 controllers and init DMA on them
264 * Scans the whole PCI space for OHCI1394 controllers and inits DMA on them
265 */
266void __init init_ohci1394_dma_on_all_controllers(void)
267{
268	int num, slot, func;
269	u32 class;
270
271	if (!early_pci_allowed())
272		return;
273
274	/* Poor man's PCI discovery, the only thing we can do at early boot */
275	for (num = 0; num < 32; num++) {
276		for (slot = 0; slot < 32; slot++) {
277			for (func = 0; func < 8; func++) {
278				class = read_pci_config(num, slot, func,
279							PCI_CLASS_REVISION);
280				if (class == 0xffffffff)
281					continue; /* No device at this func */
282
283				if (class>>8 != PCI_CLASS_SERIAL_FIREWIRE_OHCI)
284					continue; /* Not an OHCI-1394 device */
285
286				init_ohci1394_controller(num, slot, func);
287				break; /* Assume one controller per device */
288			}
289		}
290	}
291	printk(KERN_INFO "init_ohci1394_dma: finished initializing OHCI DMA\n");
292}
293
294/**
295 * setup_ohci1394_dma - enables early OHCI1394 DMA initialization
296 * @opt: Kernel command line parameter string
297 */
298static int __init setup_ohci1394_dma(char *opt)
299{
300	if (!strcmp(opt, "early"))
301		init_ohci1394_dma_early = 1;
302	return 0;
303}
304
305/* passing ohci1394_dma=early on boot causes early OHCI1394 DMA initialization */
306early_param("ohci1394_dma", setup_ohci1394_dma);