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i5400_edac.c
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linux-6.19.14/drivers/edac/i5400_edac.c
1/* 2 * Intel 5400 class Memory Controllers kernel module (Seaburg) 3 * 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * Copyright (c) 2008 by: 8 * Ben Woodard <woodard@redhat.com> 9 * Mauro Carvalho Chehab 10 * 11 * Red Hat Inc. https://www.redhat.com 12 * 13 * Forked and adapted from the i5000_edac driver which was 14 * written by Douglas Thompson Linux Networx <norsk5@xmission.com> 15 * 16 * This module is based on the following document: 17 * 18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet 19 * http://developer.intel.com/design/chipsets/datashts/313070.htm 20 * 21 * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with 22 * 2 channels operating in lockstep no-mirror mode. Each channel can have up to 23 * 4 dimm's, each with up to 8GB. 24 * 25 */ 26 27#include <linux/module.h> 28#include <linux/init.h> 29#include <linux/pci.h> 30#include <linux/pci_ids.h> 31#include <linux/slab.h> 32#include <linux/edac.h> 33#include <linux/mmzone.h> 34#include <linux/string_choices.h> 35 36#include "edac_module.h" 37 38/* 39 * Alter this version for the I5400 module when modifications are made 40 */ 41#define I5400_REVISION " Ver: 1.0.0" 42 43#define EDAC_MOD_STR "i5400_edac" 44 45#define i5400_printk(level, fmt, arg...) \ 46 edac_printk(level, "i5400", fmt, ##arg) 47 48#define i5400_mc_printk(mci, level, fmt, arg...) \ 49 edac_mc_chipset_printk(mci, level, "i5400", fmt, ##arg) 50 51/* Limits for i5400 */ 52#define MAX_BRANCHES 2 53#define CHANNELS_PER_BRANCH 2 54#define DIMMS_PER_CHANNEL 4 55#define MAX_CHANNELS (MAX_BRANCHES * CHANNELS_PER_BRANCH) 56 57/* Device 16, 58 * Function 0: System Address 59 * Function 1: Memory Branch Map, Control, Errors Register 60 * Function 2: FSB Error Registers 61 * 62 * All 3 functions of Device 16 (0,1,2) share the SAME DID and 63 * uses PCI_DEVICE_ID_INTEL_5400_ERR for device 16 (0,1,2), 64 * PCI_DEVICE_ID_INTEL_5400_FBD0 and PCI_DEVICE_ID_INTEL_5400_FBD1 65 * for device 21 (0,1). 66 */ 67 68 /* OFFSETS for Function 0 */ 69#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ 70#define MAXCH 0x56 /* Max Channel Number */ 71#define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */ 72 73 /* OFFSETS for Function 1 */ 74#define TOLM 0x6C 75#define REDMEMB 0x7C 76#define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */ 77#define MIR0 0x80 78#define MIR1 0x84 79#define AMIR0 0x8c 80#define AMIR1 0x90 81 82 /* Fatal error registers */ 83#define FERR_FAT_FBD 0x98 /* also called as FERR_FAT_FB_DIMM at datasheet */ 84#define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */ 85 86#define NERR_FAT_FBD 0x9c 87#define FERR_NF_FBD 0xa0 /* also called as FERR_NFAT_FB_DIMM at datasheet */ 88 89 /* Non-fatal error register */ 90#define NERR_NF_FBD 0xa4 91 92 /* Enable error mask */ 93#define EMASK_FBD 0xa8 94 95#define ERR0_FBD 0xac 96#define ERR1_FBD 0xb0 97#define ERR2_FBD 0xb4 98#define MCERR_FBD 0xb8 99 100 /* No OFFSETS for Device 16 Function 2 */ 101 102/* 103 * Device 21, 104 * Function 0: Memory Map Branch 0 105 * 106 * Device 22, 107 * Function 0: Memory Map Branch 1 108 */ 109 110 /* OFFSETS for Function 0 */ 111#define AMBPRESENT_0 0x64 112#define AMBPRESENT_1 0x66 113#define MTR0 0x80 114#define MTR1 0x82 115#define MTR2 0x84 116#define MTR3 0x86 117 118 /* OFFSETS for Function 1 */ 119#define NRECFGLOG 0x74 120#define RECFGLOG 0x78 121#define NRECMEMA 0xbe 122#define NRECMEMB 0xc0 123#define NRECFB_DIMMA 0xc4 124#define NRECFB_DIMMB 0xc8 125#define NRECFB_DIMMC 0xcc 126#define NRECFB_DIMMD 0xd0 127#define NRECFB_DIMME 0xd4 128#define NRECFB_DIMMF 0xd8 129#define REDMEMA 0xdC 130#define RECMEMA 0xf0 131#define RECMEMB 0xf4 132#define RECFB_DIMMA 0xf8 133#define RECFB_DIMMB 0xec 134#define RECFB_DIMMC 0xf0 135#define RECFB_DIMMD 0xf4 136#define RECFB_DIMME 0xf8 137#define RECFB_DIMMF 0xfC 138 139/* 140 * Error indicator bits and masks 141 * Error masks are according with Table 5-17 of i5400 datasheet 142 */ 143 144enum error_mask { 145 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */ 146 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */ 147 EMASK_M3 = 1<<2, /* Reserved */ 148 EMASK_M4 = 1<<3, /* Uncorrectable Data ECC on Replay */ 149 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */ 150 EMASK_M6 = 1<<5, /* Unsupported on i5400 */ 151 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */ 152 EMASK_M8 = 1<<7, /* Aliased Uncorrectable Patrol Data ECC */ 153 EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */ 154 EMASK_M10 = 1<<9, /* Unsupported on i5400 */ 155 EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */ 156 EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */ 157 EMASK_M13 = 1<<12, /* Memory Write error on first attempt */ 158 EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */ 159 EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */ 160 EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */ 161 EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */ 162 EMASK_M18 = 1<<17, /* Unsupported on i5400 */ 163 EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */ 164 EMASK_M20 = 1<<19, /* Correctable Patrol Data ECC */ 165 EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */ 166 EMASK_M22 = 1<<21, /* SPD protocol Error */ 167 EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */ 168 EMASK_M24 = 1<<23, /* Refresh error */ 169 EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */ 170 EMASK_M26 = 1<<25, /* Redundant Fast Reset Timeout */ 171 EMASK_M27 = 1<<26, /* Correctable Counter Threshold Exceeded */ 172 EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */ 173 EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */ 174}; 175 176/* 177 * Names to translate bit error into something useful 178 */ 179static const char *error_name[] = { 180 [0] = "Memory Write error on non-redundant retry", 181 [1] = "Memory or FB-DIMM configuration CRC read error", 182 /* Reserved */ 183 [3] = "Uncorrectable Data ECC on Replay", 184 [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC", 185 /* M6 Unsupported on i5400 */ 186 [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", 187 [7] = "Aliased Uncorrectable Patrol Data ECC", 188 [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC", 189 /* M10 Unsupported on i5400 */ 190 [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", 191 [11] = "Non-Aliased Uncorrectable Patrol Data ECC", 192 [12] = "Memory Write error on first attempt", 193 [13] = "FB-DIMM Configuration Write error on first attempt", 194 [14] = "Memory or FB-DIMM configuration CRC read error", 195 [15] = "Channel Failed-Over Occurred", 196 [16] = "Correctable Non-Mirrored Demand Data ECC", 197 /* M18 Unsupported on i5400 */ 198 [18] = "Correctable Resilver- or Spare-Copy Data ECC", 199 [19] = "Correctable Patrol Data ECC", 200 [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status", 201 [21] = "SPD protocol Error", 202 [22] = "Non-Redundant Fast Reset Timeout", 203 [23] = "Refresh error", 204 [24] = "Memory Write error on redundant retry", 205 [25] = "Redundant Fast Reset Timeout", 206 [26] = "Correctable Counter Threshold Exceeded", 207 [27] = "DIMM-Spare Copy Completed", 208 [28] = "DIMM-Isolation Completed", 209}; 210 211/* Fatal errors */ 212#define ERROR_FAT_MASK (EMASK_M1 | \ 213 EMASK_M2 | \ 214 EMASK_M23) 215 216/* Correctable errors */ 217#define ERROR_NF_CORRECTABLE (EMASK_M27 | \ 218 EMASK_M20 | \ 219 EMASK_M19 | \ 220 EMASK_M18 | \ 221 EMASK_M17 | \ 222 EMASK_M16) 223#define ERROR_NF_DIMM_SPARE (EMASK_M29 | \ 224 EMASK_M28) 225#define ERROR_NF_SPD_PROTOCOL (EMASK_M22) 226#define ERROR_NF_NORTH_CRC (EMASK_M21) 227 228/* Recoverable errors */ 229#define ERROR_NF_RECOVERABLE (EMASK_M26 | \ 230 EMASK_M25 | \ 231 EMASK_M24 | \ 232 EMASK_M15 | \ 233 EMASK_M14 | \ 234 EMASK_M13 | \ 235 EMASK_M12 | \ 236 EMASK_M11 | \ 237 EMASK_M9 | \ 238 EMASK_M8 | \ 239 EMASK_M7 | \ 240 EMASK_M5) 241 242/* uncorrectable errors */ 243#define ERROR_NF_UNCORRECTABLE (EMASK_M4) 244 245/* mask to all non-fatal errors */ 246#define ERROR_NF_MASK (ERROR_NF_CORRECTABLE | \ 247 ERROR_NF_UNCORRECTABLE | \ 248 ERROR_NF_RECOVERABLE | \ 249 ERROR_NF_DIMM_SPARE | \ 250 ERROR_NF_SPD_PROTOCOL | \ 251 ERROR_NF_NORTH_CRC) 252 253/* 254 * Define error masks for the several registers 255 */ 256 257/* Enable all fatal and non fatal errors */ 258#define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK) 259 260/* mask for fatal error registers */ 261#define FERR_FAT_MASK ERROR_FAT_MASK 262 263/* masks for non-fatal error register */ 264static inline int to_nf_mask(unsigned int mask) 265{ 266 return (mask & EMASK_M29) | (mask >> 3); 267}; 268 269static inline int from_nf_ferr(unsigned int mask) 270{ 271 return (mask & EMASK_M29) | /* Bit 28 */ 272 (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */ 273}; 274 275#define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK) 276#define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE) 277#define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE) 278#define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL) 279#define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC) 280#define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE) 281#define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE) 282 283/* 284 * Defines to extract the various fields from the 285 * MTRx - Memory Technology Registers 286 */ 287#define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10)) 288#define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9)) 289#define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4) 290#define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4) 291#define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) 292#define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1) 293#define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) 294#define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) 295#define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) 296#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) 297#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) 298 299/* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */ 300static inline int extract_fbdchan_indx(u32 x) 301{ 302 return (x>>28) & 0x3; 303} 304 305/* Device name and register DID (Device ID) */ 306struct i5400_dev_info { 307 const char *ctl_name; /* name for this device */ 308 u16 fsb_mapping_errors; /* DID for the branchmap,control */ 309}; 310 311/* Table of devices attributes supported by this driver */ 312static const struct i5400_dev_info i5400_devs[] = { 313 { 314 .ctl_name = "I5400", 315 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_5400_ERR, 316 }, 317}; 318 319struct i5400_dimm_info { 320 int megabytes; /* size, 0 means not present */ 321}; 322 323/* driver private data structure */ 324struct i5400_pvt { 325 struct pci_dev *system_address; /* 16.0 */ 326 struct pci_dev *branchmap_werrors; /* 16.1 */ 327 struct pci_dev *fsb_error_regs; /* 16.2 */ 328 struct pci_dev *branch_0; /* 21.0 */ 329 struct pci_dev *branch_1; /* 22.0 */ 330 331 u16 tolm; /* top of low memory */ 332 union { 333 u64 ambase; /* AMB BAR */ 334 struct { 335 u32 ambase_bottom; 336 u32 ambase_top; 337 } u __packed; 338 }; 339 340 u16 mir0, mir1; 341 342 u16 b0_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */ 343 u16 b0_ambpresent0; /* Branch 0, Channel 0 */ 344 u16 b0_ambpresent1; /* Brnach 0, Channel 1 */ 345 346 u16 b1_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */ 347 u16 b1_ambpresent0; /* Branch 1, Channel 8 */ 348 u16 b1_ambpresent1; /* Branch 1, Channel 1 */ 349 350 /* DIMM information matrix, allocating architecture maximums */ 351 struct i5400_dimm_info dimm_info[DIMMS_PER_CHANNEL][MAX_CHANNELS]; 352 353 /* Actual values for this controller */ 354 int maxch; /* Max channels */ 355 int maxdimmperch; /* Max DIMMs per channel */ 356}; 357 358/* I5400 MCH error information retrieved from Hardware */ 359struct i5400_error_info { 360 /* These registers are always read from the MC */ 361 u32 ferr_fat_fbd; /* First Errors Fatal */ 362 u32 nerr_fat_fbd; /* Next Errors Fatal */ 363 u32 ferr_nf_fbd; /* First Errors Non-Fatal */ 364 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */ 365 366 /* These registers are input ONLY if there was a Recoverable Error */ 367 u32 redmemb; /* Recoverable Mem Data Error log B */ 368 u16 recmema; /* Recoverable Mem Error log A */ 369 u32 recmemb; /* Recoverable Mem Error log B */ 370 371 /* These registers are input ONLY if there was a Non-Rec Error */ 372 u16 nrecmema; /* Non-Recoverable Mem log A */ 373 u32 nrecmemb; /* Non-Recoverable Mem log B */ 374 375}; 376 377/* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and 378 5400 better to use an inline function than a macro in this case */ 379static inline int nrec_bank(struct i5400_error_info *info) 380{ 381 return ((info->nrecmema) >> 12) & 0x7; 382} 383static inline int nrec_rank(struct i5400_error_info *info) 384{ 385 return ((info->nrecmema) >> 8) & 0xf; 386} 387static inline int nrec_buf_id(struct i5400_error_info *info) 388{ 389 return ((info->nrecmema)) & 0xff; 390} 391static inline int nrec_rdwr(struct i5400_error_info *info) 392{ 393 return (info->nrecmemb) >> 31; 394} 395/* This applies to both NREC and REC string so it can be used with nrec_rdwr 396 and rec_rdwr */ 397static inline const char *rdwr_str(int rdwr) 398{ 399 return rdwr ? "Write" : "Read"; 400} 401static inline int nrec_cas(struct i5400_error_info *info) 402{ 403 return ((info->nrecmemb) >> 16) & 0x1fff; 404} 405static inline int nrec_ras(struct i5400_error_info *info) 406{ 407 return (info->nrecmemb) & 0xffff; 408} 409static inline int rec_bank(struct i5400_error_info *info) 410{ 411 return ((info->recmema) >> 12) & 0x7; 412} 413static inline int rec_rank(struct i5400_error_info *info) 414{ 415 return ((info->recmema) >> 8) & 0xf; 416} 417static inline int rec_rdwr(struct i5400_error_info *info) 418{ 419 return (info->recmemb) >> 31; 420} 421static inline int rec_cas(struct i5400_error_info *info) 422{ 423 return ((info->recmemb) >> 16) & 0x1fff; 424} 425static inline int rec_ras(struct i5400_error_info *info) 426{ 427 return (info->recmemb) & 0xffff; 428} 429 430static struct edac_pci_ctl_info *i5400_pci; 431 432/* 433 * i5400_get_error_info Retrieve the hardware error information from 434 * the hardware and cache it in the 'info' 435 * structure 436 */ 437static void i5400_get_error_info(struct mem_ctl_info *mci, 438 struct i5400_error_info *info) 439{ 440 struct i5400_pvt *pvt; 441 u32 value; 442 443 pvt = mci->pvt_info; 444 445 /* read in the 1st FATAL error register */ 446 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); 447 448 /* Mask only the bits that the doc says are valid 449 */ 450 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK); 451 452 /* If there is an error, then read in the 453 NEXT FATAL error register and the Memory Error Log Register A 454 */ 455 if (value & FERR_FAT_MASK) { 456 info->ferr_fat_fbd = value; 457 458 /* harvest the various error data we need */ 459 pci_read_config_dword(pvt->branchmap_werrors, 460 NERR_FAT_FBD, &info->nerr_fat_fbd); 461 pci_read_config_word(pvt->branchmap_werrors, 462 NRECMEMA, &info->nrecmema); 463 pci_read_config_dword(pvt->branchmap_werrors, 464 NRECMEMB, &info->nrecmemb); 465 466 /* Clear the error bits, by writing them back */ 467 pci_write_config_dword(pvt->branchmap_werrors, 468 FERR_FAT_FBD, value); 469 } else { 470 info->ferr_fat_fbd = 0; 471 info->nerr_fat_fbd = 0; 472 info->nrecmema = 0; 473 info->nrecmemb = 0; 474 } 475 476 /* read in the 1st NON-FATAL error register */ 477 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); 478 479 /* If there is an error, then read in the 1st NON-FATAL error 480 * register as well */ 481 if (value & FERR_NF_MASK) { 482 info->ferr_nf_fbd = value; 483 484 /* harvest the various error data we need */ 485 pci_read_config_dword(pvt->branchmap_werrors, 486 NERR_NF_FBD, &info->nerr_nf_fbd); 487 pci_read_config_word(pvt->branchmap_werrors, 488 RECMEMA, &info->recmema); 489 pci_read_config_dword(pvt->branchmap_werrors, 490 RECMEMB, &info->recmemb); 491 pci_read_config_dword(pvt->branchmap_werrors, 492 REDMEMB, &info->redmemb); 493 494 /* Clear the error bits, by writing them back */ 495 pci_write_config_dword(pvt->branchmap_werrors, 496 FERR_NF_FBD, value); 497 } else { 498 info->ferr_nf_fbd = 0; 499 info->nerr_nf_fbd = 0; 500 info->recmema = 0; 501 info->recmemb = 0; 502 info->redmemb = 0; 503 } 504} 505 506/* 507 * i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci, 508 * struct i5400_error_info *info, 509 * int handle_errors); 510 * 511 * handle the Intel FATAL and unrecoverable errors, if any 512 */ 513static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci, 514 struct i5400_error_info *info, 515 unsigned long allErrors) 516{ 517 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80]; 518 int branch; 519 int channel; 520 int bank; 521 int buf_id; 522 int rank; 523 int rdwr; 524 int ras, cas; 525 int errnum; 526 char *type = NULL; 527 enum hw_event_mc_err_type tp_event = HW_EVENT_ERR_UNCORRECTED; 528 529 if (!allErrors) 530 return; /* if no error, return now */ 531 532 if (allErrors & ERROR_FAT_MASK) { 533 type = "FATAL"; 534 tp_event = HW_EVENT_ERR_FATAL; 535 } else if (allErrors & FERR_NF_UNCORRECTABLE) 536 type = "NON-FATAL uncorrected"; 537 else 538 type = "NON-FATAL recoverable"; 539 540 /* ONLY ONE of the possible error bits will be set, as per the docs */ 541 542 branch = extract_fbdchan_indx(info->ferr_fat_fbd); 543 channel = branch; 544 545 /* Use the NON-Recoverable macros to extract data */ 546 bank = nrec_bank(info); 547 rank = nrec_rank(info); 548 buf_id = nrec_buf_id(info); 549 rdwr = nrec_rdwr(info); 550 ras = nrec_ras(info); 551 cas = nrec_cas(info); 552 553 edac_dbg(0, "\t\t%s DIMM= %d Channels= %d,%d (Branch= %d DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n", 554 type, rank, channel, channel + 1, branch >> 1, bank, 555 buf_id, rdwr_str(rdwr), ras, cas); 556 557 /* Only 1 bit will be on */ 558 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); 559 560 /* Form out message */ 561 snprintf(msg, sizeof(msg), 562 "Bank=%d Buffer ID = %d RAS=%d CAS=%d Err=0x%lx (%s)", 563 bank, buf_id, ras, cas, allErrors, error_name[errnum]); 564 565 edac_mc_handle_error(tp_event, mci, 1, 0, 0, 0, 566 branch >> 1, -1, rank, 567 rdwr ? "Write error" : "Read error", 568 msg); 569} 570 571/* 572 * i5400_process_fatal_error_info(struct mem_ctl_info *mci, 573 * struct i5400_error_info *info, 574 * int handle_errors); 575 * 576 * handle the Intel NON-FATAL errors, if any 577 */ 578static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci, 579 struct i5400_error_info *info) 580{ 581 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80]; 582 unsigned long allErrors; 583 int branch; 584 int channel; 585 int bank; 586 int rank; 587 int rdwr; 588 int ras, cas; 589 int errnum; 590 591 /* mask off the Error bits that are possible */ 592 allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK); 593 if (!allErrors) 594 return; /* if no error, return now */ 595 596 /* ONLY ONE of the possible error bits will be set, as per the docs */ 597 598 if (allErrors & (ERROR_NF_UNCORRECTABLE | ERROR_NF_RECOVERABLE)) { 599 i5400_proccess_non_recoverable_info(mci, info, allErrors); 600 return; 601 } 602 603 /* Correctable errors */ 604 if (allErrors & ERROR_NF_CORRECTABLE) { 605 edac_dbg(0, "\tCorrected bits= 0x%lx\n", allErrors); 606 607 branch = extract_fbdchan_indx(info->ferr_nf_fbd); 608 609 channel = 0; 610 if (REC_ECC_LOCATOR_ODD(info->redmemb)) 611 channel = 1; 612 613 /* Convert channel to be based from zero, instead of 614 * from branch base of 0 */ 615 channel += branch; 616 617 bank = rec_bank(info); 618 rank = rec_rank(info); 619 rdwr = rec_rdwr(info); 620 ras = rec_ras(info); 621 cas = rec_cas(info); 622 623 /* Only 1 bit will be on */ 624 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); 625 626 edac_dbg(0, "\t\tDIMM= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", 627 rank, channel, branch >> 1, bank, 628 rdwr_str(rdwr), ras, cas); 629 630 /* Form out message */ 631 snprintf(msg, sizeof(msg), 632 "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s " 633 "RAS=%d CAS=%d, CE Err=0x%lx (%s))", 634 branch >> 1, bank, rdwr_str(rdwr), ras, cas, 635 allErrors, error_name[errnum]); 636 637 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, 638 branch >> 1, channel % 2, rank, 639 rdwr ? "Write error" : "Read error", 640 msg); 641 642 return; 643 } 644 645 /* Miscellaneous errors */ 646 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); 647 648 branch = extract_fbdchan_indx(info->ferr_nf_fbd); 649 650 i5400_mc_printk(mci, KERN_EMERG, 651 "Non-Fatal misc error (Branch=%d Err=%#lx (%s))", 652 branch >> 1, allErrors, error_name[errnum]); 653} 654 655/* 656 * i5400_process_error_info Process the error info that is 657 * in the 'info' structure, previously retrieved from hardware 658 */ 659static void i5400_process_error_info(struct mem_ctl_info *mci, 660 struct i5400_error_info *info) 661{ u32 allErrors; 662 663 /* First handle any fatal errors that occurred */ 664 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK); 665 i5400_proccess_non_recoverable_info(mci, info, allErrors); 666 667 /* now handle any non-fatal errors that occurred */ 668 i5400_process_nonfatal_error_info(mci, info); 669} 670 671/* 672 * i5400_clear_error Retrieve any error from the hardware 673 * but do NOT process that error. 674 * Used for 'clearing' out of previous errors 675 * Called by the Core module. 676 */ 677static void i5400_clear_error(struct mem_ctl_info *mci) 678{ 679 struct i5400_error_info info; 680 681 i5400_get_error_info(mci, &info); 682} 683 684/* 685 * i5400_check_error Retrieve and process errors reported by the 686 * hardware. Called by the Core module. 687 */ 688static void i5400_check_error(struct mem_ctl_info *mci) 689{ 690 struct i5400_error_info info; 691 692 i5400_get_error_info(mci, &info); 693 i5400_process_error_info(mci, &info); 694} 695 696/* 697 * i5400_put_devices 'put' all the devices that we have 698 * reserved via 'get' 699 */ 700static void i5400_put_devices(struct mem_ctl_info *mci) 701{ 702 struct i5400_pvt *pvt; 703 704 pvt = mci->pvt_info; 705 706 /* Decrement usage count for devices */ 707 pci_dev_put(pvt->branch_1); 708 pci_dev_put(pvt->branch_0); 709 pci_dev_put(pvt->fsb_error_regs); 710 pci_dev_put(pvt->branchmap_werrors); 711} 712 713/* 714 * i5400_get_devices Find and perform 'get' operation on the MCH's 715 * device/functions we want to reference for this driver 716 * 717 * Need to 'get' device 16 func 1 and func 2 718 */ 719static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx) 720{ 721 struct i5400_pvt *pvt; 722 struct pci_dev *pdev; 723 724 pvt = mci->pvt_info; 725 pvt->branchmap_werrors = NULL; 726 pvt->fsb_error_regs = NULL; 727 pvt->branch_0 = NULL; 728 pvt->branch_1 = NULL; 729 730 /* Attempt to 'get' the MCH register we want */ 731 pdev = NULL; 732 while (1) { 733 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 734 PCI_DEVICE_ID_INTEL_5400_ERR, pdev); 735 if (!pdev) { 736 /* End of list, leave */ 737 i5400_printk(KERN_ERR, 738 "'system address,Process Bus' " 739 "device not found:" 740 "vendor 0x%x device 0x%x ERR func 1 " 741 "(broken BIOS?)\n", 742 PCI_VENDOR_ID_INTEL, 743 PCI_DEVICE_ID_INTEL_5400_ERR); 744 return -ENODEV; 745 } 746 747 /* Store device 16 func 1 */ 748 if (PCI_FUNC(pdev->devfn) == 1) 749 break; 750 } 751 pvt->branchmap_werrors = pdev; 752 753 pdev = NULL; 754 while (1) { 755 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 756 PCI_DEVICE_ID_INTEL_5400_ERR, pdev); 757 if (!pdev) { 758 /* End of list, leave */ 759 i5400_printk(KERN_ERR, 760 "'system address,Process Bus' " 761 "device not found:" 762 "vendor 0x%x device 0x%x ERR func 2 " 763 "(broken BIOS?)\n", 764 PCI_VENDOR_ID_INTEL, 765 PCI_DEVICE_ID_INTEL_5400_ERR); 766 767 pci_dev_put(pvt->branchmap_werrors); 768 return -ENODEV; 769 } 770 771 /* Store device 16 func 2 */ 772 if (PCI_FUNC(pdev->devfn) == 2) 773 break; 774 } 775 pvt->fsb_error_regs = pdev; 776 777 edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n", 778 pci_name(pvt->system_address), 779 pvt->system_address->vendor, pvt->system_address->device); 780 edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", 781 pci_name(pvt->branchmap_werrors), 782 pvt->branchmap_werrors->vendor, 783 pvt->branchmap_werrors->device); 784 edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n", 785 pci_name(pvt->fsb_error_regs), 786 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device); 787 788 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL, 789 PCI_DEVICE_ID_INTEL_5400_FBD0, NULL); 790 if (!pvt->branch_0) { 791 i5400_printk(KERN_ERR, 792 "MC: 'BRANCH 0' device not found:" 793 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n", 794 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD0); 795 796 pci_dev_put(pvt->fsb_error_regs); 797 pci_dev_put(pvt->branchmap_werrors); 798 return -ENODEV; 799 } 800 801 /* If this device claims to have more than 2 channels then 802 * fetch Branch 1's information 803 */ 804 if (pvt->maxch < CHANNELS_PER_BRANCH) 805 return 0; 806 807 pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL, 808 PCI_DEVICE_ID_INTEL_5400_FBD1, NULL); 809 if (!pvt->branch_1) { 810 i5400_printk(KERN_ERR, 811 "MC: 'BRANCH 1' device not found:" 812 "vendor 0x%x device 0x%x Func 0 " 813 "(broken BIOS?)\n", 814 PCI_VENDOR_ID_INTEL, 815 PCI_DEVICE_ID_INTEL_5400_FBD1); 816 817 pci_dev_put(pvt->branch_0); 818 pci_dev_put(pvt->fsb_error_regs); 819 pci_dev_put(pvt->branchmap_werrors); 820 return -ENODEV; 821 } 822 823 return 0; 824} 825 826/* 827 * determine_amb_present 828 * 829 * the information is contained in DIMMS_PER_CHANNEL different 830 * registers determining which of the DIMMS_PER_CHANNEL requires 831 * knowing which channel is in question 832 * 833 * 2 branches, each with 2 channels 834 * b0_ambpresent0 for channel '0' 835 * b0_ambpresent1 for channel '1' 836 * b1_ambpresent0 for channel '2' 837 * b1_ambpresent1 for channel '3' 838 */ 839static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel) 840{ 841 int amb_present; 842 843 if (channel < CHANNELS_PER_BRANCH) { 844 if (channel & 0x1) 845 amb_present = pvt->b0_ambpresent1; 846 else 847 amb_present = pvt->b0_ambpresent0; 848 } else { 849 if (channel & 0x1) 850 amb_present = pvt->b1_ambpresent1; 851 else 852 amb_present = pvt->b1_ambpresent0; 853 } 854 855 return amb_present; 856} 857 858/* 859 * determine_mtr(pvt, dimm, channel) 860 * 861 * return the proper MTR register as determine by the dimm and desired channel 862 */ 863static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel) 864{ 865 int mtr; 866 int n; 867 868 /* There is one MTR for each slot pair of FB-DIMMs, 869 Each slot pair may be at branch 0 or branch 1. 870 */ 871 n = dimm; 872 873 if (n >= DIMMS_PER_CHANNEL) { 874 edac_dbg(0, "ERROR: trying to access an invalid dimm: %d\n", 875 dimm); 876 return 0; 877 } 878 879 if (channel < CHANNELS_PER_BRANCH) 880 mtr = pvt->b0_mtr[n]; 881 else 882 mtr = pvt->b1_mtr[n]; 883 884 return mtr; 885} 886 887/* 888 */ 889static void decode_mtr(int slot_row, u16 mtr) 890{ 891 int ans; 892 893 ans = MTR_DIMMS_PRESENT(mtr); 894 895 edac_dbg(2, "\tMTR%d=0x%x: DIMMs are %sPresent\n", 896 slot_row, mtr, ans ? "" : "NOT "); 897 if (!ans) 898 return; 899 900 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); 901 902 edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n", 903 str_enabled_disabled(MTR_DIMMS_ETHROTTLE(mtr))); 904 905 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); 906 edac_dbg(2, "\t\tNUMRANK: %s\n", 907 MTR_DIMM_RANK(mtr) ? "double" : "single"); 908 edac_dbg(2, "\t\tNUMROW: %s\n", 909 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : 910 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : 911 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : 912 "65,536 - 16 rows"); 913 edac_dbg(2, "\t\tNUMCOL: %s\n", 914 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : 915 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : 916 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : 917 "reserved"); 918} 919 920static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel, 921 struct i5400_dimm_info *dinfo) 922{ 923 int mtr; 924 int amb_present_reg; 925 int addrBits; 926 927 mtr = determine_mtr(pvt, dimm, channel); 928 if (MTR_DIMMS_PRESENT(mtr)) { 929 amb_present_reg = determine_amb_present_reg(pvt, channel); 930 931 /* Determine if there is a DIMM present in this DIMM slot */ 932 if (amb_present_reg & (1 << dimm)) { 933 /* Start with the number of bits for a Bank 934 * on the DRAM */ 935 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr); 936 /* Add thenumber of ROW bits */ 937 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); 938 /* add the number of COLUMN bits */ 939 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); 940 /* add the number of RANK bits */ 941 addrBits += MTR_DIMM_RANK(mtr); 942 943 addrBits += 6; /* add 64 bits per DIMM */ 944 addrBits -= 20; /* divide by 2^^20 */ 945 addrBits -= 3; /* 8 bits per bytes */ 946 947 dinfo->megabytes = 1 << addrBits; 948 } 949 } 950} 951 952/* 953 * calculate_dimm_size 954 * 955 * also will output a DIMM matrix map, if debug is enabled, for viewing 956 * how the DIMMs are populated 957 */ 958static void calculate_dimm_size(struct i5400_pvt *pvt) 959{ 960 struct i5400_dimm_info *dinfo; 961 int dimm, max_dimms; 962 char *p, *mem_buffer; 963 int space, n; 964 int channel, branch; 965 966 /* ================= Generate some debug output ================= */ 967 space = PAGE_SIZE; 968 mem_buffer = p = kmalloc(space, GFP_KERNEL); 969 if (p == NULL) { 970 i5400_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n", 971 __FILE__, __func__); 972 return; 973 } 974 975 /* Scan all the actual DIMMS 976 * and calculate the information for each DIMM 977 * Start with the highest dimm first, to display it first 978 * and work toward the 0th dimm 979 */ 980 max_dimms = pvt->maxdimmperch; 981 for (dimm = max_dimms - 1; dimm >= 0; dimm--) { 982 983 /* on an odd dimm, first output a 'boundary' marker, 984 * then reset the message buffer */ 985 if (dimm & 0x1) { 986 n = snprintf(p, space, "---------------------------" 987 "-------------------------------"); 988 p += n; 989 space -= n; 990 edac_dbg(2, "%s\n", mem_buffer); 991 p = mem_buffer; 992 space = PAGE_SIZE; 993 } 994 n = snprintf(p, space, "dimm %2d ", dimm); 995 p += n; 996 space -= n; 997 998 for (channel = 0; channel < pvt->maxch; channel++) { 999 dinfo = &pvt->dimm_info[dimm][channel]; 1000 handle_channel(pvt, dimm, channel, dinfo); 1001 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); 1002 p += n; 1003 space -= n; 1004 } 1005 edac_dbg(2, "%s\n", mem_buffer); 1006 p = mem_buffer; 1007 space = PAGE_SIZE; 1008 } 1009 1010 /* Output the last bottom 'boundary' marker */ 1011 n = snprintf(p, space, "---------------------------" 1012 "-------------------------------"); 1013 p += n; 1014 space -= n; 1015 edac_dbg(2, "%s\n", mem_buffer); 1016 p = mem_buffer; 1017 space = PAGE_SIZE; 1018 1019 /* now output the 'channel' labels */ 1020 n = snprintf(p, space, " "); 1021 p += n; 1022 space -= n; 1023 for (channel = 0; channel < pvt->maxch; channel++) { 1024 n = snprintf(p, space, "channel %d | ", channel); 1025 p += n; 1026 space -= n; 1027 } 1028 1029 edac_dbg(2, "%s\n", mem_buffer); 1030 p = mem_buffer; 1031 space = PAGE_SIZE; 1032 1033 n = snprintf(p, space, " "); 1034 p += n; 1035 space -= n; 1036 for (branch = 0; branch < MAX_BRANCHES; branch++) { 1037 n = snprintf(p, space, " branch %d | ", branch); 1038 p += n; 1039 space -= n; 1040 } 1041 1042 /* output the last message and free buffer */ 1043 edac_dbg(2, "%s\n", mem_buffer); 1044 kfree(mem_buffer); 1045} 1046 1047/* 1048 * i5400_get_mc_regs read in the necessary registers and 1049 * cache locally 1050 * 1051 * Fills in the private data members 1052 */ 1053static void i5400_get_mc_regs(struct mem_ctl_info *mci) 1054{ 1055 struct i5400_pvt *pvt; 1056 u32 actual_tolm; 1057 u16 limit; 1058 int slot_row; 1059 int way0, way1; 1060 1061 pvt = mci->pvt_info; 1062 1063 pci_read_config_dword(pvt->system_address, AMBASE, 1064 &pvt->u.ambase_bottom); 1065 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32), 1066 &pvt->u.ambase_top); 1067 1068 edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n", 1069 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch); 1070 1071 /* Get the Branch Map regs */ 1072 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm); 1073 pvt->tolm >>= 12; 1074 edac_dbg(2, "\nTOLM (number of 256M regions) =%u (0x%x)\n", 1075 pvt->tolm, pvt->tolm); 1076 1077 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); 1078 edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x)\n", 1079 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); 1080 1081 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0); 1082 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1); 1083 1084 /* Get the MIR[0-1] regs */ 1085 limit = (pvt->mir0 >> 4) & 0x0fff; 1086 way0 = pvt->mir0 & 0x1; 1087 way1 = pvt->mir0 & 0x2; 1088 edac_dbg(2, "MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", 1089 limit, way1, way0); 1090 limit = (pvt->mir1 >> 4) & 0xfff; 1091 way0 = pvt->mir1 & 0x1; 1092 way1 = pvt->mir1 & 0x2; 1093 edac_dbg(2, "MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", 1094 limit, way1, way0); 1095 1096 /* Get the set of MTR[0-3] regs by each branch */ 1097 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) { 1098 int where = MTR0 + (slot_row * sizeof(u16)); 1099 1100 /* Branch 0 set of MTR registers */ 1101 pci_read_config_word(pvt->branch_0, where, 1102 &pvt->b0_mtr[slot_row]); 1103 1104 edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n", 1105 slot_row, where, pvt->b0_mtr[slot_row]); 1106 1107 if (pvt->maxch < CHANNELS_PER_BRANCH) { 1108 pvt->b1_mtr[slot_row] = 0; 1109 continue; 1110 } 1111 1112 /* Branch 1 set of MTR registers */ 1113 pci_read_config_word(pvt->branch_1, where, 1114 &pvt->b1_mtr[slot_row]); 1115 edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n", 1116 slot_row, where, pvt->b1_mtr[slot_row]); 1117 } 1118 1119 /* Read and dump branch 0's MTRs */ 1120 edac_dbg(2, "Memory Technology Registers:\n"); 1121 edac_dbg(2, " Branch 0:\n"); 1122 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) 1123 decode_mtr(slot_row, pvt->b0_mtr[slot_row]); 1124 1125 pci_read_config_word(pvt->branch_0, AMBPRESENT_0, 1126 &pvt->b0_ambpresent0); 1127 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0); 1128 pci_read_config_word(pvt->branch_0, AMBPRESENT_1, 1129 &pvt->b0_ambpresent1); 1130 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1); 1131 1132 /* Only if we have 2 branchs (4 channels) */ 1133 if (pvt->maxch < CHANNELS_PER_BRANCH) { 1134 pvt->b1_ambpresent0 = 0; 1135 pvt->b1_ambpresent1 = 0; 1136 } else { 1137 /* Read and dump branch 1's MTRs */ 1138 edac_dbg(2, " Branch 1:\n"); 1139 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) 1140 decode_mtr(slot_row, pvt->b1_mtr[slot_row]); 1141 1142 pci_read_config_word(pvt->branch_1, AMBPRESENT_0, 1143 &pvt->b1_ambpresent0); 1144 edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n", 1145 pvt->b1_ambpresent0); 1146 pci_read_config_word(pvt->branch_1, AMBPRESENT_1, 1147 &pvt->b1_ambpresent1); 1148 edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n", 1149 pvt->b1_ambpresent1); 1150 } 1151 1152 /* Go and determine the size of each DIMM and place in an 1153 * orderly matrix */ 1154 calculate_dimm_size(pvt); 1155} 1156 1157/* 1158 * i5400_init_dimms Initialize the 'dimms' table within 1159 * the mci control structure with the 1160 * addressing of memory. 1161 * 1162 * return: 1163 * 0 success 1164 * 1 no actual memory found on this MC 1165 */ 1166static int i5400_init_dimms(struct mem_ctl_info *mci) 1167{ 1168 struct i5400_pvt *pvt; 1169 struct dimm_info *dimm; 1170 int ndimms; 1171 int mtr; 1172 int size_mb; 1173 int channel, slot; 1174 1175 pvt = mci->pvt_info; 1176 1177 ndimms = 0; 1178 1179 /* 1180 * FIXME: remove pvt->dimm_info[slot][channel] and use the 3 1181 * layers here. 1182 */ 1183 for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size; 1184 channel++) { 1185 for (slot = 0; slot < mci->layers[2].size; slot++) { 1186 mtr = determine_mtr(pvt, slot, channel); 1187 1188 /* if no DIMMS on this slot, continue */ 1189 if (!MTR_DIMMS_PRESENT(mtr)) 1190 continue; 1191 1192 dimm = edac_get_dimm(mci, channel / 2, channel % 2, slot); 1193 1194 size_mb = pvt->dimm_info[slot][channel].megabytes; 1195 1196 edac_dbg(2, "dimm (branch %d channel %d slot %d): %d.%03d GB\n", 1197 channel / 2, channel % 2, slot, 1198 size_mb / 1000, size_mb % 1000); 1199 1200 dimm->nr_pages = size_mb << 8; 1201 dimm->grain = 8; 1202 dimm->dtype = MTR_DRAM_WIDTH(mtr) == 8 ? 1203 DEV_X8 : DEV_X4; 1204 dimm->mtype = MEM_FB_DDR2; 1205 /* 1206 * The eccc mechanism is SDDC (aka SECC), with 1207 * is similar to Chipkill. 1208 */ 1209 dimm->edac_mode = MTR_DRAM_WIDTH(mtr) == 8 ? 1210 EDAC_S8ECD8ED : EDAC_S4ECD4ED; 1211 ndimms++; 1212 } 1213 } 1214 1215 /* 1216 * When just one memory is provided, it should be at location (0,0,0). 1217 * With such single-DIMM mode, the SDCC algorithm degrades to SECDEC+. 1218 */ 1219 if (ndimms == 1) 1220 mci->dimms[0]->edac_mode = EDAC_SECDED; 1221 1222 return (ndimms == 0); 1223} 1224 1225/* 1226 * i5400_enable_error_reporting 1227 * Turn on the memory reporting features of the hardware 1228 */ 1229static void i5400_enable_error_reporting(struct mem_ctl_info *mci) 1230{ 1231 struct i5400_pvt *pvt; 1232 u32 fbd_error_mask; 1233 1234 pvt = mci->pvt_info; 1235 1236 /* Read the FBD Error Mask Register */ 1237 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD, 1238 &fbd_error_mask); 1239 1240 /* Enable with a '0' */ 1241 fbd_error_mask &= ~(ENABLE_EMASK_ALL); 1242 1243 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD, 1244 fbd_error_mask); 1245} 1246 1247/* 1248 * i5400_probe1 Probe for ONE instance of device to see if it is 1249 * present. 1250 * return: 1251 * 0 for FOUND a device 1252 * < 0 for error code 1253 */ 1254static int i5400_probe1(struct pci_dev *pdev, int dev_idx) 1255{ 1256 struct mem_ctl_info *mci; 1257 struct i5400_pvt *pvt; 1258 struct edac_mc_layer layers[3]; 1259 1260 if (dev_idx >= ARRAY_SIZE(i5400_devs)) 1261 return -EINVAL; 1262 1263 edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n", 1264 pdev->bus->number, 1265 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 1266 1267 /* We only are looking for func 0 of the set */ 1268 if (PCI_FUNC(pdev->devfn) != 0) 1269 return -ENODEV; 1270 1271 /* 1272 * allocate a new MC control structure 1273 * 1274 * This drivers uses the DIMM slot as "csrow" and the rest as "channel". 1275 */ 1276 layers[0].type = EDAC_MC_LAYER_BRANCH; 1277 layers[0].size = MAX_BRANCHES; 1278 layers[0].is_virt_csrow = false; 1279 layers[1].type = EDAC_MC_LAYER_CHANNEL; 1280 layers[1].size = CHANNELS_PER_BRANCH; 1281 layers[1].is_virt_csrow = false; 1282 layers[2].type = EDAC_MC_LAYER_SLOT; 1283 layers[2].size = DIMMS_PER_CHANNEL; 1284 layers[2].is_virt_csrow = true; 1285 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); 1286 if (mci == NULL) 1287 return -ENOMEM; 1288 1289 edac_dbg(0, "MC: mci = %p\n", mci); 1290 1291 mci->pdev = &pdev->dev; /* record ptr to the generic device */ 1292 1293 pvt = mci->pvt_info; 1294 pvt->system_address = pdev; /* Record this device in our private */ 1295 pvt->maxch = MAX_CHANNELS; 1296 pvt->maxdimmperch = DIMMS_PER_CHANNEL; 1297 1298 /* 'get' the pci devices we want to reserve for our use */ 1299 if (i5400_get_devices(mci, dev_idx)) 1300 goto fail0; 1301 1302 /* Time to get serious */ 1303 i5400_get_mc_regs(mci); /* retrieve the hardware registers */ 1304 1305 mci->mc_idx = 0; 1306 mci->mtype_cap = MEM_FLAG_FB_DDR2; 1307 mci->edac_ctl_cap = EDAC_FLAG_NONE; 1308 mci->edac_cap = EDAC_FLAG_NONE; 1309 mci->mod_name = "i5400_edac.c"; 1310 mci->ctl_name = i5400_devs[dev_idx].ctl_name; 1311 mci->dev_name = pci_name(pdev); 1312 mci->ctl_page_to_phys = NULL; 1313 1314 /* Set the function pointer to an actual operation function */ 1315 mci->edac_check = i5400_check_error; 1316 1317 /* initialize the MC control structure 'dimms' table 1318 * with the mapping and control information */ 1319 if (i5400_init_dimms(mci)) { 1320 edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5400_init_dimms() returned nonzero value\n"); 1321 mci->edac_cap = EDAC_FLAG_NONE; /* no dimms found */ 1322 } else { 1323 edac_dbg(1, "MC: Enable error reporting now\n"); 1324 i5400_enable_error_reporting(mci); 1325 } 1326 1327 /* add this new MC control structure to EDAC's list of MCs */ 1328 if (edac_mc_add_mc(mci)) { 1329 edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); 1330 /* FIXME: perhaps some code should go here that disables error 1331 * reporting if we just enabled it 1332 */ 1333 goto fail1; 1334 } 1335 1336 i5400_clear_error(mci); 1337 1338 /* allocating generic PCI control info */ 1339 i5400_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 1340 if (!i5400_pci) { 1341 printk(KERN_WARNING 1342 "%s(): Unable to create PCI control\n", 1343 __func__); 1344 printk(KERN_WARNING 1345 "%s(): PCI error report via EDAC not setup\n", 1346 __func__); 1347 } 1348 1349 return 0; 1350 1351 /* Error exit unwinding stack */ 1352fail1: 1353 1354 i5400_put_devices(mci); 1355 1356fail0: 1357 edac_mc_free(mci); 1358 return -ENODEV; 1359} 1360 1361/* 1362 * i5400_init_one constructor for one instance of device 1363 * 1364 * returns: 1365 * negative on error 1366 * count (>= 0) 1367 */ 1368static int i5400_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 1369{ 1370 int rc; 1371 1372 edac_dbg(0, "MC:\n"); 1373 1374 /* wake up device */ 1375 rc = pci_enable_device(pdev); 1376 if (rc) 1377 return rc; 1378 1379 /* now probe and enable the device */ 1380 return i5400_probe1(pdev, id->driver_data); 1381} 1382 1383/* 1384 * i5400_remove_one destructor for one instance of device 1385 * 1386 */ 1387static void i5400_remove_one(struct pci_dev *pdev) 1388{ 1389 struct mem_ctl_info *mci; 1390 1391 edac_dbg(0, "\n"); 1392 1393 if (i5400_pci) 1394 edac_pci_release_generic_ctl(i5400_pci); 1395 1396 mci = edac_mc_del_mc(&pdev->dev); 1397 if (!mci) 1398 return; 1399 1400 /* retrieve references to resources, and free those resources */ 1401 i5400_put_devices(mci); 1402 1403 pci_disable_device(pdev); 1404 1405 edac_mc_free(mci); 1406} 1407 1408/* 1409 * pci_device_id table for which devices we are looking for 1410 * 1411 * The "E500P" device is the first device supported. 1412 */ 1413static const struct pci_device_id i5400_pci_tbl[] = { 1414 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR)}, 1415 {0,} /* 0 terminated list. */ 1416}; 1417 1418MODULE_DEVICE_TABLE(pci, i5400_pci_tbl); 1419 1420/* 1421 * i5400_driver pci_driver structure for this module 1422 * 1423 */ 1424static struct pci_driver i5400_driver = { 1425 .name = "i5400_edac", 1426 .probe = i5400_init_one, 1427 .remove = i5400_remove_one, 1428 .id_table = i5400_pci_tbl, 1429}; 1430 1431/* 1432 * i5400_init Module entry function 1433 * Try to initialize this module for its devices 1434 */ 1435static int __init i5400_init(void) 1436{ 1437 int pci_rc; 1438 1439 edac_dbg(2, "MC:\n"); 1440 1441 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 1442 opstate_init(); 1443 1444 pci_rc = pci_register_driver(&i5400_driver); 1445 1446 return (pci_rc < 0) ? pci_rc : 0; 1447} 1448 1449/* 1450 * i5400_exit() Module exit function 1451 * Unregister the driver 1452 */ 1453static void __exit i5400_exit(void) 1454{ 1455 edac_dbg(2, "MC:\n"); 1456 pci_unregister_driver(&i5400_driver); 1457} 1458 1459module_init(i5400_init); 1460module_exit(i5400_exit); 1461 1462MODULE_LICENSE("GPL"); 1463MODULE_AUTHOR("Ben Woodard <woodard@redhat.com>"); 1464MODULE_AUTHOR("Mauro Carvalho Chehab"); 1465MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)"); 1466MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - " 1467 I5400_REVISION); 1468 1469module_param(edac_op_state, int, 0444); 1470MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
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