amd64_edac.h

  1/*
  2 * AMD64 class Memory Controller kernel module
  3 *
  4 * Copyright (c) 2009 SoftwareBitMaker.
  5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
  6 *
  7 * This file may be distributed under the terms of the
  8 * GNU General Public License.
  9 */
 10
 11#include <linux/module.h>
 12#include <linux/ctype.h>
 13#include <linux/init.h>
 14#include <linux/pci.h>
 15#include <linux/pci_ids.h>
 16#include <linux/slab.h>
 17#include <linux/mmzone.h>
 18#include <linux/edac.h>
 19#include <linux/bitfield.h>
 20#include <asm/cpu_device_id.h>
 21#include <asm/msr.h>
 22#include "edac_module.h"
 23#include "mce_amd.h"
 24
 25#define amd64_info(fmt, arg...) \
 26	edac_printk(KERN_INFO, "amd64", fmt, ##arg)
 27
 28#define amd64_warn(fmt, arg...) \
 29	edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)
 30
 31#define amd64_err(fmt, arg...) \
 32	edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)
 33
 34#define amd64_mc_warn(mci, fmt, arg...) \
 35	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
 36
 37#define amd64_mc_err(mci, fmt, arg...) \
 38	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
 39
 40/*
 41 * Throughout the comments in this code, the following terms are used:
 42 *
 43 *	SysAddr, DramAddr, and InputAddr
 44 *
 45 *  These terms come directly from the amd64 documentation
 46 * (AMD publication #26094).  They are defined as follows:
 47 *
 48 *     SysAddr:
 49 *         This is a physical address generated by a CPU core or a device
 50 *         doing DMA.  If generated by a CPU core, a SysAddr is the result of
 51 *         a virtual to physical address translation by the CPU core's address
 52 *         translation mechanism (MMU).
 53 *
 54 *     DramAddr:
 55 *         A DramAddr is derived from a SysAddr by subtracting an offset that
 56 *         depends on which node the SysAddr maps to and whether the SysAddr
 57 *         is within a range affected by memory hoisting.  The DRAM Base
 58 *         (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
 59 *         determine which node a SysAddr maps to.
 60 *
 61 *         If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
 62 *         is within the range of addresses specified by this register, then
 63 *         a value x from the DHAR is subtracted from the SysAddr to produce a
 64 *         DramAddr.  Here, x represents the base address for the node that
 65 *         the SysAddr maps to plus an offset due to memory hoisting.  See
 66 *         section 3.4.8 and the comments in amd64_get_dram_hole_info() and
 67 *         sys_addr_to_dram_addr() below for more information.
 68 *
 69 *         If the SysAddr is not affected by the DHAR then a value y is
 70 *         subtracted from the SysAddr to produce a DramAddr.  Here, y is the
 71 *         base address for the node that the SysAddr maps to.  See section
 72 *         3.4.4 and the comments in sys_addr_to_dram_addr() below for more
 73 *         information.
 74 *
 75 *     InputAddr:
 76 *         A DramAddr is translated to an InputAddr before being passed to the
 77 *         memory controller for the node that the DramAddr is associated
 78 *         with.  The memory controller then maps the InputAddr to a csrow.
 79 *         If node interleaving is not in use, then the InputAddr has the same
 80 *         value as the DramAddr.  Otherwise, the InputAddr is produced by
 81 *         discarding the bits used for node interleaving from the DramAddr.
 82 *         See section 3.4.4 for more information.
 83 *
 84 *         The memory controller for a given node uses its DRAM CS Base and
 85 *         DRAM CS Mask registers to map an InputAddr to a csrow.  See
 86 *         sections 3.5.4 and 3.5.5 for more information.
 87 */
 88
 89#define EDAC_MOD_STR			"amd64_edac"
 90
 91/* Extended Model from CPUID, for CPU Revision numbers */
 92#define K8_REV_D			1
 93#define K8_REV_E			2
 94#define K8_REV_F			4
 95
 96/* Hardware limit on ChipSelect rows per MC and processors per system */
 97#define NUM_CHIPSELECTS			8
 98#define DRAM_RANGES			8
 99
100#define ON true
101#define OFF false
102
103#define MAX_CTL_NAMELEN	19
104
105/*
106 * PCI-defined configuration space registers
107 */
108#define PCI_DEVICE_ID_AMD_15H_NB_F1	0x1601
109#define PCI_DEVICE_ID_AMD_15H_NB_F2	0x1602
110#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
111#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
112#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
113#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
114#define PCI_DEVICE_ID_AMD_16H_NB_F1	0x1531
115#define PCI_DEVICE_ID_AMD_16H_NB_F2	0x1532
116#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
117#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
118
119/*
120 * Function 1 - Address Map
121 */
122#define DRAM_BASE_LO			0x40
123#define DRAM_LIMIT_LO			0x44
124
125/*
126 * F15 M30h D18F1x2[1C:00]
127 */
128#define DRAM_CONT_BASE			0x200
129#define DRAM_CONT_LIMIT			0x204
130
131/*
132 * F15 M30h D18F1x2[4C:40]
133 */
134#define DRAM_CONT_HIGH_OFF		0x240
135
136#define dram_rw(pvt, i)			((u8)(pvt->ranges[i].base.lo & 0x3))
137#define dram_intlv_sel(pvt, i)		((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
138#define dram_dst_node(pvt, i)		((u8)(pvt->ranges[i].lim.lo & 0x7))
139
140#define DHAR				0xf0
141#define dhar_mem_hoist_valid(pvt)	((pvt)->dhar & BIT(1))
142#define dhar_base(pvt)			((pvt)->dhar & 0xff000000)
143#define k8_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff00) << 16)
144
145					/* NOTE: Extra mask bit vs K8 */
146#define f10_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff80) << 16)
147
148#define DCT_CFG_SEL			0x10C
149
150#define DRAM_LOCAL_NODE_BASE		0x120
151#define DRAM_LOCAL_NODE_LIM		0x124
152
153#define DRAM_BASE_HI			0x140
154#define DRAM_LIMIT_HI			0x144
155
156
157/*
158 * Function 2 - DRAM controller
159 */
160#define DCSB0				0x40
161#define DCSB1				0x140
162#define DCSB_CS_ENABLE			BIT(0)
163
164#define DCSM0				0x60
165#define DCSM1				0x160
166
167#define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)]     & DCSB_CS_ENABLE)
168#define csrow_sec_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
169
170#define DRAM_CONTROL			0x78
171
172#define DBAM0				0x80
173#define DBAM1				0x180
174
175/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
176#define DBAM_DIMM(i, reg)		((((reg) >> (4*(i)))) & 0xF)
177
178#define DBAM_MAX_VALUE			11
179
180#define DCLR0				0x90
181#define DCLR1				0x190
182#define REVE_WIDTH_128			BIT(16)
183#define WIDTH_128			BIT(11)
184
185#define DCHR0				0x94
186#define DCHR1				0x194
187#define DDR3_MODE			BIT(8)
188
189#define DCT_SEL_LO			0x110
190#define dct_high_range_enabled(pvt)	((pvt)->dct_sel_lo & BIT(0))
191#define dct_interleave_enabled(pvt)	((pvt)->dct_sel_lo & BIT(2))
192
193#define dct_ganging_enabled(pvt)	((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
194
195#define dct_data_intlv_enabled(pvt)	((pvt)->dct_sel_lo & BIT(5))
196#define dct_memory_cleared(pvt)		((pvt)->dct_sel_lo & BIT(10))
197
198#define SWAP_INTLV_REG			0x10c
199
200#define DCT_SEL_HI			0x114
201
202#define F15H_M60H_SCRCTRL		0x1C8
203
204/*
205 * Function 3 - Misc Control
206 */
207#define NBCTL				0x40
208
209#define NBCFG				0x44
210#define NBCFG_CHIPKILL			BIT(23)
211#define NBCFG_ECC_ENABLE		BIT(22)
212
213/* F3x48: NBSL */
214#define F10_NBSL_EXT_ERR_ECC		0x8
215#define NBSL_PP_OBS			0x2
216
217#define SCRCTRL				0x58
218
219#define F10_ONLINE_SPARE		0xB0
220#define online_spare_swap_done(pvt, c)	(((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
221#define online_spare_bad_dramcs(pvt, c)	(((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
222
223#define F10_NB_ARRAY_ADDR		0xB8
224#define F10_NB_ARRAY_DRAM		BIT(31)
225
226/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
227#define SET_NB_ARRAY_ADDR(section)	(((section) & 0x3) << 1)
228
229#define F10_NB_ARRAY_DATA		0xBC
230#define F10_NB_ARR_ECC_WR_REQ		BIT(17)
231#define SET_NB_DRAM_INJECTION_WRITE(inj)  \
232					(BIT(((inj.word) & 0xF) + 20) | \
233					F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
234#define SET_NB_DRAM_INJECTION_READ(inj)  \
235					(BIT(((inj.word) & 0xF) + 20) | \
236					BIT(16) |  inj.bit_map)
237
238
239#define NBCAP				0xE8
240#define NBCAP_CHIPKILL			BIT(4)
241#define NBCAP_SECDED			BIT(3)
242#define NBCAP_DCT_DUAL			BIT(0)
243
244#define EXT_NB_MCA_CFG			0x180
245
246/* MSRs */
247#define MSR_MCGCTL_NBE			BIT(4)
248
249/* F17h */
250
251/* F0: */
252#define DF_DHAR				0x104
253
254/* UMC CH register offsets */
255#define UMCCH_BASE_ADDR			0x0
256#define UMCCH_BASE_ADDR_SEC		0x10
257#define UMCCH_ADDR_MASK			0x20
258#define UMCCH_ADDR_MASK_SEC		0x28
259#define UMCCH_ADDR_MASK_SEC_DDR5	0x30
260#define UMCCH_DIMM_CFG			0x80
261#define UMCCH_DIMM_CFG_DDR5		0x90
262#define UMCCH_UMC_CFG			0x100
263#define UMCCH_SDP_CTRL			0x104
264#define UMCCH_ECC_CTRL			0x14C
265#define UMCCH_UMC_CAP_HI		0xDF4
266
267/* UMC CH bitfields */
268#define UMC_ECC_CHIPKILL_CAP		BIT(31)
269#define UMC_ECC_ENABLED			BIT(30)
270
271#define UMC_SDP_INIT			BIT(31)
272
273/* Error injection control structure */
274struct error_injection {
275	u32	 section;
276	u32	 word;
277	u32	 bit_map;
278};
279
280/* low and high part of PCI config space regs */
281struct reg_pair {
282	u32 lo, hi;
283};
284
285/*
286 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
287 */
288struct dram_range {
289	struct reg_pair base;
290	struct reg_pair lim;
291};
292
293/* A DCT chip selects collection */
294struct chip_select {
295	u32 csbases[NUM_CHIPSELECTS];
296	u32 csbases_sec[NUM_CHIPSELECTS];
297	u8 b_cnt;
298
299	u32 csmasks[NUM_CHIPSELECTS];
300	u32 csmasks_sec[NUM_CHIPSELECTS];
301	u8 m_cnt;
302};
303
304struct amd64_umc {
305	u32 dimm_cfg;		/* DIMM Configuration reg */
306	u32 umc_cfg;		/* Configuration reg */
307	u32 sdp_ctrl;		/* SDP Control reg */
308	u32 ecc_ctrl;		/* DRAM ECC Control reg */
309	u32 umc_cap_hi;		/* Capabilities High reg */
310
311	/* cache the dram_type */
312	enum mem_type dram_type;
313};
314
315struct amd64_family_flags {
316	/*
317	 * Indicates that the system supports the new register offsets, etc.
318	 * first introduced with Family 19h Model 10h.
319	 */
320	__u64 zn_regs_v2	: 1,
321
322	      __reserved	: 63;
323};
324
325struct amd64_pvt {
326	struct low_ops *ops;
327
328	/* pci_device handles which we utilize */
329	struct pci_dev *F1, *F2, *F3;
330
331	u16 mc_node_id;		/* MC index of this MC node */
332	u8 fam;			/* CPU family */
333	u8 model;		/* ... model */
334	u8 stepping;		/* ... stepping */
335
336	int ext_model;		/* extended model value of this node */
337
338	/* Raw registers */
339	u32 dclr0;		/* DRAM Configuration Low DCT0 reg */
340	u32 dclr1;		/* DRAM Configuration Low DCT1 reg */
341	u32 dchr0;		/* DRAM Configuration High DCT0 reg */
342	u32 dchr1;		/* DRAM Configuration High DCT1 reg */
343	u32 nbcap;		/* North Bridge Capabilities */
344	u32 nbcfg;		/* F10 North Bridge Configuration */
345	u32 dhar;		/* DRAM Hoist reg */
346	u32 dbam0;		/* DRAM Base Address Mapping reg for DCT0 */
347	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */
348
349	/* one for each DCT/UMC */
350	struct chip_select *csels;
351
352	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
353	struct dram_range ranges[DRAM_RANGES];
354
355	u64 top_mem;		/* top of memory below 4GB */
356	u64 top_mem2;		/* top of memory above 4GB */
357
358	u32 dct_sel_lo;		/* DRAM Controller Select Low */
359	u32 dct_sel_hi;		/* DRAM Controller Select High */
360	u32 online_spare;	/* On-Line spare Reg */
361	u32 gpu_umc_base;	/* Base address used for channel selection on GPUs */
362
363	/* x4, x8, or x16 syndromes in use */
364	u8 ecc_sym_sz;
365
366	char ctl_name[MAX_CTL_NAMELEN];
367	u16 f1_id, f2_id;
368	/* Maximum number of memory controllers per die/node. */
369	u8 max_mcs;
370
371	struct amd64_family_flags flags;
372	/* place to store error injection parameters prior to issue */
373	struct error_injection injection;
374
375	/*
376	 * cache the dram_type
377	 *
378	 * NOTE: Don't use this for Family 17h and later.
379	 *	 Use dram_type in struct amd64_umc instead.
380	 */
381	enum mem_type dram_type;
382
383	struct amd64_umc *umc;	/* UMC registers */
384};
385
386enum err_codes {
387	DECODE_OK	=  0,
388	ERR_NODE	= -1,
389	ERR_CSROW	= -2,
390	ERR_CHANNEL	= -3,
391	ERR_SYND	= -4,
392	ERR_NORM_ADDR	= -5,
393};
394
395struct err_info {
396	int err_code;
397	struct mem_ctl_info *src_mci;
398	int csrow;
399	int channel;
400	u16 syndrome;
401	u32 page;
402	u32 offset;
403};
404
405static inline u32 get_umc_base(u8 channel)
406{
407	/* chY: 0xY50000 */
408	return 0x50000 + (channel << 20);
409}
410
411static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
412{
413	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
414
415	if (boot_cpu_data.x86 == 0xf)
416		return addr;
417
418	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
419}
420
421static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
422{
423	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
424
425	if (boot_cpu_data.x86 == 0xf)
426		return lim;
427
428	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
429}
430
431static inline u16 extract_syndrome(u64 status)
432{
433	return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
434}
435
436static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
437{
438	if (pvt->fam == 0x15 && pvt->model >= 0x30)
439		return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
440			((pvt->dct_sel_lo >> 6) & 0x3);
441
442	return	((pvt)->dct_sel_lo >> 6) & 0x3;
443}
444/*
445 * per-node ECC settings descriptor
446 */
447struct ecc_settings {
448	u32 old_nbctl;
449	bool nbctl_valid;
450
451	struct flags {
452		unsigned long nb_mce_enable:1;
453		unsigned long nb_ecc_prev:1;
454	} flags;
455};
456
457/*
458 * Each of the PCI Device IDs types have their own set of hardware accessor
459 * functions and per device encoding/decoding logic.
460 */
461struct low_ops {
462	void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci, u64 sys_addr,
463				     struct err_info *err);
464	int  (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct,
465			   unsigned int cs_mode, int cs_mask_nr);
466	int (*hw_info_get)(struct amd64_pvt *pvt);
467	bool (*ecc_enabled)(struct amd64_pvt *pvt);
468	void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci);
469	void (*dump_misc_regs)(struct amd64_pvt *pvt);
470	void (*get_err_info)(struct mce *m, struct err_info *err);
471};
472
473int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
474			       u32 *val, const char *func);
475int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
476				u32 val, const char *func);
477
478#define amd64_read_pci_cfg(pdev, offset, val)	\
479	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
480
481#define amd64_write_pci_cfg(pdev, offset, val)	\
482	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
483
484#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
485
486/* Injection helpers */
487static inline void disable_caches(void *dummy)
488{
489	write_cr0(read_cr0() | X86_CR0_CD);
490	wbinvd();
491}
492
493static inline void enable_caches(void *dummy)
494{
495	write_cr0(read_cr0() & ~X86_CR0_CD);
496}
497
498static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
499{
500	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
501		u32 tmp;
502		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
503		return (u8) tmp & 0xF;
504	}
505	return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
506}
507
508static inline u8 dhar_valid(struct amd64_pvt *pvt)
509{
510	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
511		u32 tmp;
512		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
513		return (tmp >> 1) & BIT(0);
514	}
515	return (pvt)->dhar & BIT(0);
516}
517
518static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
519{
520	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
521		u32 tmp;
522		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
523		return (tmp >> 11) & 0x1FFF;
524	}
525	return (pvt)->dct_sel_lo & 0xFFFFF800;
526}