altera_edac.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 *  Copyright (C) 2017-2018, Intel Corporation. All rights reserved
   4 *  Copyright Altera Corporation (C) 2014-2016. All rights reserved.
   5 *  Copyright 2011-2012 Calxeda, Inc.
   6 */
   7
   8#include <asm/cacheflush.h>
   9#include <linux/ctype.h>
  10#include <linux/delay.h>
  11#include <linux/edac.h>
  12#include <linux/firmware/intel/stratix10-smc.h>
  13#include <linux/genalloc.h>
  14#include <linux/interrupt.h>
  15#include <linux/irqchip/chained_irq.h>
  16#include <linux/kernel.h>
  17#include <linux/mfd/altera-sysmgr.h>
  18#include <linux/mfd/syscon.h>
  19#include <linux/notifier.h>
  20#include <linux/of_address.h>
  21#include <linux/of_irq.h>
  22#include <linux/of_platform.h>
  23#include <linux/panic_notifier.h>
  24#include <linux/platform_device.h>
  25#include <linux/property.h>
  26#include <linux/regmap.h>
  27#include <linux/types.h>
  28#include <linux/uaccess.h>
  29
  30#include "altera_edac.h"
  31#include "edac_module.h"
  32
  33#define EDAC_MOD_STR		"altera_edac"
  34#define EDAC_DEVICE		"Altera"
  35
  36#ifdef CONFIG_EDAC_ALTERA_SDRAM
  37static const struct altr_sdram_prv_data c5_data = {
  38	.ecc_ctrl_offset    = CV_CTLCFG_OFST,
  39	.ecc_ctl_en_mask    = CV_CTLCFG_ECC_AUTO_EN,
  40	.ecc_stat_offset    = CV_DRAMSTS_OFST,
  41	.ecc_stat_ce_mask   = CV_DRAMSTS_SBEERR,
  42	.ecc_stat_ue_mask   = CV_DRAMSTS_DBEERR,
  43	.ecc_saddr_offset   = CV_ERRADDR_OFST,
  44	.ecc_daddr_offset   = CV_ERRADDR_OFST,
  45	.ecc_cecnt_offset   = CV_SBECOUNT_OFST,
  46	.ecc_uecnt_offset   = CV_DBECOUNT_OFST,
  47	.ecc_irq_en_offset  = CV_DRAMINTR_OFST,
  48	.ecc_irq_en_mask    = CV_DRAMINTR_INTREN,
  49	.ecc_irq_clr_offset = CV_DRAMINTR_OFST,
  50	.ecc_irq_clr_mask   = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
  51	.ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
  52	.ecc_cnt_rst_mask   = CV_DRAMINTR_INTRCLR,
  53	.ce_ue_trgr_offset  = CV_CTLCFG_OFST,
  54	.ce_set_mask        = CV_CTLCFG_GEN_SB_ERR,
  55	.ue_set_mask        = CV_CTLCFG_GEN_DB_ERR,
  56};
  57
  58static const struct altr_sdram_prv_data a10_data = {
  59	.ecc_ctrl_offset    = A10_ECCCTRL1_OFST,
  60	.ecc_ctl_en_mask    = A10_ECCCTRL1_ECC_EN,
  61	.ecc_stat_offset    = A10_INTSTAT_OFST,
  62	.ecc_stat_ce_mask   = A10_INTSTAT_SBEERR,
  63	.ecc_stat_ue_mask   = A10_INTSTAT_DBEERR,
  64	.ecc_saddr_offset   = A10_SERRADDR_OFST,
  65	.ecc_daddr_offset   = A10_DERRADDR_OFST,
  66	.ecc_irq_en_offset  = A10_ERRINTEN_OFST,
  67	.ecc_irq_en_mask    = A10_ECC_IRQ_EN_MASK,
  68	.ecc_irq_clr_offset = A10_INTSTAT_OFST,
  69	.ecc_irq_clr_mask   = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
  70	.ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
  71	.ecc_cnt_rst_mask   = A10_ECC_CNT_RESET_MASK,
  72	.ce_ue_trgr_offset  = A10_DIAGINTTEST_OFST,
  73	.ce_set_mask        = A10_DIAGINT_TSERRA_MASK,
  74	.ue_set_mask        = A10_DIAGINT_TDERRA_MASK,
  75};
  76
  77/*********************** EDAC Memory Controller Functions ****************/
  78
  79/* The SDRAM controller uses the EDAC Memory Controller framework.       */
  80
  81static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
  82{
  83	struct mem_ctl_info *mci = dev_id;
  84	struct altr_sdram_mc_data *drvdata = mci->pvt_info;
  85	const struct altr_sdram_prv_data *priv = drvdata->data;
  86	u32 status, err_count = 1, err_addr;
  87
  88	regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
  89
  90	if (status & priv->ecc_stat_ue_mask) {
  91		regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
  92			    &err_addr);
  93		if (priv->ecc_uecnt_offset)
  94			regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
  95				    &err_count);
  96		panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
  97		      err_count, err_addr);
  98	}
  99	if (status & priv->ecc_stat_ce_mask) {
 100		regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
 101			    &err_addr);
 102		if (priv->ecc_cecnt_offset)
 103			regmap_read(drvdata->mc_vbase,  priv->ecc_cecnt_offset,
 104				    &err_count);
 105		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
 106				     err_addr >> PAGE_SHIFT,
 107				     err_addr & ~PAGE_MASK, 0,
 108				     0, 0, -1, mci->ctl_name, "");
 109		/* Clear IRQ to resume */
 110		regmap_write(drvdata->mc_vbase,	priv->ecc_irq_clr_offset,
 111			     priv->ecc_irq_clr_mask);
 112
 113		return IRQ_HANDLED;
 114	}
 115	return IRQ_NONE;
 116}
 117
 118static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
 119					    const char __user *data,
 120					    size_t count, loff_t *ppos)
 121{
 122	struct mem_ctl_info *mci = file->private_data;
 123	struct altr_sdram_mc_data *drvdata = mci->pvt_info;
 124	const struct altr_sdram_prv_data *priv = drvdata->data;
 125	u32 *ptemp;
 126	dma_addr_t dma_handle;
 127	u32 reg, read_reg;
 128
 129	ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
 130	if (!ptemp) {
 131		edac_printk(KERN_ERR, EDAC_MC,
 132			    "Inject: Buffer Allocation error\n");
 133		return -ENOMEM;
 134	}
 135
 136	regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 137		    &read_reg);
 138	read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
 139
 140	/* Error are injected by writing a word while the SBE or DBE
 141	 * bit in the CTLCFG register is set. Reading the word will
 142	 * trigger the SBE or DBE error and the corresponding IRQ.
 143	 */
 144	if (count == 3) {
 145		edac_printk(KERN_ALERT, EDAC_MC,
 146			    "Inject Double bit error\n");
 147		local_irq_disable();
 148		regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
 149			     (read_reg | priv->ue_set_mask));
 150		local_irq_enable();
 151	} else {
 152		edac_printk(KERN_ALERT, EDAC_MC,
 153			    "Inject Single bit error\n");
 154		local_irq_disable();
 155		regmap_write(drvdata->mc_vbase,	priv->ce_ue_trgr_offset,
 156			     (read_reg | priv->ce_set_mask));
 157		local_irq_enable();
 158	}
 159
 160	ptemp[0] = 0x5A5A5A5A;
 161	ptemp[1] = 0xA5A5A5A5;
 162
 163	/* Clear the error injection bits */
 164	regmap_write(drvdata->mc_vbase,	priv->ce_ue_trgr_offset, read_reg);
 165	/* Ensure it has been written out */
 166	wmb();
 167
 168	/*
 169	 * To trigger the error, we need to read the data back
 170	 * (the data was written with errors above).
 171	 * The READ_ONCE macros and printk are used to prevent the
 172	 * the compiler optimizing these reads out.
 173	 */
 174	reg = READ_ONCE(ptemp[0]);
 175	read_reg = READ_ONCE(ptemp[1]);
 176	/* Force Read */
 177	rmb();
 178
 179	edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
 180		    reg, read_reg);
 181
 182	dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
 183
 184	return count;
 185}
 186
 187static const struct file_operations altr_sdr_mc_debug_inject_fops = {
 188	.open = simple_open,
 189	.write = altr_sdr_mc_err_inject_write,
 190	.llseek = generic_file_llseek,
 191};
 192
 193static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
 194{
 195	if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
 196		return;
 197
 198	if (!mci->debugfs)
 199		return;
 200
 201	edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
 202				 &altr_sdr_mc_debug_inject_fops);
 203}
 204
 205/* Get total memory size from Open Firmware DTB */
 206static unsigned long get_total_mem(void)
 207{
 208	struct device_node *np = NULL;
 209	struct resource res;
 210	int ret;
 211	unsigned long total_mem = 0;
 212
 213	for_each_node_by_type(np, "memory") {
 214		ret = of_address_to_resource(np, 0, &res);
 215		if (ret)
 216			continue;
 217
 218		total_mem += resource_size(&res);
 219	}
 220	edac_dbg(0, "total_mem 0x%lx\n", total_mem);
 221	return total_mem;
 222}
 223
 224static const struct of_device_id altr_sdram_ctrl_of_match[] = {
 225	{ .compatible = "altr,sdram-edac", .data = &c5_data},
 226	{ .compatible = "altr,sdram-edac-a10", .data = &a10_data},
 227	{},
 228};
 229MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
 230
 231static int a10_init(struct regmap *mc_vbase)
 232{
 233	if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
 234			       A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
 235		edac_printk(KERN_ERR, EDAC_MC,
 236			    "Error setting SB IRQ mode\n");
 237		return -ENODEV;
 238	}
 239
 240	if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
 241		edac_printk(KERN_ERR, EDAC_MC,
 242			    "Error setting trigger count\n");
 243		return -ENODEV;
 244	}
 245
 246	return 0;
 247}
 248
 249static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
 250{
 251	void __iomem  *sm_base;
 252	int  ret = 0;
 253
 254	if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
 255				dev_name(&pdev->dev))) {
 256		edac_printk(KERN_ERR, EDAC_MC,
 257			    "Unable to request mem region\n");
 258		return -EBUSY;
 259	}
 260
 261	sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
 262	if (!sm_base) {
 263		edac_printk(KERN_ERR, EDAC_MC,
 264			    "Unable to ioremap device\n");
 265
 266		ret = -ENOMEM;
 267		goto release;
 268	}
 269
 270	iowrite32(mask, sm_base);
 271
 272	iounmap(sm_base);
 273
 274release:
 275	release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
 276
 277	return ret;
 278}
 279
 280static int altr_sdram_probe(struct platform_device *pdev)
 281{
 282	struct edac_mc_layer layers[2];
 283	struct mem_ctl_info *mci;
 284	struct altr_sdram_mc_data *drvdata;
 285	const struct altr_sdram_prv_data *priv;
 286	struct regmap *mc_vbase;
 287	struct dimm_info *dimm;
 288	u32 read_reg;
 289	int irq, irq2, res = 0;
 290	unsigned long mem_size, irqflags = 0;
 291
 292	/* Grab the register range from the sdr controller in device tree */
 293	mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 294						   "altr,sdr-syscon");
 295	if (IS_ERR(mc_vbase)) {
 296		edac_printk(KERN_ERR, EDAC_MC,
 297			    "regmap for altr,sdr-syscon lookup failed.\n");
 298		return -ENODEV;
 299	}
 300
 301	/* Check specific dependencies for the module */
 302	priv = device_get_match_data(&pdev->dev);
 303
 304	/* Validate the SDRAM controller has ECC enabled */
 305	if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
 306	    ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
 307		edac_printk(KERN_ERR, EDAC_MC,
 308			    "No ECC/ECC disabled [0x%08X]\n", read_reg);
 309		return -ENODEV;
 310	}
 311
 312	/* Grab memory size from device tree. */
 313	mem_size = get_total_mem();
 314	if (!mem_size) {
 315		edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
 316		return -ENODEV;
 317	}
 318
 319	/* Ensure the SDRAM Interrupt is disabled */
 320	if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
 321			       priv->ecc_irq_en_mask, 0)) {
 322		edac_printk(KERN_ERR, EDAC_MC,
 323			    "Error disabling SDRAM ECC IRQ\n");
 324		return -ENODEV;
 325	}
 326
 327	/* Toggle to clear the SDRAM Error count */
 328	if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
 329			       priv->ecc_cnt_rst_mask,
 330			       priv->ecc_cnt_rst_mask)) {
 331		edac_printk(KERN_ERR, EDAC_MC,
 332			    "Error clearing SDRAM ECC count\n");
 333		return -ENODEV;
 334	}
 335
 336	if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
 337			       priv->ecc_cnt_rst_mask, 0)) {
 338		edac_printk(KERN_ERR, EDAC_MC,
 339			    "Error clearing SDRAM ECC count\n");
 340		return -ENODEV;
 341	}
 342
 343	irq = platform_get_irq(pdev, 0);
 344	if (irq < 0) {
 345		edac_printk(KERN_ERR, EDAC_MC,
 346			    "No irq %d in DT\n", irq);
 347		return irq;
 348	}
 349
 350	/* Arria10 has a 2nd IRQ */
 351	irq2 = platform_get_irq(pdev, 1);
 352
 353	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
 354	layers[0].size = 1;
 355	layers[0].is_virt_csrow = true;
 356	layers[1].type = EDAC_MC_LAYER_CHANNEL;
 357	layers[1].size = 1;
 358	layers[1].is_virt_csrow = false;
 359	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
 360			    sizeof(struct altr_sdram_mc_data));
 361	if (!mci)
 362		return -ENOMEM;
 363
 364	mci->pdev = &pdev->dev;
 365	drvdata = mci->pvt_info;
 366	drvdata->mc_vbase = mc_vbase;
 367	drvdata->data = priv;
 368	platform_set_drvdata(pdev, mci);
 369
 370	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
 371		edac_printk(KERN_ERR, EDAC_MC,
 372			    "Unable to get managed device resource\n");
 373		res = -ENOMEM;
 374		goto free;
 375	}
 376
 377	mci->mtype_cap = MEM_FLAG_DDR3;
 378	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 379	mci->edac_cap = EDAC_FLAG_SECDED;
 380	mci->mod_name = EDAC_MOD_STR;
 381	mci->ctl_name = dev_name(&pdev->dev);
 382	mci->scrub_mode = SCRUB_SW_SRC;
 383	mci->dev_name = dev_name(&pdev->dev);
 384
 385	dimm = *mci->dimms;
 386	dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
 387	dimm->grain = 8;
 388	dimm->dtype = DEV_X8;
 389	dimm->mtype = MEM_DDR3;
 390	dimm->edac_mode = EDAC_SECDED;
 391
 392	res = edac_mc_add_mc(mci);
 393	if (res < 0)
 394		goto err;
 395
 396	/* Only the Arria10 has separate IRQs */
 397	if (of_machine_is_compatible("altr,socfpga-arria10")) {
 398		/* Arria10 specific initialization */
 399		res = a10_init(mc_vbase);
 400		if (res < 0)
 401			goto err2;
 402
 403		res = devm_request_irq(&pdev->dev, irq2,
 404				       altr_sdram_mc_err_handler,
 405				       IRQF_SHARED, dev_name(&pdev->dev), mci);
 406		if (res < 0) {
 407			edac_mc_printk(mci, KERN_ERR,
 408				       "Unable to request irq %d\n", irq2);
 409			res = -ENODEV;
 410			goto err2;
 411		}
 412
 413		res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
 414		if (res < 0)
 415			goto err2;
 416
 417		irqflags = IRQF_SHARED;
 418	}
 419
 420	res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
 421			       irqflags, dev_name(&pdev->dev), mci);
 422	if (res < 0) {
 423		edac_mc_printk(mci, KERN_ERR,
 424			       "Unable to request irq %d\n", irq);
 425		res = -ENODEV;
 426		goto err2;
 427	}
 428
 429	/* Infrastructure ready - enable the IRQ */
 430	if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
 431			       priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
 432		edac_mc_printk(mci, KERN_ERR,
 433			       "Error enabling SDRAM ECC IRQ\n");
 434		res = -ENODEV;
 435		goto err2;
 436	}
 437
 438	altr_sdr_mc_create_debugfs_nodes(mci);
 439
 440	devres_close_group(&pdev->dev, NULL);
 441
 442	return 0;
 443
 444err2:
 445	edac_mc_del_mc(&pdev->dev);
 446err:
 447	devres_release_group(&pdev->dev, NULL);
 448free:
 449	edac_mc_free(mci);
 450	edac_printk(KERN_ERR, EDAC_MC,
 451		    "EDAC Probe Failed; Error %d\n", res);
 452
 453	return res;
 454}
 455
 456static void altr_sdram_remove(struct platform_device *pdev)
 457{
 458	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
 459
 460	edac_mc_del_mc(&pdev->dev);
 461	edac_mc_free(mci);
 462	platform_set_drvdata(pdev, NULL);
 463}
 464
 465/*
 466 * If you want to suspend, need to disable EDAC by removing it
 467 * from the device tree or defconfig.
 468 */
 469#ifdef CONFIG_PM
 470static int altr_sdram_prepare(struct device *dev)
 471{
 472	pr_err("Suspend not allowed when EDAC is enabled.\n");
 473
 474	return -EPERM;
 475}
 476
 477static const struct dev_pm_ops altr_sdram_pm_ops = {
 478	.prepare = altr_sdram_prepare,
 479};
 480#endif
 481
 482static struct platform_driver altr_sdram_edac_driver = {
 483	.probe = altr_sdram_probe,
 484	.remove = altr_sdram_remove,
 485	.driver = {
 486		.name = "altr_sdram_edac",
 487#ifdef CONFIG_PM
 488		.pm = &altr_sdram_pm_ops,
 489#endif
 490		.of_match_table = altr_sdram_ctrl_of_match,
 491	},
 492};
 493
 494module_platform_driver(altr_sdram_edac_driver);
 495
 496#endif	/* CONFIG_EDAC_ALTERA_SDRAM */
 497
 498/************************* EDAC Parent Probe *************************/
 499
 500static const struct of_device_id altr_edac_device_of_match[];
 501
 502static const struct of_device_id altr_edac_of_match[] = {
 503	{ .compatible = "altr,socfpga-ecc-manager" },
 504	{},
 505};
 506MODULE_DEVICE_TABLE(of, altr_edac_of_match);
 507
 508static int altr_edac_probe(struct platform_device *pdev)
 509{
 510	of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
 511			     NULL, &pdev->dev);
 512	return 0;
 513}
 514
 515static struct platform_driver altr_edac_driver = {
 516	.probe =  altr_edac_probe,
 517	.driver = {
 518		.name = "socfpga_ecc_manager",
 519		.of_match_table = altr_edac_of_match,
 520	},
 521};
 522module_platform_driver(altr_edac_driver);
 523
 524/************************* EDAC Device Functions *************************/
 525
 526/*
 527 * EDAC Device Functions (shared between various IPs).
 528 * The discrete memories use the EDAC Device framework. The probe
 529 * and error handling functions are very similar between memories
 530 * so they are shared. The memory allocation and freeing for EDAC
 531 * trigger testing are different for each memory.
 532 */
 533
 534#ifdef CONFIG_EDAC_ALTERA_OCRAM
 535static const struct edac_device_prv_data ocramecc_data;
 536#endif
 537#ifdef CONFIG_EDAC_ALTERA_L2C
 538static const struct edac_device_prv_data l2ecc_data;
 539#endif
 540#ifdef CONFIG_EDAC_ALTERA_OCRAM
 541static const struct edac_device_prv_data a10_ocramecc_data;
 542#endif
 543#ifdef CONFIG_EDAC_ALTERA_L2C
 544static const struct edac_device_prv_data a10_l2ecc_data;
 545#endif
 546
 547static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
 548{
 549	irqreturn_t ret_value = IRQ_NONE;
 550	struct edac_device_ctl_info *dci = dev_id;
 551	struct altr_edac_device_dev *drvdata = dci->pvt_info;
 552	const struct edac_device_prv_data *priv = drvdata->data;
 553
 554	if (irq == drvdata->sb_irq) {
 555		if (priv->ce_clear_mask)
 556			writel(priv->ce_clear_mask, drvdata->base);
 557		edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
 558		ret_value = IRQ_HANDLED;
 559	} else if (irq == drvdata->db_irq) {
 560		if (priv->ue_clear_mask)
 561			writel(priv->ue_clear_mask, drvdata->base);
 562		edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
 563		panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
 564		ret_value = IRQ_HANDLED;
 565	} else {
 566		WARN_ON(1);
 567	}
 568
 569	return ret_value;
 570}
 571
 572static ssize_t __maybe_unused
 573altr_edac_device_trig(struct file *file, const char __user *user_buf,
 574		      size_t count, loff_t *ppos)
 575
 576{
 577	u32 *ptemp, i, error_mask;
 578	int result = 0;
 579	u8 trig_type;
 580	unsigned long flags;
 581	struct edac_device_ctl_info *edac_dci = file->private_data;
 582	struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
 583	const struct edac_device_prv_data *priv = drvdata->data;
 584	void *generic_ptr = edac_dci->dev;
 585
 586	if (!user_buf || get_user(trig_type, user_buf))
 587		return -EFAULT;
 588
 589	if (!priv->alloc_mem)
 590		return -ENOMEM;
 591
 592	/*
 593	 * Note that generic_ptr is initialized to the device * but in
 594	 * some alloc_functions, this is overridden and returns data.
 595	 */
 596	ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
 597	if (!ptemp) {
 598		edac_printk(KERN_ERR, EDAC_DEVICE,
 599			    "Inject: Buffer Allocation error\n");
 600		return -ENOMEM;
 601	}
 602
 603	if (trig_type == ALTR_UE_TRIGGER_CHAR)
 604		error_mask = priv->ue_set_mask;
 605	else
 606		error_mask = priv->ce_set_mask;
 607
 608	edac_printk(KERN_ALERT, EDAC_DEVICE,
 609		    "Trigger Error Mask (0x%X)\n", error_mask);
 610
 611	local_irq_save(flags);
 612	/* write ECC corrupted data out. */
 613	for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
 614		/* Read data so we're in the correct state */
 615		rmb();
 616		if (READ_ONCE(ptemp[i]))
 617			result = -1;
 618		/* Toggle Error bit (it is latched), leave ECC enabled */
 619		writel(error_mask, (drvdata->base + priv->set_err_ofst));
 620		writel(priv->ecc_enable_mask, (drvdata->base +
 621					       priv->set_err_ofst));
 622		ptemp[i] = i;
 623	}
 624	/* Ensure it has been written out */
 625	wmb();
 626	local_irq_restore(flags);
 627
 628	if (result)
 629		edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
 630
 631	/* Read out written data. ECC error caused here */
 632	for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
 633		if (READ_ONCE(ptemp[i]) != i)
 634			edac_printk(KERN_ERR, EDAC_DEVICE,
 635				    "Read doesn't match written data\n");
 636
 637	if (priv->free_mem)
 638		priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
 639
 640	return count;
 641}
 642
 643static const struct file_operations altr_edac_device_inject_fops __maybe_unused = {
 644	.open = simple_open,
 645	.write = altr_edac_device_trig,
 646	.llseek = generic_file_llseek,
 647};
 648
 649static ssize_t __maybe_unused
 650altr_edac_a10_device_trig(struct file *file, const char __user *user_buf,
 651			  size_t count, loff_t *ppos);
 652
 653static const struct file_operations altr_edac_a10_device_inject_fops __maybe_unused = {
 654	.open = simple_open,
 655	.write = altr_edac_a10_device_trig,
 656	.llseek = generic_file_llseek,
 657};
 658
 659static ssize_t __maybe_unused
 660altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf,
 661			   size_t count, loff_t *ppos);
 662
 663static const struct file_operations altr_edac_a10_device_inject2_fops __maybe_unused = {
 664	.open = simple_open,
 665	.write = altr_edac_a10_device_trig2,
 666	.llseek = generic_file_llseek,
 667};
 668
 669static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
 670				      const struct edac_device_prv_data *priv)
 671{
 672	struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
 673
 674	if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
 675		return;
 676
 677	drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
 678	if (!drvdata->debugfs_dir)
 679		return;
 680
 681	if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
 682				      drvdata->debugfs_dir, edac_dci,
 683				      priv->inject_fops))
 684		debugfs_remove_recursive(drvdata->debugfs_dir);
 685}
 686
 687static const struct of_device_id altr_edac_device_of_match[] = {
 688#ifdef CONFIG_EDAC_ALTERA_L2C
 689	{ .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
 690#endif
 691#ifdef CONFIG_EDAC_ALTERA_OCRAM
 692	{ .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
 693#endif
 694	{},
 695};
 696MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
 697
 698/*
 699 * altr_edac_device_probe()
 700 *	This is a generic EDAC device driver that will support
 701 *	various Altera memory devices such as the L2 cache ECC and
 702 *	OCRAM ECC as well as the memories for other peripherals.
 703 *	Module specific initialization is done by passing the
 704 *	function index in the device tree.
 705 */
 706static int altr_edac_device_probe(struct platform_device *pdev)
 707{
 708	struct edac_device_ctl_info *dci;
 709	struct altr_edac_device_dev *drvdata;
 710	struct resource *r;
 711	int res = 0;
 712	struct device_node *np = pdev->dev.of_node;
 713	char *ecc_name = (char *)np->name;
 714	static int dev_instance;
 715
 716	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
 717		edac_printk(KERN_ERR, EDAC_DEVICE,
 718			    "Unable to open devm\n");
 719		return -ENOMEM;
 720	}
 721
 722	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 723	if (!r) {
 724		edac_printk(KERN_ERR, EDAC_DEVICE,
 725			    "Unable to get mem resource\n");
 726		res = -ENODEV;
 727		goto fail;
 728	}
 729
 730	if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
 731				     dev_name(&pdev->dev))) {
 732		edac_printk(KERN_ERR, EDAC_DEVICE,
 733			    "%s:Error requesting mem region\n", ecc_name);
 734		res = -EBUSY;
 735		goto fail;
 736	}
 737
 738	dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
 739					 1, ecc_name, 1, 0, dev_instance++);
 740
 741	if (!dci) {
 742		edac_printk(KERN_ERR, EDAC_DEVICE,
 743			    "%s: Unable to allocate EDAC device\n", ecc_name);
 744		res = -ENOMEM;
 745		goto fail;
 746	}
 747
 748	drvdata = dci->pvt_info;
 749	dci->dev = &pdev->dev;
 750	platform_set_drvdata(pdev, dci);
 751	drvdata->edac_dev_name = ecc_name;
 752
 753	drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
 754	if (!drvdata->base) {
 755		res = -ENOMEM;
 756		goto fail1;
 757	}
 758
 759	/* Get driver specific data for this EDAC device */
 760	drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
 761
 762	/* Check specific dependencies for the module */
 763	if (drvdata->data->setup) {
 764		res = drvdata->data->setup(drvdata);
 765		if (res)
 766			goto fail1;
 767	}
 768
 769	drvdata->sb_irq = platform_get_irq(pdev, 0);
 770	res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
 771			       altr_edac_device_handler,
 772			       0, dev_name(&pdev->dev), dci);
 773	if (res)
 774		goto fail1;
 775
 776	drvdata->db_irq = platform_get_irq(pdev, 1);
 777	res = devm_request_irq(&pdev->dev, drvdata->db_irq,
 778			       altr_edac_device_handler,
 779			       0, dev_name(&pdev->dev), dci);
 780	if (res)
 781		goto fail1;
 782
 783	dci->mod_name = "Altera ECC Manager";
 784	dci->dev_name = drvdata->edac_dev_name;
 785
 786	res = edac_device_add_device(dci);
 787	if (res)
 788		goto fail1;
 789
 790	altr_create_edacdev_dbgfs(dci, drvdata->data);
 791
 792	devres_close_group(&pdev->dev, NULL);
 793
 794	return 0;
 795
 796fail1:
 797	edac_device_free_ctl_info(dci);
 798fail:
 799	devres_release_group(&pdev->dev, NULL);
 800	edac_printk(KERN_ERR, EDAC_DEVICE,
 801		    "%s:Error setting up EDAC device: %d\n", ecc_name, res);
 802
 803	return res;
 804}
 805
 806static void altr_edac_device_remove(struct platform_device *pdev)
 807{
 808	struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
 809	struct altr_edac_device_dev *drvdata = dci->pvt_info;
 810
 811	debugfs_remove_recursive(drvdata->debugfs_dir);
 812	edac_device_del_device(&pdev->dev);
 813	edac_device_free_ctl_info(dci);
 814}
 815
 816static struct platform_driver altr_edac_device_driver = {
 817	.probe =  altr_edac_device_probe,
 818	.remove = altr_edac_device_remove,
 819	.driver = {
 820		.name = "altr_edac_device",
 821		.of_match_table = altr_edac_device_of_match,
 822	},
 823};
 824module_platform_driver(altr_edac_device_driver);
 825
 826/******************* Arria10 Device ECC Shared Functions *****************/
 827
 828/*
 829 *  Test for memory's ECC dependencies upon entry because platform specific
 830 *  startup should have initialized the memory and enabled the ECC.
 831 *  Can't turn on ECC here because accessing un-initialized memory will
 832 *  cause CE/UE errors possibly causing an ABORT.
 833 */
 834static int __maybe_unused
 835altr_check_ecc_deps(struct altr_edac_device_dev *device)
 836{
 837	void __iomem  *base = device->base;
 838	const struct edac_device_prv_data *prv = device->data;
 839
 840	if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
 841		return 0;
 842
 843	edac_printk(KERN_ERR, EDAC_DEVICE,
 844		    "%s: No ECC present or ECC disabled.\n",
 845		    device->edac_dev_name);
 846	return -ENODEV;
 847}
 848
 849static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
 850{
 851	struct altr_edac_device_dev *dci = dev_id;
 852	void __iomem  *base = dci->base;
 853
 854	if (irq == dci->sb_irq) {
 855		writel(ALTR_A10_ECC_SERRPENA,
 856		       base + ALTR_A10_ECC_INTSTAT_OFST);
 857		edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
 858
 859		return IRQ_HANDLED;
 860	} else if (irq == dci->db_irq) {
 861		writel(ALTR_A10_ECC_DERRPENA,
 862		       base + ALTR_A10_ECC_INTSTAT_OFST);
 863		edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
 864		if (dci->data->panic)
 865			panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
 866
 867		return IRQ_HANDLED;
 868	}
 869
 870	WARN_ON(1);
 871
 872	return IRQ_NONE;
 873}
 874
 875/******************* Arria10 Memory Buffer Functions *********************/
 876
 877static inline int a10_get_irq_mask(struct device_node *np)
 878{
 879	int irq;
 880	const u32 *handle = of_get_property(np, "interrupts", NULL);
 881
 882	if (!handle)
 883		return -ENODEV;
 884	irq = be32_to_cpup(handle);
 885	return irq;
 886}
 887
 888static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
 889{
 890	u32 value = readl(ioaddr);
 891
 892	value |= bit_mask;
 893	writel(value, ioaddr);
 894}
 895
 896static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
 897{
 898	u32 value = readl(ioaddr);
 899
 900	value &= ~bit_mask;
 901	writel(value, ioaddr);
 902}
 903
 904static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
 905{
 906	u32 value = readl(ioaddr);
 907
 908	return (value & bit_mask) ? 1 : 0;
 909}
 910
 911/*
 912 * This function uses the memory initialization block in the Arria10 ECC
 913 * controller to initialize/clear the entire memory data and ECC data.
 914 */
 915static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
 916{
 917	int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
 918	u32 init_mask, stat_mask, clear_mask;
 919	int ret = 0;
 920
 921	if (port) {
 922		init_mask = ALTR_A10_ECC_INITB;
 923		stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
 924		clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
 925	} else {
 926		init_mask = ALTR_A10_ECC_INITA;
 927		stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
 928		clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
 929	}
 930
 931	ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
 932	while (limit--) {
 933		if (ecc_test_bits(stat_mask,
 934				  (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
 935			break;
 936		udelay(1);
 937	}
 938	if (limit < 0)
 939		ret = -EBUSY;
 940
 941	/* Clear any pending ECC interrupts */
 942	writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
 943
 944	return ret;
 945}
 946
 947static __init int __maybe_unused
 948altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
 949			u32 ecc_ctrl_en_mask, bool dual_port)
 950{
 951	int ret = 0;
 952	void __iomem *ecc_block_base;
 953	struct regmap *ecc_mgr_map;
 954	char *ecc_name;
 955	struct device_node *np_eccmgr;
 956
 957	ecc_name = (char *)np->name;
 958
 959	/* Get the ECC Manager - parent of the device EDACs */
 960	np_eccmgr = of_get_parent(np);
 961
 962	ecc_mgr_map =
 963		altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr,
 964						     "altr,sysmgr-syscon");
 965
 966	of_node_put(np_eccmgr);
 967	if (IS_ERR(ecc_mgr_map)) {
 968		edac_printk(KERN_ERR, EDAC_DEVICE,
 969			    "Unable to get syscon altr,sysmgr-syscon\n");
 970		return -ENODEV;
 971	}
 972
 973	/* Map the ECC Block */
 974	ecc_block_base = of_iomap(np, 0);
 975	if (!ecc_block_base) {
 976		edac_printk(KERN_ERR, EDAC_DEVICE,
 977			    "Unable to map %s ECC block\n", ecc_name);
 978		return -ENODEV;
 979	}
 980
 981	/* Disable ECC */
 982	regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
 983	writel(ALTR_A10_ECC_SERRINTEN,
 984	       (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
 985	ecc_clear_bits(ecc_ctrl_en_mask,
 986		       (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
 987	/* Ensure all writes complete */
 988	wmb();
 989	/* Use HW initialization block to initialize memory for ECC */
 990	ret = altr_init_memory_port(ecc_block_base, 0);
 991	if (ret) {
 992		edac_printk(KERN_ERR, EDAC_DEVICE,
 993			    "ECC: cannot init %s PORTA memory\n", ecc_name);
 994		goto out;
 995	}
 996
 997	if (dual_port) {
 998		ret = altr_init_memory_port(ecc_block_base, 1);
 999		if (ret) {
1000			edac_printk(KERN_ERR, EDAC_DEVICE,
1001				    "ECC: cannot init %s PORTB memory\n",
1002				    ecc_name);
1003			goto out;
1004		}
1005	}
1006
1007	/* Enable ECC */
1008	ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1009					ALTR_A10_ECC_CTRL_OFST));
1010	writel(ALTR_A10_ECC_SERRINTEN,
1011	       (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1012	regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1013	/* Ensure all writes complete */
1014	wmb();
1015out:
1016	iounmap(ecc_block_base);
1017	return ret;
1018}
1019
1020static int validate_parent_available(struct device_node *np);
1021static const struct of_device_id altr_edac_a10_device_of_match[];
1022static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1023{
1024	int irq;
1025	struct device_node *child, *np;
1026
1027	np = of_find_compatible_node(NULL, NULL,
1028				     "altr,socfpga-a10-ecc-manager");
1029	if (!np) {
1030		edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1031		return -ENODEV;
1032	}
1033
1034	for_each_child_of_node(np, child) {
1035		const struct of_device_id *pdev_id;
1036		const struct edac_device_prv_data *prv;
1037
1038		if (!of_device_is_available(child))
1039			continue;
1040		if (!of_device_is_compatible(child, compat))
1041			continue;
1042
1043		if (validate_parent_available(child))
1044			continue;
1045
1046		irq = a10_get_irq_mask(child);
1047		if (irq < 0)
1048			continue;
1049
1050		/* Get matching node and check for valid result */
1051		pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1052		if (IS_ERR_OR_NULL(pdev_id))
1053			continue;
1054
1055		/* Validate private data pointer before dereferencing */
1056		prv = pdev_id->data;
1057		if (!prv)
1058			continue;
1059
1060		altr_init_a10_ecc_block(child, BIT(irq),
1061					prv->ecc_enable_mask, 0);
1062	}
1063
1064	of_node_put(np);
1065	return 0;
1066}
1067
1068/*********************** SDRAM EDAC Device Functions *********************/
1069
1070#ifdef CONFIG_EDAC_ALTERA_SDRAM
1071
1072/*
1073 * A legacy U-Boot bug only enabled memory mapped access to the ECC Enable
1074 * register if ECC is enabled. Linux checks the ECC Enable register to
1075 * determine ECC status.
1076 * Use an SMC call (which always works) to determine ECC enablement.
1077 */
1078static int altr_s10_sdram_check_ecc_deps(struct altr_edac_device_dev *device)
1079{
1080	const struct edac_device_prv_data *prv = device->data;
1081	unsigned long sdram_ecc_addr;
1082	struct arm_smccc_res result;
1083	struct device_node *np;
1084	phys_addr_t sdram_addr;
1085	u32 read_reg;
1086	int ret;
1087
1088	np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
1089	if (!np)
1090		goto sdram_err;
1091
1092	sdram_addr = of_translate_address(np, of_get_address(np, 0,
1093							     NULL, NULL));
1094	of_node_put(np);
1095	sdram_ecc_addr = (unsigned long)sdram_addr + prv->ecc_en_ofst;
1096	arm_smccc_smc(INTEL_SIP_SMC_REG_READ, sdram_ecc_addr,
1097		      0, 0, 0, 0, 0, 0, &result);
1098	read_reg = (unsigned int)result.a1;
1099	ret = (int)result.a0;
1100	if (!ret && (read_reg & prv->ecc_enable_mask))
1101		return 0;
1102
1103sdram_err:
1104	edac_printk(KERN_ERR, EDAC_DEVICE,
1105		    "%s: No ECC present or ECC disabled.\n",
1106		    device->edac_dev_name);
1107	return -ENODEV;
1108}
1109
1110static const struct edac_device_prv_data s10_sdramecc_data = {
1111	.setup = altr_s10_sdram_check_ecc_deps,
1112	.ce_clear_mask = ALTR_S10_ECC_SERRPENA,
1113	.ue_clear_mask = ALTR_S10_ECC_DERRPENA,
1114	.ecc_enable_mask = ALTR_S10_ECC_EN,
1115	.ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST,
1116	.ce_set_mask = ALTR_S10_ECC_TSERRA,
1117	.ue_set_mask = ALTR_S10_ECC_TDERRA,
1118	.set_err_ofst = ALTR_S10_ECC_INTTEST_OFST,
1119	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1120	.inject_fops = &altr_edac_a10_device_inject_fops,
1121};
1122#endif /* CONFIG_EDAC_ALTERA_SDRAM */
1123
1124/*********************** OCRAM EDAC Device Functions *********************/
1125
1126#ifdef CONFIG_EDAC_ALTERA_OCRAM
1127
1128static void *ocram_alloc_mem(size_t size, void **other)
1129{
1130	struct device_node *np;
1131	struct gen_pool *gp;
1132	void *sram_addr;
1133
1134	np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1135	if (!np)
1136		return NULL;
1137
1138	gp = of_gen_pool_get(np, "iram", 0);
1139	of_node_put(np);
1140	if (!gp)
1141		return NULL;
1142
1143	sram_addr = (void *)gen_pool_alloc(gp, size);
1144	if (!sram_addr)
1145		return NULL;
1146
1147	memset(sram_addr, 0, size);
1148	/* Ensure data is written out */
1149	wmb();
1150
1151	/* Remember this handle for freeing  later */
1152	*other = gp;
1153
1154	return sram_addr;
1155}
1156
1157static void ocram_free_mem(void *p, size_t size, void *other)
1158{
1159	gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1160}
1161
1162static const struct edac_device_prv_data ocramecc_data = {
1163	.setup = altr_check_ecc_deps,
1164	.ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1165	.ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1166	.alloc_mem = ocram_alloc_mem,
1167	.free_mem = ocram_free_mem,
1168	.ecc_enable_mask = ALTR_OCR_ECC_EN,
1169	.ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1170	.ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1171	.ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1172	.set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1173	.trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1174	.inject_fops = &altr_edac_device_inject_fops,
1175};
1176
1177static int __maybe_unused
1178altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
1179{
1180	void __iomem  *base = device->base;
1181	int ret;
1182
1183	ret = altr_check_ecc_deps(device);
1184	if (ret)
1185		return ret;
1186
1187	/*
1188	 * Verify that OCRAM has been initialized.
1189	 * During a warm reset, OCRAM contents are retained, but the control
1190	 * and status registers are reset to their default values. Therefore,
1191	 * ECC must be explicitly re-enabled in the control register.
1192	 * Error condition: if INITCOMPLETEA is clear and ECC_EN is already set.
1193	 */
1194	if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
1195			   (base + ALTR_A10_ECC_INITSTAT_OFST))) {
1196		if (!ecc_test_bits(ALTR_A10_ECC_EN,
1197				   (base + ALTR_A10_ECC_CTRL_OFST)))
1198			ecc_set_bits(ALTR_A10_ECC_EN,
1199				     (base + ALTR_A10_ECC_CTRL_OFST));
1200		else
1201			return -ENODEV;
1202	}
1203
1204	/* Enable IRQ on Single Bit Error */
1205	writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
1206	/* Ensure all writes complete */
1207	wmb();
1208
1209	return 0;
1210}
1211
1212static const struct edac_device_prv_data a10_ocramecc_data = {
1213	.setup = altr_check_ocram_deps_init,
1214	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1215	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1216	.irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1217	.ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1218	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1219	.ce_set_mask = ALTR_A10_ECC_TSERRA,
1220	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1221	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1222	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1223	.inject_fops = &altr_edac_a10_device_inject2_fops,
1224	/*
1225	 * OCRAM panic on uncorrectable error because sleep/resume
1226	 * functions and FPGA contents are stored in OCRAM. Prefer
1227	 * a kernel panic over executing/loading corrupted data.
1228	 */
1229	.panic = true,
1230};
1231
1232#endif	/* CONFIG_EDAC_ALTERA_OCRAM */
1233
1234/********************* L2 Cache EDAC Device Functions ********************/
1235
1236#ifdef CONFIG_EDAC_ALTERA_L2C
1237
1238static void *l2_alloc_mem(size_t size, void **other)
1239{
1240	struct device *dev = *other;
1241	void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1242
1243	if (!ptemp)
1244		return NULL;
1245
1246	/* Make sure everything is written out */
1247	wmb();
1248
1249	/*
1250	 * Clean all cache levels up to LoC (includes L2)
1251	 * This ensures the corrupted data is written into
1252	 * L2 cache for readback test (which causes ECC error).
1253	 */
1254	flush_cache_all();
1255
1256	return ptemp;
1257}
1258
1259static void l2_free_mem(void *p, size_t size, void *other)
1260{
1261	struct device *dev = other;
1262
1263	if (dev && p)
1264		devm_kfree(dev, p);
1265}
1266
1267/*
1268 * altr_l2_check_deps()
1269 *	Test for L2 cache ECC dependencies upon entry because
1270 *	platform specific startup should have initialized the L2
1271 *	memory and enabled the ECC.
1272 *	Bail if ECC is not enabled.
1273 *	Note that L2 Cache Enable is forced at build time.
1274 */
1275static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1276{
1277	void __iomem *base = device->base;
1278	const struct edac_device_prv_data *prv = device->data;
1279
1280	if ((readl(base) & prv->ecc_enable_mask) ==
1281	     prv->ecc_enable_mask)
1282		return 0;
1283
1284	edac_printk(KERN_ERR, EDAC_DEVICE,
1285		    "L2: No ECC present, or ECC disabled\n");
1286	return -ENODEV;
1287}
1288
1289static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1290{
1291	struct altr_edac_device_dev *dci = dev_id;
1292
1293	if (irq == dci->sb_irq) {
1294		regmap_write(dci->edac->ecc_mgr_map,
1295			     A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1296			     A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1297		edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1298
1299		return IRQ_HANDLED;
1300	} else if (irq == dci->db_irq) {
1301		regmap_write(dci->edac->ecc_mgr_map,
1302			     A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1303			     A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1304		edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1305		panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1306
1307		return IRQ_HANDLED;
1308	}
1309
1310	WARN_ON(1);
1311
1312	return IRQ_NONE;
1313}
1314
1315static const struct edac_device_prv_data l2ecc_data = {
1316	.setup = altr_l2_check_deps,
1317	.ce_clear_mask = 0,
1318	.ue_clear_mask = 0,
1319	.alloc_mem = l2_alloc_mem,
1320	.free_mem = l2_free_mem,
1321	.ecc_enable_mask = ALTR_L2_ECC_EN,
1322	.ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1323	.ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1324	.set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1325	.trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1326	.inject_fops = &altr_edac_device_inject_fops,
1327};
1328
1329static const struct edac_device_prv_data a10_l2ecc_data = {
1330	.setup = altr_l2_check_deps,
1331	.ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1332	.ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1333	.irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1334	.alloc_mem = l2_alloc_mem,
1335	.free_mem = l2_free_mem,
1336	.ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1337	.ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1338	.ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1339	.set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1340	.ecc_irq_handler = altr_edac_a10_l2_irq,
1341	.trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1342	.inject_fops = &altr_edac_device_inject_fops,
1343};
1344
1345#endif	/* CONFIG_EDAC_ALTERA_L2C */
1346
1347/********************* Ethernet Device Functions ********************/
1348
1349#ifdef CONFIG_EDAC_ALTERA_ETHERNET
1350
1351static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev)
1352{
1353	int ret;
1354
1355	ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1356	if (ret)
1357		return ret;
1358
1359	return altr_check_ecc_deps(dev);
1360}
1361
1362static const struct edac_device_prv_data a10_enetecc_data = {
1363	.setup = socfpga_init_ethernet_ecc,
1364	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1365	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1366	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1367	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1368	.ce_set_mask = ALTR_A10_ECC_TSERRA,
1369	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1370	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1371	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1372	.inject_fops = &altr_edac_a10_device_inject_fops,
1373};
1374
1375#endif	/* CONFIG_EDAC_ALTERA_ETHERNET */
1376
1377/********************** NAND Device Functions **********************/
1378
1379#ifdef CONFIG_EDAC_ALTERA_NAND
1380
1381static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device)
1382{
1383	int ret;
1384
1385	ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1386	if (ret)
1387		return ret;
1388
1389	return altr_check_ecc_deps(device);
1390}
1391
1392static const struct edac_device_prv_data a10_nandecc_data = {
1393	.setup = socfpga_init_nand_ecc,
1394	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1395	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1396	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1397	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1398	.ce_set_mask = ALTR_A10_ECC_TSERRA,
1399	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1400	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1401	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1402	.inject_fops = &altr_edac_a10_device_inject_fops,
1403};
1404
1405#endif	/* CONFIG_EDAC_ALTERA_NAND */
1406
1407/********************** DMA Device Functions **********************/
1408
1409#ifdef CONFIG_EDAC_ALTERA_DMA
1410
1411static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device)
1412{
1413	int ret;
1414
1415	ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1416	if (ret)
1417		return ret;
1418
1419	return altr_check_ecc_deps(device);
1420}
1421
1422static const struct edac_device_prv_data a10_dmaecc_data = {
1423	.setup = socfpga_init_dma_ecc,
1424	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1425	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1426	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1427	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1428	.ce_set_mask = ALTR_A10_ECC_TSERRA,
1429	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1430	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1431	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1432	.inject_fops = &altr_edac_a10_device_inject_fops,
1433};
1434
1435#endif	/* CONFIG_EDAC_ALTERA_DMA */
1436
1437/********************** USB Device Functions **********************/
1438
1439#ifdef CONFIG_EDAC_ALTERA_USB
1440
1441static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device)
1442{
1443	int ret;
1444
1445	ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1446	if (ret)
1447		return ret;
1448
1449	return altr_check_ecc_deps(device);
1450}
1451
1452static const struct edac_device_prv_data a10_usbecc_data = {
1453	.setup = socfpga_init_usb_ecc,
1454	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1455	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1456	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1457	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1458	.ce_set_mask = ALTR_A10_ECC_TSERRA,
1459	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1460	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1461	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1462	.inject_fops = &altr_edac_a10_device_inject_fops,
1463};
1464
1465#endif	/* CONFIG_EDAC_ALTERA_USB */
1466
1467/********************** QSPI Device Functions **********************/
1468
1469#ifdef CONFIG_EDAC_ALTERA_QSPI
1470
1471static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device)
1472{
1473	int ret;
1474
1475	ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1476	if (ret)
1477		return ret;
1478
1479	return altr_check_ecc_deps(device);
1480}
1481
1482static const struct edac_device_prv_data a10_qspiecc_data = {
1483	.setup = socfpga_init_qspi_ecc,
1484	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1485	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1486	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1487	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1488	.ce_set_mask = ALTR_A10_ECC_TSERRA,
1489	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1490	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1491	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1492	.inject_fops = &altr_edac_a10_device_inject_fops,
1493};
1494
1495#endif	/* CONFIG_EDAC_ALTERA_QSPI */
1496
1497/********************* SDMMC Device Functions **********************/
1498
1499#ifdef CONFIG_EDAC_ALTERA_SDMMC
1500
1501static const struct edac_device_prv_data a10_sdmmceccb_data;
1502static int altr_portb_setup(struct altr_edac_device_dev *device)
1503{
1504	struct edac_device_ctl_info *dci;
1505	struct altr_edac_device_dev *altdev;
1506	char *ecc_name = "sdmmcb-ecc";
1507	int edac_idx, rc;
1508	struct device_node *np;
1509	const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1510
1511	rc = altr_check_ecc_deps(device);
1512	if (rc)
1513		return rc;
1514
1515	np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1516	if (!np) {
1517		edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1518		return -ENODEV;
1519	}
1520
1521	/* Create the PortB EDAC device */
1522	edac_idx = edac_device_alloc_index();
1523	dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1524					 ecc_name, 1, 0, edac_idx);
1525	if (!dci) {
1526		edac_printk(KERN_ERR, EDAC_DEVICE,
1527			    "%s: Unable to allocate PortB EDAC device\n",
1528			    ecc_name);
1529		return -ENOMEM;
1530	}
1531
1532	/* Initialize the PortB EDAC device structure from PortA structure */
1533	altdev = dci->pvt_info;
1534	*altdev = *device;
1535
1536	if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1537		return -ENOMEM;
1538
1539	/* Update PortB specific values */
1540	altdev->edac_dev_name = ecc_name;
1541	altdev->edac_idx = edac_idx;
1542	altdev->edac_dev = dci;
1543	altdev->data = prv;
1544	dci->dev = &altdev->ddev;
1545	dci->ctl_name = "Altera ECC Manager";
1546	dci->mod_name = ecc_name;
1547	dci->dev_name = ecc_name;
1548
1549	/*
1550	 * Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly
1551	 *
1552	 * FIXME: Instead of ifdefs with different architectures the driver
1553	 *        should properly use compatibles.
1554	 */
1555#ifdef CONFIG_64BIT
1556	altdev->sb_irq = irq_of_parse_and_map(np, 1);
1557#else
1558	altdev->sb_irq = irq_of_parse_and_map(np, 2);
1559#endif
1560	if (!altdev->sb_irq) {
1561		edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1562		rc = -ENODEV;
1563		goto err_release_group_1;
1564	}
1565	rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1566			      prv->ecc_irq_handler, IRQF_TRIGGER_HIGH,
1567			      ecc_name, altdev);
1568	if (rc) {
1569		edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1570		goto err_release_group_1;
1571	}
1572
1573#ifdef CONFIG_64BIT
1574	/* Use IRQ to determine SError origin instead of assigning IRQ */
1575	rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);
1576	if (rc) {
1577		edac_printk(KERN_ERR, EDAC_DEVICE,
1578			    "Error PortB DBIRQ alloc\n");
1579		goto err_release_group_1;
1580	}
1581#else
1582	altdev->db_irq = irq_of_parse_and_map(np, 3);
1583	if (!altdev->db_irq) {
1584		edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1585		rc = -ENODEV;
1586		goto err_release_group_1;
1587	}
1588	rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1589			      prv->ecc_irq_handler, IRQF_TRIGGER_HIGH,
1590			      ecc_name, altdev);
1591	if (rc) {
1592		edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1593		goto err_release_group_1;
1594	}
1595#endif
1596
1597	rc = edac_device_add_device(dci);
1598	if (rc) {
1599		edac_printk(KERN_ERR, EDAC_DEVICE,
1600			    "edac_device_add_device portB failed\n");
1601		rc = -ENOMEM;
1602		goto err_release_group_1;
1603	}
1604	altr_create_edacdev_dbgfs(dci, prv);
1605
1606	list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1607
1608	devres_remove_group(&altdev->ddev, altr_portb_setup);
1609
1610	return 0;
1611
1612err_release_group_1:
1613	edac_device_free_ctl_info(dci);
1614	devres_release_group(&altdev->ddev, altr_portb_setup);
1615	edac_printk(KERN_ERR, EDAC_DEVICE,
1616		    "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1617	return rc;
1618}
1619
1620static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device)
1621{
1622	int rc = -ENODEV;
1623	struct device_node *child;
1624
1625	child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1626	if (!child)
1627		return -ENODEV;
1628
1629	if (!of_device_is_available(child))
1630		goto exit;
1631
1632	if (validate_parent_available(child))
1633		goto exit;
1634
1635	/* Init portB */
1636	rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1637				     a10_sdmmceccb_data.ecc_enable_mask, 1);
1638	if (rc)
1639		goto exit;
1640
1641	/* Setup portB */
1642	return altr_portb_setup(device);
1643
1644exit:
1645	of_node_put(child);
1646	return rc;
1647}
1648
1649static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1650{
1651	struct altr_edac_device_dev *ad = dev_id;
1652	void __iomem  *base = ad->base;
1653	const struct edac_device_prv_data *priv = ad->data;
1654
1655	if (irq == ad->sb_irq) {
1656		writel(priv->ce_clear_mask,
1657		       base + ALTR_A10_ECC_INTSTAT_OFST);
1658		edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1659		return IRQ_HANDLED;
1660	} else if (irq == ad->db_irq) {
1661		writel(priv->ue_clear_mask,
1662		       base + ALTR_A10_ECC_INTSTAT_OFST);
1663		edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1664		return IRQ_HANDLED;
1665	}
1666
1667	WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1668
1669	return IRQ_NONE;
1670}
1671
1672static const struct edac_device_prv_data a10_sdmmcecca_data = {
1673	.setup = socfpga_init_sdmmc_ecc,
1674	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1675	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1676	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1677	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1678	.ce_set_mask = ALTR_A10_ECC_SERRPENA,
1679	.ue_set_mask = ALTR_A10_ECC_DERRPENA,
1680	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1681	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1682	.inject_fops = &altr_edac_a10_device_inject_fops,
1683};
1684
1685static const struct edac_device_prv_data a10_sdmmceccb_data = {
1686	.setup = socfpga_init_sdmmc_ecc,
1687	.ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1688	.ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1689	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1690	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1691	.ce_set_mask = ALTR_A10_ECC_TSERRB,
1692	.ue_set_mask = ALTR_A10_ECC_TDERRB,
1693	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1694	.ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1695	.inject_fops = &altr_edac_a10_device_inject_fops,
1696};
1697
1698#endif	/* CONFIG_EDAC_ALTERA_SDMMC */
1699
1700/********************* Arria10 EDAC Device Functions *************************/
1701static const struct of_device_id altr_edac_a10_device_of_match[] = {
1702#ifdef CONFIG_EDAC_ALTERA_L2C
1703	{ .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1704#endif
1705#ifdef CONFIG_EDAC_ALTERA_OCRAM
1706	{ .compatible = "altr,socfpga-a10-ocram-ecc",
1707	  .data = &a10_ocramecc_data },
1708#endif
1709#ifdef CONFIG_EDAC_ALTERA_ETHERNET
1710	{ .compatible = "altr,socfpga-eth-mac-ecc",
1711	  .data = &a10_enetecc_data },
1712#endif
1713#ifdef CONFIG_EDAC_ALTERA_NAND
1714	{ .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1715#endif
1716#ifdef CONFIG_EDAC_ALTERA_DMA
1717	{ .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1718#endif
1719#ifdef CONFIG_EDAC_ALTERA_USB
1720	{ .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1721#endif
1722#ifdef CONFIG_EDAC_ALTERA_QSPI
1723	{ .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1724#endif
1725#ifdef CONFIG_EDAC_ALTERA_SDMMC
1726	{ .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1727#endif
1728#ifdef CONFIG_EDAC_ALTERA_SDRAM
1729	{ .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },
1730#endif
1731	{},
1732};
1733MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1734
1735/*
1736 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1737 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1738 * manager manages the IRQs and the children.
1739 * Based on xgene_edac.c peripheral code.
1740 */
1741
1742static ssize_t __maybe_unused
1743altr_edac_a10_device_trig(struct file *file, const char __user *user_buf,
1744			  size_t count, loff_t *ppos)
1745{
1746	struct edac_device_ctl_info *edac_dci = file->private_data;
1747	struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1748	const struct edac_device_prv_data *priv = drvdata->data;
1749	void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1750	unsigned long flags;
1751	u8 trig_type;
1752
1753	if (!user_buf || get_user(trig_type, user_buf))
1754		return -EFAULT;
1755
1756	local_irq_save(flags);
1757	if (trig_type == ALTR_UE_TRIGGER_CHAR)
1758		writew(priv->ue_set_mask, set_addr);
1759	else
1760		writew(priv->ce_set_mask, set_addr);
1761
1762	/* Ensure the interrupt test bits are set */
1763	wmb();
1764	local_irq_restore(flags);
1765
1766	return count;
1767}
1768
1769/*
1770 * The Stratix10 EDAC Error Injection Functions differ from Arria10
1771 * slightly. A few Arria10 peripherals can use this injection function.
1772 * Inject the error into the memory and then readback to trigger the IRQ.
1773 */
1774static ssize_t __maybe_unused
1775altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf,
1776			   size_t count, loff_t *ppos)
1777{
1778	struct edac_device_ctl_info *edac_dci = file->private_data;
1779	struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1780	const struct edac_device_prv_data *priv = drvdata->data;
1781	void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1782	unsigned long flags;
1783	u8 trig_type;
1784
1785	if (!user_buf || get_user(trig_type, user_buf))
1786		return -EFAULT;
1787
1788	local_irq_save(flags);
1789	if (trig_type == ALTR_UE_TRIGGER_CHAR) {
1790		writew(priv->ue_set_mask, set_addr);
1791	} else {
1792		/* Setup read/write of 4 bytes */
1793		writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
1794		/* Setup Address to 0 */
1795		writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
1796		/* Setup accctrl to read & ecc & data override */
1797		writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1798		/* Kick it. */
1799		writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1800		/* Setup write for single bit change */
1801		writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
1802		       drvdata->base + ECC_BLK_WDATA0_OFST);
1803		writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
1804		       drvdata->base + ECC_BLK_WDATA1_OFST);
1805		writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
1806		       drvdata->base + ECC_BLK_WDATA2_OFST);
1807		writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
1808		       drvdata->base + ECC_BLK_WDATA3_OFST);
1809
1810		/* Copy Read ECC to Write ECC */
1811		writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
1812		       drvdata->base + ECC_BLK_WECC0_OFST);
1813		writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
1814		       drvdata->base + ECC_BLK_WECC1_OFST);
1815		/* Setup accctrl to write & ecc override & data override */
1816		writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1817		/* Kick it. */
1818		writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1819		/* Setup accctrl to read & ecc overwrite & data overwrite */
1820		writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1821		/* Kick it. */
1822		writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1823	}
1824
1825	/* Ensure the interrupt test bits are set */
1826	wmb();
1827	local_irq_restore(flags);
1828
1829	return count;
1830}
1831
1832static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1833{
1834	int dberr, bit, sm_offset, irq_status;
1835	struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1836	struct irq_chip *chip = irq_desc_get_chip(desc);
1837	int irq = irq_desc_get_irq(desc);
1838	unsigned long bits;
1839
1840	dberr = (irq == edac->db_irq) ? 1 : 0;
1841	sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1842			    A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1843
1844	chained_irq_enter(chip, desc);
1845
1846	regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1847
1848	bits = irq_status;
1849	for_each_set_bit(bit, &bits, 32)
1850		generic_handle_domain_irq(edac->domain, dberr * 32 + bit);
1851
1852	chained_irq_exit(chip, desc);
1853}
1854
1855static int validate_parent_available(struct device_node *np)
1856{
1857	struct device_node *parent;
1858	int ret = 0;
1859
1860	/* SDRAM must be present for Linux (implied parent) */
1861	if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1862		return 0;
1863
1864	/* Ensure parent device is enabled if parent node exists */
1865	parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1866	if (parent && !of_device_is_available(parent))
1867		ret = -ENODEV;
1868
1869	of_node_put(parent);
1870	return ret;
1871}
1872
1873static int get_s10_sdram_edac_resource(struct device_node *np,
1874				       struct resource *res)
1875{
1876	struct device_node *parent;
1877	int ret;
1878
1879	parent = of_parse_phandle(np, "altr,sdr-syscon", 0);
1880	if (!parent)
1881		return -ENODEV;
1882
1883	ret = of_address_to_resource(parent, 0, res);
1884	of_node_put(parent);
1885
1886	return ret;
1887}
1888
1889static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1890				    struct device_node *np)
1891{
1892	struct edac_device_ctl_info *dci;
1893	struct altr_edac_device_dev *altdev;
1894	char *ecc_name = (char *)np->name;
1895	struct resource res;
1896	int edac_idx;
1897	int rc = 0;
1898	const struct edac_device_prv_data *prv;
1899	/* Get matching node and check for valid result */
1900	const struct of_device_id *pdev_id =
1901		of_match_node(altr_edac_a10_device_of_match, np);
1902	if (IS_ERR_OR_NULL(pdev_id))
1903		return -ENODEV;
1904
1905	/* Get driver specific data for this EDAC device */
1906	prv = pdev_id->data;
1907	if (IS_ERR_OR_NULL(prv))
1908		return -ENODEV;
1909
1910	if (validate_parent_available(np))
1911		return -ENODEV;
1912
1913	if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1914		return -ENOMEM;
1915
1916	if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1917		rc = get_s10_sdram_edac_resource(np, &res);
1918	else
1919		rc = of_address_to_resource(np, 0, &res);
1920
1921	if (rc < 0) {
1922		edac_printk(KERN_ERR, EDAC_DEVICE,
1923			    "%s: no resource address\n", ecc_name);
1924		goto err_release_group;
1925	}
1926
1927	edac_idx = edac_device_alloc_index();
1928	dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1929					 1, ecc_name, 1, 0, edac_idx);
1930
1931	if (!dci) {
1932		edac_printk(KERN_ERR, EDAC_DEVICE,
1933			    "%s: Unable to allocate EDAC device\n", ecc_name);
1934		rc = -ENOMEM;
1935		goto err_release_group;
1936	}
1937
1938	altdev = dci->pvt_info;
1939	dci->dev = edac->dev;
1940	altdev->edac_dev_name = ecc_name;
1941	altdev->edac_idx = edac_idx;
1942	altdev->edac = edac;
1943	altdev->edac_dev = dci;
1944	altdev->data = prv;
1945	altdev->ddev = *edac->dev;
1946	dci->dev = &altdev->ddev;
1947	dci->ctl_name = "Altera ECC Manager";
1948	dci->mod_name = ecc_name;
1949	dci->dev_name = ecc_name;
1950
1951	altdev->base = devm_ioremap_resource(edac->dev, &res);
1952	if (IS_ERR(altdev->base)) {
1953		rc = PTR_ERR(altdev->base);
1954		goto err_release_group1;
1955	}
1956
1957	/* Check specific dependencies for the module */
1958	if (altdev->data->setup) {
1959		rc = altdev->data->setup(altdev);
1960		if (rc)
1961			goto err_release_group1;
1962	}
1963
1964	altdev->sb_irq = irq_of_parse_and_map(np, 0);
1965	if (!altdev->sb_irq) {
1966		edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
1967		rc = -ENODEV;
1968		goto err_release_group1;
1969	}
1970	rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
1971			      IRQF_TRIGGER_HIGH, ecc_name, altdev);
1972	if (rc) {
1973		edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
1974		goto err_release_group1;
1975	}
1976
1977#ifdef CONFIG_64BIT
1978	/* Use IRQ to determine SError origin instead of assigning IRQ */
1979	rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
1980	if (rc) {
1981		edac_printk(KERN_ERR, EDAC_DEVICE,
1982			    "Unable to parse DB IRQ index\n");
1983		goto err_release_group1;
1984	}
1985#else
1986	altdev->db_irq = irq_of_parse_and_map(np, 1);
1987	if (!altdev->db_irq) {
1988		edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
1989		rc = -ENODEV;
1990		goto err_release_group1;
1991	}
1992	rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
1993			      IRQF_TRIGGER_HIGH,
1994			      ecc_name, altdev);
1995	if (rc) {
1996		edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1997		goto err_release_group1;
1998	}
1999#endif
2000
2001	rc = edac_device_add_device(dci);
2002	if (rc) {
2003		dev_err(edac->dev, "edac_device_add_device failed\n");
2004		rc = -ENOMEM;
2005		goto err_release_group1;
2006	}
2007
2008	altr_create_edacdev_dbgfs(dci, prv);
2009
2010	list_add(&altdev->next, &edac->a10_ecc_devices);
2011
2012	devres_remove_group(edac->dev, altr_edac_a10_device_add);
2013
2014	return 0;
2015
2016err_release_group1:
2017	edac_device_free_ctl_info(dci);
2018err_release_group:
2019	devres_release_group(edac->dev, NULL);
2020	edac_printk(KERN_ERR, EDAC_DEVICE,
2021		    "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
2022
2023	return rc;
2024}
2025
2026static void a10_eccmgr_irq_mask(struct irq_data *d)
2027{
2028	struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2029
2030	regmap_write(edac->ecc_mgr_map,	A10_SYSMGR_ECC_INTMASK_SET_OFST,
2031		     BIT(d->hwirq));
2032}
2033
2034static void a10_eccmgr_irq_unmask(struct irq_data *d)
2035{
2036	struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2037
2038	regmap_write(edac->ecc_mgr_map,	A10_SYSMGR_ECC_INTMASK_CLR_OFST,
2039		     BIT(d->hwirq));
2040}
2041
2042static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2043				    irq_hw_number_t hwirq)
2044{
2045	struct altr_arria10_edac *edac = d->host_data;
2046
2047	irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2048	irq_set_chip_data(irq, edac);
2049	irq_set_noprobe(irq);
2050
2051	return 0;
2052}
2053
2054static const struct irq_domain_ops a10_eccmgr_ic_ops = {
2055	.map = a10_eccmgr_irqdomain_map,
2056	.xlate = irq_domain_xlate_twocell,
2057};
2058
2059/************** Stratix 10 EDAC Double Bit Error Handler ************/
2060#define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2061
2062#ifdef CONFIG_64BIT
2063/* panic routine issues reboot on non-zero panic_timeout */
2064extern int panic_timeout;
2065
2066/*
2067 * The double bit error is handled through SError which is fatal. This is
2068 * called as a panic notifier to printout ECC error info as part of the panic.
2069 */
2070static int s10_edac_dberr_handler(struct notifier_block *this,
2071				  unsigned long event, void *ptr)
2072{
2073	struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
2074	int err_addr, dberror;
2075
2076	regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2077		    &dberror);
2078	regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
2079	if (dberror & S10_DBE_IRQ_MASK) {
2080		struct list_head *position;
2081		struct altr_edac_device_dev *ed;
2082		struct arm_smccc_res result;
2083
2084		/* Find the matching DBE in the list of devices */
2085		list_for_each(position, &edac->a10_ecc_devices) {
2086			ed = list_entry(position, struct altr_edac_device_dev,
2087					next);
2088			if (!(BIT(ed->db_irq) & dberror))
2089				continue;
2090
2091			writel(ALTR_A10_ECC_DERRPENA,
2092			       ed->base + ALTR_A10_ECC_INTSTAT_OFST);
2093			err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST);
2094			regmap_write(edac->ecc_mgr_map,
2095				     S10_SYSMGR_UE_ADDR_OFST, err_addr);
2096			edac_printk(KERN_ERR, EDAC_DEVICE,
2097				    "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
2098				    ed->edac_dev_name, err_addr);
2099			break;
2100		}
2101		/* Notify the System through SMC. Reboot delay = 1 second */
2102		panic_timeout = 1;
2103		arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0,
2104			      0, 0, &result);
2105	}
2106
2107	return NOTIFY_DONE;
2108}
2109#endif
2110
2111/****************** Arria 10 EDAC Probe Function *********************/
2112static int altr_edac_a10_probe(struct platform_device *pdev)
2113{
2114	struct altr_arria10_edac *edac;
2115	struct device_node *child;
2116
2117	edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2118	if (!edac)
2119		return -ENOMEM;
2120
2121	edac->dev = &pdev->dev;
2122	platform_set_drvdata(pdev, edac);
2123	INIT_LIST_HEAD(&edac->a10_ecc_devices);
2124
2125	edac->ecc_mgr_map =
2126		altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node,
2127						     "altr,sysmgr-syscon");
2128
2129	if (IS_ERR(edac->ecc_mgr_map)) {
2130		edac_printk(KERN_ERR, EDAC_DEVICE,
2131			    "Unable to get syscon altr,sysmgr-syscon\n");
2132		return PTR_ERR(edac->ecc_mgr_map);
2133	}
2134
2135	/* Set irq mask for DDR SBE to avoid any pending irq before registration */
2136	regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
2137		     (A10_SYSMGR_ECC_INTMASK_SDMMCB | A10_SYSMGR_ECC_INTMASK_DDR0));
2138
2139	edac->irq_chip.name = pdev->dev.of_node->name;
2140	edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2141	edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2142	edac->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), 64, &a10_eccmgr_ic_ops,
2143						edac);
2144	if (!edac->domain) {
2145		dev_err(&pdev->dev, "Error adding IRQ domain\n");
2146		return -ENOMEM;
2147	}
2148
2149	edac->sb_irq = platform_get_irq(pdev, 0);
2150	if (edac->sb_irq < 0)
2151		return edac->sb_irq;
2152
2153	irq_set_chained_handler_and_data(edac->sb_irq,
2154					 altr_edac_a10_irq_handler,
2155					 edac);
2156
2157#ifdef CONFIG_64BIT
2158	{
2159		int dberror, err_addr;
2160
2161		edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2162		atomic_notifier_chain_register(&panic_notifier_list,
2163					       &edac->panic_notifier);
2164
2165		/* Printout a message if uncorrectable error previously. */
2166		regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
2167			    &dberror);
2168		if (dberror) {
2169			regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2170				    &err_addr);
2171			edac_printk(KERN_ERR, EDAC_DEVICE,
2172				    "Previous Boot UE detected[0x%X] @ 0x%X\n",
2173				    dberror, err_addr);
2174			/* Reset the sticky registers */
2175			regmap_write(edac->ecc_mgr_map,
2176				     S10_SYSMGR_UE_VAL_OFST, 0);
2177			regmap_write(edac->ecc_mgr_map,
2178				     S10_SYSMGR_UE_ADDR_OFST, 0);
2179		}
2180	}
2181#else
2182	edac->db_irq = platform_get_irq(pdev, 1);
2183	if (edac->db_irq < 0)
2184		return edac->db_irq;
2185
2186	irq_set_chained_handler_and_data(edac->db_irq,
2187					 altr_edac_a10_irq_handler, edac);
2188#endif
2189
2190	for_each_child_of_node(pdev->dev.of_node, child) {
2191		if (!of_device_is_available(child))
2192			continue;
2193
2194		if (of_match_node(altr_edac_a10_device_of_match, child))
2195			altr_edac_a10_device_add(edac, child);
2196
2197#ifdef CONFIG_EDAC_ALTERA_SDRAM
2198		else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
2199			of_platform_populate(pdev->dev.of_node,
2200					     altr_sdram_ctrl_of_match,
2201					     NULL, &pdev->dev);
2202#endif
2203	}
2204
2205	return 0;
2206}
2207
2208static const struct of_device_id altr_edac_a10_of_match[] = {
2209	{ .compatible = "altr,socfpga-a10-ecc-manager" },
2210	{ .compatible = "altr,socfpga-s10-ecc-manager" },
2211	{},
2212};
2213MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2214
2215static struct platform_driver altr_edac_a10_driver = {
2216	.probe =  altr_edac_a10_probe,
2217	.driver = {
2218		.name = "socfpga_a10_ecc_manager",
2219		.of_match_table = altr_edac_a10_of_match,
2220	},
2221};
2222module_platform_driver(altr_edac_a10_driver);
2223
2224MODULE_AUTHOR("Thor Thayer");
2225MODULE_DESCRIPTION("EDAC Driver for Altera Memories");