regs.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2
  3#ifndef _ZL3073X_REGS_H
  4#define _ZL3073X_REGS_H
  5
  6#include <linux/bitfield.h>
  7#include <linux/bits.h>
  8
  9/*
 10 * Register address structure:
 11 * ===========================
 12 *  25        19 18  16 15     7 6           0
 13 * +------------------------------------------+
 14 * | max_offset | size |  page  | page_offset |
 15 * +------------------------------------------+
 16 *
 17 * page_offset ... <0x00..0x7F>
 18 * page .......... HW page number
 19 * size .......... register byte size (1, 2, 4 or 6)
 20 * max_offset .... maximal offset for indexed registers
 21 *                 (for non-indexed regs max_offset == page_offset)
 22 */
 23
 24#define ZL_REG_OFFSET_MASK	GENMASK(6, 0)
 25#define ZL_REG_PAGE_MASK	GENMASK(15, 7)
 26#define ZL_REG_SIZE_MASK	GENMASK(18, 16)
 27#define ZL_REG_MAX_OFFSET_MASK	GENMASK(25, 19)
 28#define ZL_REG_ADDR_MASK	GENMASK(15, 0)
 29
 30#define ZL_REG_OFFSET(_reg)	FIELD_GET(ZL_REG_OFFSET_MASK, _reg)
 31#define ZL_REG_PAGE(_reg)	FIELD_GET(ZL_REG_PAGE_MASK, _reg)
 32#define ZL_REG_MAX_OFFSET(_reg)	FIELD_GET(ZL_REG_MAX_OFFSET_MASK, _reg)
 33#define ZL_REG_SIZE(_reg)	FIELD_GET(ZL_REG_SIZE_MASK, _reg)
 34#define ZL_REG_ADDR(_reg)	FIELD_GET(ZL_REG_ADDR_MASK, _reg)
 35
 36/**
 37 * ZL_REG_IDX - define indexed register
 38 * @_idx: index of register to access
 39 * @_page: register page
 40 * @_offset: register offset in page
 41 * @_size: register byte size (1, 2, 4 or 6)
 42 * @_items: number of register indices
 43 * @_stride: stride between items in bytes
 44 *
 45 * All parameters except @_idx should be constant.
 46 */
 47#define ZL_REG_IDX(_idx, _page, _offset, _size, _items, _stride)	\
 48	(FIELD_PREP(ZL_REG_OFFSET_MASK,					\
 49		    (_offset) + (_idx) * (_stride))		|	\
 50	 FIELD_PREP_CONST(ZL_REG_PAGE_MASK, _page)		|	\
 51	 FIELD_PREP_CONST(ZL_REG_SIZE_MASK, _size)		|	\
 52	 FIELD_PREP_CONST(ZL_REG_MAX_OFFSET_MASK,			\
 53			  (_offset) + ((_items) - 1) * (_stride)))
 54
 55/**
 56 * ZL_REG - define simple (non-indexed) register
 57 * @_page: register page
 58 * @_offset: register offset in page
 59 * @_size: register byte size (1, 2, 4 or 6)
 60 *
 61 * All parameters should be constant.
 62 */
 63#define ZL_REG(_page, _offset, _size)					\
 64	ZL_REG_IDX(0, _page, _offset, _size, 1, 0)
 65
 66/**************************
 67 * Register Page 0, General
 68 **************************/
 69
 70#define ZL_REG_INFO				ZL_REG(0, 0x00, 1)
 71#define ZL_INFO_READY				BIT(7)
 72
 73#define ZL_REG_ID				ZL_REG(0, 0x01, 2)
 74#define ZL_REG_REVISION				ZL_REG(0, 0x03, 2)
 75#define ZL_REG_FW_VER				ZL_REG(0, 0x05, 2)
 76#define ZL_REG_CUSTOM_CONFIG_VER		ZL_REG(0, 0x07, 4)
 77
 78#define ZL_REG_RESET_STATUS			ZL_REG(0, 0x18, 1)
 79#define ZL_REG_RESET_STATUS_RESET		BIT(0)
 80
 81/*************************
 82 * Register Page 2, Status
 83 *************************/
 84
 85#define ZL_REG_REF_MON_STATUS(_idx)					\
 86	ZL_REG_IDX(_idx, 2, 0x02, 1, ZL3073X_NUM_REFS, 1)
 87#define ZL_REF_MON_STATUS_OK			0 /* all bits zeroed */
 88
 89#define ZL_REG_DPLL_MON_STATUS(_idx)					\
 90	ZL_REG_IDX(_idx, 2, 0x10, 1, ZL3073X_MAX_CHANNELS, 1)
 91#define ZL_DPLL_MON_STATUS_STATE		GENMASK(1, 0)
 92#define ZL_DPLL_MON_STATUS_STATE_ACQUIRING	0
 93#define ZL_DPLL_MON_STATUS_STATE_LOCK		1
 94#define ZL_DPLL_MON_STATUS_STATE_HOLDOVER	2
 95#define ZL_DPLL_MON_STATUS_HO_READY		BIT(2)
 96
 97#define ZL_REG_DPLL_REFSEL_STATUS(_idx)					\
 98	ZL_REG_IDX(_idx, 2, 0x30, 1, ZL3073X_MAX_CHANNELS, 1)
 99#define ZL_DPLL_REFSEL_STATUS_REFSEL		GENMASK(3, 0)
100#define ZL_DPLL_REFSEL_STATUS_STATE		GENMASK(6, 4)
101#define ZL_DPLL_REFSEL_STATUS_STATE_LOCK	4
102
103#define ZL_REG_REF_FREQ(_idx)						\
104	ZL_REG_IDX(_idx, 2, 0x44, 4, ZL3073X_NUM_REFS, 4)
105
106/**********************
107 * Register Page 4, Ref
108 **********************/
109
110#define ZL_REG_REF_PHASE_ERR_READ_RQST		ZL_REG(4, 0x0f, 1)
111#define ZL_REF_PHASE_ERR_READ_RQST_RD		BIT(0)
112
113#define ZL_REG_REF_FREQ_MEAS_CTRL		ZL_REG(4, 0x1c, 1)
114#define ZL_REF_FREQ_MEAS_CTRL			GENMASK(1, 0)
115#define ZL_REF_FREQ_MEAS_CTRL_REF_FREQ		1
116#define ZL_REF_FREQ_MEAS_CTRL_REF_FREQ_OFF	2
117#define ZL_REF_FREQ_MEAS_CTRL_DPLL_FREQ_OFF	3
118
119#define ZL_REG_REF_FREQ_MEAS_MASK_3_0		ZL_REG(4, 0x1d, 1)
120#define ZL_REF_FREQ_MEAS_MASK_3_0(_ref)		BIT(_ref)
121
122#define ZL_REG_REF_FREQ_MEAS_MASK_4		ZL_REG(4, 0x1e, 1)
123#define ZL_REF_FREQ_MEAS_MASK_4(_ref)		BIT((_ref) - 8)
124
125#define ZL_REG_DPLL_MEAS_REF_FREQ_CTRL		ZL_REG(4, 0x1f, 1)
126#define ZL_DPLL_MEAS_REF_FREQ_CTRL_EN		BIT(0)
127#define ZL_DPLL_MEAS_REF_FREQ_CTRL_IDX		GENMASK(6, 4)
128
129#define ZL_REG_REF_PHASE(_idx)						\
130	ZL_REG_IDX(_idx, 4, 0x20, 6, ZL3073X_NUM_REFS, 6)
131
132/***********************
133 * Register Page 5, DPLL
134 ***********************/
135
136#define ZL_REG_DPLL_MODE_REFSEL(_idx)					\
137	ZL_REG_IDX(_idx, 5, 0x04, 1, ZL3073X_MAX_CHANNELS, 4)
138#define ZL_DPLL_MODE_REFSEL_MODE		GENMASK(2, 0)
139#define ZL_DPLL_MODE_REFSEL_MODE_FREERUN	0
140#define ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER	1
141#define ZL_DPLL_MODE_REFSEL_MODE_REFLOCK	2
142#define ZL_DPLL_MODE_REFSEL_MODE_AUTO		3
143#define ZL_DPLL_MODE_REFSEL_MODE_NCO		4
144#define ZL_DPLL_MODE_REFSEL_REF			GENMASK(7, 4)
145
146#define ZL_REG_DPLL_MEAS_CTRL			ZL_REG(5, 0x50, 1)
147#define ZL_DPLL_MEAS_CTRL_EN			BIT(0)
148#define ZL_DPLL_MEAS_CTRL_AVG_FACTOR		GENMASK(7, 4)
149
150#define ZL_REG_DPLL_MEAS_IDX			ZL_REG(5, 0x51, 1)
151#define ZL_DPLL_MEAS_IDX			GENMASK(2, 0)
152
153#define ZL_REG_DPLL_PHASE_ERR_READ_MASK		ZL_REG(5, 0x54, 1)
154
155#define ZL_REG_DPLL_PHASE_ERR_DATA(_idx)				\
156	ZL_REG_IDX(_idx, 5, 0x55, 6, ZL3073X_MAX_CHANNELS, 6)
157
158/***********************************
159 * Register Page 9, Synth and Output
160 ***********************************/
161
162#define ZL_REG_SYNTH_CTRL(_idx)						\
163	ZL_REG_IDX(_idx, 9, 0x00, 1, ZL3073X_NUM_SYNTHS, 1)
164#define ZL_SYNTH_CTRL_EN			BIT(0)
165#define ZL_SYNTH_CTRL_DPLL_SEL			GENMASK(6, 4)
166
167#define ZL_REG_SYNTH_PHASE_SHIFT_CTRL		ZL_REG(9, 0x1e, 1)
168#define ZL_REG_SYNTH_PHASE_SHIFT_MASK		ZL_REG(9, 0x1f, 1)
169#define ZL_REG_SYNTH_PHASE_SHIFT_INTVL		ZL_REG(9, 0x20, 1)
170#define ZL_REG_SYNTH_PHASE_SHIFT_DATA		ZL_REG(9, 0x21, 2)
171
172#define ZL_REG_OUTPUT_CTRL(_idx)					\
173	ZL_REG_IDX(_idx, 9, 0x28, 1, ZL3073X_NUM_OUTS, 1)
174#define ZL_OUTPUT_CTRL_EN			BIT(0)
175#define ZL_OUTPUT_CTRL_SYNTH_SEL		GENMASK(6, 4)
176
177/*******************************
178 * Register Page 10, Ref Mailbox
179 *******************************/
180
181#define ZL_REG_REF_MB_MASK			ZL_REG(10, 0x02, 2)
182
183#define ZL_REG_REF_MB_SEM			ZL_REG(10, 0x04, 1)
184#define ZL_REF_MB_SEM_WR			BIT(0)
185#define ZL_REF_MB_SEM_RD			BIT(1)
186
187#define ZL_REG_REF_FREQ_BASE			ZL_REG(10, 0x05, 2)
188#define ZL_REG_REF_FREQ_MULT			ZL_REG(10, 0x07, 2)
189#define ZL_REG_REF_RATIO_M			ZL_REG(10, 0x09, 2)
190#define ZL_REG_REF_RATIO_N			ZL_REG(10, 0x0b, 2)
191
192#define ZL_REG_REF_CONFIG			ZL_REG(10, 0x0d, 1)
193#define ZL_REF_CONFIG_ENABLE			BIT(0)
194#define ZL_REF_CONFIG_DIFF_EN			BIT(2)
195
196#define ZL_REG_REF_PHASE_OFFSET_COMP		ZL_REG(10, 0x28, 6)
197#define ZL_REG_REF_PHASE_OFFSET_COMP_32	ZL_REG(10, 0x28, 4)
198
199#define ZL_REG_REF_SYNC_CTRL			ZL_REG(10, 0x2e, 1)
200#define ZL_REF_SYNC_CTRL_MODE			GENMASK(2, 0)
201#define ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF	0
202#define ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75	2
203
204#define ZL_REG_REF_ESYNC_DIV			ZL_REG(10, 0x30, 4)
205#define ZL_REF_ESYNC_DIV_1HZ			0
206
207/********************************
208 * Register Page 12, DPLL Mailbox
209 ********************************/
210
211#define ZL_REG_DPLL_MB_MASK			ZL_REG(12, 0x02, 2)
212
213#define ZL_REG_DPLL_MB_SEM			ZL_REG(12, 0x04, 1)
214#define ZL_DPLL_MB_SEM_WR			BIT(0)
215#define ZL_DPLL_MB_SEM_RD			BIT(1)
216
217#define ZL_REG_DPLL_REF_PRIO(_idx)					\
218	ZL_REG_IDX(_idx, 12, 0x52, 1, ZL3073X_NUM_REFS / 2, 1)
219#define ZL_DPLL_REF_PRIO_REF_P			GENMASK(3, 0)
220#define ZL_DPLL_REF_PRIO_REF_N			GENMASK(7, 4)
221#define ZL_DPLL_REF_PRIO_MAX			14
222#define ZL_DPLL_REF_PRIO_NONE			15
223
224/*********************************
225 * Register Page 13, Synth Mailbox
226 *********************************/
227
228#define ZL_REG_SYNTH_MB_MASK			ZL_REG(13, 0x02, 2)
229
230#define ZL_REG_SYNTH_MB_SEM			ZL_REG(13, 0x04, 1)
231#define ZL_SYNTH_MB_SEM_WR			BIT(0)
232#define ZL_SYNTH_MB_SEM_RD			BIT(1)
233
234#define ZL_REG_SYNTH_FREQ_BASE			ZL_REG(13, 0x06, 2)
235#define ZL_REG_SYNTH_FREQ_MULT			ZL_REG(13, 0x08, 4)
236#define ZL_REG_SYNTH_FREQ_M			ZL_REG(13, 0x0c, 2)
237#define ZL_REG_SYNTH_FREQ_N			ZL_REG(13, 0x0e, 2)
238
239/**********************************
240 * Register Page 14, Output Mailbox
241 **********************************/
242#define ZL_REG_OUTPUT_MB_MASK			ZL_REG(14, 0x02, 2)
243
244#define ZL_REG_OUTPUT_MB_SEM			ZL_REG(14, 0x04, 1)
245#define ZL_OUTPUT_MB_SEM_WR			BIT(0)
246#define ZL_OUTPUT_MB_SEM_RD			BIT(1)
247
248#define ZL_REG_OUTPUT_MODE			ZL_REG(14, 0x05, 1)
249#define ZL_OUTPUT_MODE_CLOCK_TYPE		GENMASK(2, 0)
250#define ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL	0
251#define ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC		1
252#define ZL_OUTPUT_MODE_SIGNAL_FORMAT		GENMASK(7, 4)
253#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_DISABLED	0
254#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_LVDS	1
255#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_DIFF	2
256#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_LOWVCM	3
257#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2		4
258#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_1P		5
259#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_1N		6
260#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_INV	7
261#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV	12
262#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV	15
263
264#define ZL_REG_OUTPUT_DIV			ZL_REG(14, 0x0c, 4)
265#define ZL_REG_OUTPUT_WIDTH			ZL_REG(14, 0x10, 4)
266#define ZL_REG_OUTPUT_ESYNC_PERIOD		ZL_REG(14, 0x14, 4)
267#define ZL_REG_OUTPUT_ESYNC_WIDTH		ZL_REG(14, 0x18, 4)
268#define ZL_REG_OUTPUT_PHASE_COMP		ZL_REG(14, 0x20, 4)
269
270/*
271 * Register Page 255 - HW registers access
272 */
273#define ZL_REG_HWREG_OP				ZL_REG(0xff, 0x00, 1)
274#define ZL_HWREG_OP_WRITE			0x28
275#define ZL_HWREG_OP_READ			0x29
276#define ZL_HWREG_OP_PENDING			BIT(1)
277
278#define ZL_REG_HWREG_ADDR			ZL_REG(0xff, 0x04, 4)
279#define ZL_REG_HWREG_WRITE_DATA			ZL_REG(0xff, 0x08, 4)
280#define ZL_REG_HWREG_READ_DATA			ZL_REG(0xff, 0x0c, 4)
281
282/*
283 * Registers available in flash mode
284 */
285#define ZL_REG_FLASH_HASH			ZL_REG(0, 0x78, 4)
286#define ZL_REG_FLASH_FAMILY			ZL_REG(0, 0x7c, 1)
287#define ZL_REG_FLASH_RELEASE			ZL_REG(0, 0x7d, 1)
288
289#define ZL_REG_HOST_CONTROL			ZL_REG(1, 0x02, 1)
290#define ZL_HOST_CONTROL_ENABLE			BIT(0)
291
292#define ZL_REG_IMAGE_START_ADDR			ZL_REG(1, 0x04, 4)
293#define ZL_REG_IMAGE_SIZE			ZL_REG(1, 0x08, 4)
294#define ZL_REG_FLASH_INDEX_READ			ZL_REG(1, 0x0c, 4)
295#define ZL_REG_FLASH_INDEX_WRITE		ZL_REG(1, 0x10, 4)
296#define ZL_REG_FILL_PATTERN			ZL_REG(1, 0x14, 4)
297
298#define ZL_REG_WRITE_FLASH			ZL_REG(1, 0x18, 1)
299#define ZL_WRITE_FLASH_OP			GENMASK(2, 0)
300#define ZL_WRITE_FLASH_OP_DONE			0x0
301#define ZL_WRITE_FLASH_OP_SECTORS		0x2
302#define ZL_WRITE_FLASH_OP_PAGE			0x3
303#define ZL_WRITE_FLASH_OP_COPY_PAGE		0x4
304
305#define ZL_REG_FLASH_INFO			ZL_REG(2, 0x00, 1)
306#define ZL_FLASH_INFO_SECTOR_SIZE		GENMASK(3, 0)
307#define ZL_FLASH_INFO_SECTOR_4K			0
308#define ZL_FLASH_INFO_SECTOR_64K		1
309
310#define ZL_REG_ERROR_COUNT			ZL_REG(2, 0x04, 4)
311#define ZL_REG_ERROR_CAUSE			ZL_REG(2, 0x08, 4)
312
313#define ZL_REG_OP_STATE				ZL_REG(2, 0x14, 1)
314#define ZL_OP_STATE_NO_COMMAND			0
315#define ZL_OP_STATE_PENDING			1
316#define ZL_OP_STATE_DONE			2
317
318#endif /* _ZL3073X_REGS_H */