dpll.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2
   3#include <linux/bits.h>
   4#include <linux/bitfield.h>
   5#include <linux/bug.h>
   6#include <linux/container_of.h>
   7#include <linux/dev_printk.h>
   8#include <linux/dpll.h>
   9#include <linux/err.h>
  10#include <linux/kthread.h>
  11#include <linux/math64.h>
  12#include <linux/mod_devicetable.h>
  13#include <linux/module.h>
  14#include <linux/netlink.h>
  15#include <linux/platform_device.h>
  16#include <linux/slab.h>
  17#include <linux/sprintf.h>
  18
  19#include "core.h"
  20#include "dpll.h"
  21#include "prop.h"
  22#include "regs.h"
  23
  24#define ZL3073X_DPLL_REF_NONE		ZL3073X_NUM_REFS
  25#define ZL3073X_DPLL_REF_IS_VALID(_ref)	((_ref) != ZL3073X_DPLL_REF_NONE)
  26
  27/**
  28 * struct zl3073x_dpll_pin - DPLL pin
  29 * @list: this DPLL pin list entry
  30 * @dpll: DPLL the pin is registered to
  31 * @dpll_pin: pointer to registered dpll_pin
  32 * @label: package label
  33 * @dir: pin direction
  34 * @id: pin id
  35 * @prio: pin priority <0, 14>
  36 * @selectable: pin is selectable in automatic mode
  37 * @esync_control: embedded sync is controllable
  38 * @phase_gran: phase adjustment granularity
  39 * @pin_state: last saved pin state
  40 * @phase_offset: last saved pin phase offset
  41 * @freq_offset: last saved fractional frequency offset
  42 */
  43struct zl3073x_dpll_pin {
  44	struct list_head	list;
  45	struct zl3073x_dpll	*dpll;
  46	struct dpll_pin		*dpll_pin;
  47	char			label[8];
  48	enum dpll_pin_direction	dir;
  49	u8			id;
  50	u8			prio;
  51	bool			selectable;
  52	bool			esync_control;
  53	s32			phase_gran;
  54	enum dpll_pin_state	pin_state;
  55	s64			phase_offset;
  56	s64			freq_offset;
  57};
  58
  59/*
  60 * Supported esync ranges for input and for output per output pair type
  61 */
  62static const struct dpll_pin_frequency esync_freq_ranges[] = {
  63	DPLL_PIN_FREQUENCY_RANGE(0, 1),
  64};
  65
  66/**
  67 * zl3073x_dpll_is_input_pin - check if the pin is input one
  68 * @pin: pin to check
  69 *
  70 * Return: true if pin is input, false if pin is output.
  71 */
  72static bool
  73zl3073x_dpll_is_input_pin(struct zl3073x_dpll_pin *pin)
  74{
  75	return pin->dir == DPLL_PIN_DIRECTION_INPUT;
  76}
  77
  78/**
  79 * zl3073x_dpll_is_p_pin - check if the pin is P-pin
  80 * @pin: pin to check
  81 *
  82 * Return: true if the pin is P-pin, false if it is N-pin
  83 */
  84static bool
  85zl3073x_dpll_is_p_pin(struct zl3073x_dpll_pin *pin)
  86{
  87	return zl3073x_is_p_pin(pin->id);
  88}
  89
  90static int
  91zl3073x_dpll_pin_direction_get(const struct dpll_pin *dpll_pin, void *pin_priv,
  92			       const struct dpll_device *dpll, void *dpll_priv,
  93			       enum dpll_pin_direction *direction,
  94			       struct netlink_ext_ack *extack)
  95{
  96	struct zl3073x_dpll_pin *pin = pin_priv;
  97
  98	*direction = pin->dir;
  99
 100	return 0;
 101}
 102
 103static int
 104zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin,
 105				 void *pin_priv,
 106				 const struct dpll_device *dpll,
 107				 void *dpll_priv,
 108				 struct dpll_pin_esync *esync,
 109				 struct netlink_ext_ack *extack)
 110{
 111	struct zl3073x_dpll *zldpll = dpll_priv;
 112	struct zl3073x_dev *zldev = zldpll->dev;
 113	struct zl3073x_dpll_pin *pin = pin_priv;
 114	const struct zl3073x_ref *ref;
 115	u8 ref_id;
 116
 117	ref_id = zl3073x_input_pin_ref_get(pin->id);
 118	ref = zl3073x_ref_state_get(zldev, ref_id);
 119
 120	switch (FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref->sync_ctrl)) {
 121	case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75:
 122		esync->freq = ref->esync_n_div == ZL_REF_ESYNC_DIV_1HZ ? 1 : 0;
 123		esync->pulse = 25;
 124		break;
 125	default:
 126		esync->freq = 0;
 127		esync->pulse = 0;
 128		break;
 129	}
 130
 131	/* If the pin supports esync control expose its range but only
 132	 * if the current reference frequency is > 1 Hz.
 133	 */
 134	if (pin->esync_control && zl3073x_ref_freq_get(ref) > 1) {
 135		esync->range = esync_freq_ranges;
 136		esync->range_num = ARRAY_SIZE(esync_freq_ranges);
 137	} else {
 138		esync->range = NULL;
 139		esync->range_num = 0;
 140	}
 141
 142	return 0;
 143}
 144
 145static int
 146zl3073x_dpll_input_pin_esync_set(const struct dpll_pin *dpll_pin,
 147				 void *pin_priv,
 148				 const struct dpll_device *dpll,
 149				 void *dpll_priv, u64 freq,
 150				 struct netlink_ext_ack *extack)
 151{
 152	struct zl3073x_dpll *zldpll = dpll_priv;
 153	struct zl3073x_dev *zldev = zldpll->dev;
 154	struct zl3073x_dpll_pin *pin = pin_priv;
 155	struct zl3073x_ref ref;
 156	u8 ref_id, sync_mode;
 157
 158	ref_id = zl3073x_input_pin_ref_get(pin->id);
 159	ref = *zl3073x_ref_state_get(zldev, ref_id);
 160
 161	/* Use freq == 0 to disable esync */
 162	if (!freq)
 163		sync_mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF;
 164	else
 165		sync_mode = ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75;
 166
 167	ref.sync_ctrl &= ~ZL_REF_SYNC_CTRL_MODE;
 168	ref.sync_ctrl |= FIELD_PREP(ZL_REF_SYNC_CTRL_MODE, sync_mode);
 169
 170	if (freq) {
 171		/* 1 Hz is only supported frequency now */
 172		ref.esync_n_div = ZL_REF_ESYNC_DIV_1HZ;
 173	}
 174
 175	/* Update reference configuration */
 176	return zl3073x_ref_state_set(zldev, ref_id, &ref);
 177}
 178
 179static int
 180zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv,
 181			       const struct dpll_device *dpll, void *dpll_priv,
 182			       s64 *ffo, struct netlink_ext_ack *extack)
 183{
 184	struct zl3073x_dpll_pin *pin = pin_priv;
 185
 186	*ffo = pin->freq_offset;
 187
 188	return 0;
 189}
 190
 191static int
 192zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin *dpll_pin,
 193				     void *pin_priv,
 194				     const struct dpll_device *dpll,
 195				     void *dpll_priv, u64 *frequency,
 196				     struct netlink_ext_ack *extack)
 197{
 198	struct zl3073x_dpll *zldpll = dpll_priv;
 199	struct zl3073x_dpll_pin *pin = pin_priv;
 200	u8 ref_id;
 201
 202	ref_id = zl3073x_input_pin_ref_get(pin->id);
 203	*frequency = zl3073x_dev_ref_freq_get(zldpll->dev, ref_id);
 204
 205	return 0;
 206}
 207
 208static int
 209zl3073x_dpll_input_pin_frequency_set(const struct dpll_pin *dpll_pin,
 210				     void *pin_priv,
 211				     const struct dpll_device *dpll,
 212				     void *dpll_priv, u64 frequency,
 213				     struct netlink_ext_ack *extack)
 214{
 215	struct zl3073x_dpll *zldpll = dpll_priv;
 216	struct zl3073x_dev *zldev = zldpll->dev;
 217	struct zl3073x_dpll_pin *pin = pin_priv;
 218	struct zl3073x_ref ref;
 219	u8 ref_id;
 220
 221	/* Get reference state */
 222	ref_id = zl3073x_input_pin_ref_get(pin->id);
 223	ref = *zl3073x_ref_state_get(zldev, ref_id);
 224
 225	/* Update frequency */
 226	zl3073x_ref_freq_set(&ref, frequency);
 227
 228	/* Commit reference state */
 229	return zl3073x_ref_state_set(zldev, ref_id, &ref);
 230}
 231
 232/**
 233 * zl3073x_dpll_selected_ref_get - get currently selected reference
 234 * @zldpll: pointer to zl3073x_dpll
 235 * @ref: place to store selected reference
 236 *
 237 * Check for currently selected reference the DPLL should be locked to
 238 * and stores its index to given @ref.
 239 *
 240 * Return: 0 on success, <0 on error
 241 */
 242static int
 243zl3073x_dpll_selected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref)
 244{
 245	struct zl3073x_dev *zldev = zldpll->dev;
 246	u8 state, value;
 247	int rc;
 248
 249	switch (zldpll->refsel_mode) {
 250	case ZL_DPLL_MODE_REFSEL_MODE_AUTO:
 251		/* For automatic mode read refsel_status register */
 252		rc = zl3073x_read_u8(zldev,
 253				     ZL_REG_DPLL_REFSEL_STATUS(zldpll->id),
 254				     &value);
 255		if (rc)
 256			return rc;
 257
 258		/* Extract reference state */
 259		state = FIELD_GET(ZL_DPLL_REFSEL_STATUS_STATE, value);
 260
 261		/* Return the reference only if the DPLL is locked to it */
 262		if (state == ZL_DPLL_REFSEL_STATUS_STATE_LOCK)
 263			*ref = FIELD_GET(ZL_DPLL_REFSEL_STATUS_REFSEL, value);
 264		else
 265			*ref = ZL3073X_DPLL_REF_NONE;
 266		break;
 267	case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK:
 268		/* For manual mode return stored value */
 269		*ref = zldpll->forced_ref;
 270		break;
 271	default:
 272		/* For other modes like NCO, freerun... there is no input ref */
 273		*ref = ZL3073X_DPLL_REF_NONE;
 274		break;
 275	}
 276
 277	return 0;
 278}
 279
 280/**
 281 * zl3073x_dpll_selected_ref_set - select reference in manual mode
 282 * @zldpll: pointer to zl3073x_dpll
 283 * @ref: input reference to be selected
 284 *
 285 * Selects the given reference for the DPLL channel it should be
 286 * locked to.
 287 *
 288 * Return: 0 on success, <0 on error
 289 */
 290static int
 291zl3073x_dpll_selected_ref_set(struct zl3073x_dpll *zldpll, u8 ref)
 292{
 293	struct zl3073x_dev *zldev = zldpll->dev;
 294	u8 mode, mode_refsel;
 295	int rc;
 296
 297	mode = zldpll->refsel_mode;
 298
 299	switch (mode) {
 300	case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK:
 301		/* Manual mode with ref selected */
 302		if (ref == ZL3073X_DPLL_REF_NONE) {
 303			switch (zldpll->lock_status) {
 304			case DPLL_LOCK_STATUS_LOCKED_HO_ACQ:
 305			case DPLL_LOCK_STATUS_HOLDOVER:
 306				/* Switch to forced holdover */
 307				mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER;
 308				break;
 309			default:
 310				/* Switch to freerun */
 311				mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN;
 312				break;
 313			}
 314			/* Keep selected reference */
 315			ref = zldpll->forced_ref;
 316		} else if (ref == zldpll->forced_ref) {
 317			/* No register update - same mode and same ref */
 318			return 0;
 319		}
 320		break;
 321	case ZL_DPLL_MODE_REFSEL_MODE_FREERUN:
 322	case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER:
 323		/* Manual mode without no ref */
 324		if (ref == ZL3073X_DPLL_REF_NONE)
 325			/* No register update - keep current mode */
 326			return 0;
 327
 328		/* Switch to reflock mode and update ref selection */
 329		mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK;
 330		break;
 331	default:
 332		/* For other modes like automatic or NCO ref cannot be selected
 333		 * manually
 334		 */
 335		return -EOPNOTSUPP;
 336	}
 337
 338	/* Build mode_refsel value */
 339	mode_refsel = FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, mode) |
 340		      FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref);
 341
 342	/* Update dpll_mode_refsel register */
 343	rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id),
 344			      mode_refsel);
 345	if (rc)
 346		return rc;
 347
 348	/* Store new mode and forced reference */
 349	zldpll->refsel_mode = mode;
 350	zldpll->forced_ref = ref;
 351
 352	return rc;
 353}
 354
 355/**
 356 * zl3073x_dpll_connected_ref_get - get currently connected reference
 357 * @zldpll: pointer to zl3073x_dpll
 358 * @ref: place to store selected reference
 359 *
 360 * Looks for currently connected the DPLL is locked to and stores its index
 361 * to given @ref.
 362 *
 363 * Return: 0 on success, <0 on error
 364 */
 365static int
 366zl3073x_dpll_connected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref)
 367{
 368	struct zl3073x_dev *zldev = zldpll->dev;
 369	int rc;
 370
 371	/* Get currently selected input reference */
 372	rc = zl3073x_dpll_selected_ref_get(zldpll, ref);
 373	if (rc)
 374		return rc;
 375
 376	/* If the monitor indicates an error nothing is connected */
 377	if (ZL3073X_DPLL_REF_IS_VALID(*ref) &&
 378	    !zl3073x_dev_ref_is_status_ok(zldev, *ref))
 379		*ref = ZL3073X_DPLL_REF_NONE;
 380
 381	return 0;
 382}
 383
 384static int
 385zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin *dpll_pin,
 386					void *pin_priv,
 387					const struct dpll_device *dpll,
 388					void *dpll_priv, s64 *phase_offset,
 389					struct netlink_ext_ack *extack)
 390{
 391	struct zl3073x_dpll *zldpll = dpll_priv;
 392	struct zl3073x_dev *zldev = zldpll->dev;
 393	struct zl3073x_dpll_pin *pin = pin_priv;
 394	const struct zl3073x_ref *ref;
 395	u8 conn_id, ref_id;
 396	s64 ref_phase;
 397	int rc;
 398
 399	/* Get currently connected reference */
 400	rc = zl3073x_dpll_connected_ref_get(zldpll, &conn_id);
 401	if (rc)
 402		return rc;
 403
 404	/* Report phase offset only for currently connected pin if the phase
 405	 * monitor feature is disabled and only if the input pin signal is
 406	 * present.
 407	 */
 408	ref_id = zl3073x_input_pin_ref_get(pin->id);
 409	ref = zl3073x_ref_state_get(zldev, ref_id);
 410	if ((!zldpll->phase_monitor && ref_id != conn_id) ||
 411	    !zl3073x_ref_is_status_ok(ref)) {
 412		*phase_offset = 0;
 413		return 0;
 414	}
 415
 416	ref_phase = pin->phase_offset;
 417
 418	/* The DPLL being locked to a higher freq than the current ref
 419	 * the phase offset is modded to the period of the signal
 420	 * the dpll is locked to.
 421	 */
 422	if (ZL3073X_DPLL_REF_IS_VALID(conn_id) && conn_id != ref_id) {
 423		u32 conn_freq, ref_freq;
 424
 425		/* Get frequency of connected and given ref */
 426		conn_freq = zl3073x_dev_ref_freq_get(zldev, conn_id);
 427		ref_freq = zl3073x_ref_freq_get(ref);
 428
 429		if (conn_freq > ref_freq) {
 430			s64 conn_period, div_factor;
 431
 432			conn_period = div_s64(PSEC_PER_SEC, conn_freq);
 433			div_factor = div64_s64(ref_phase, conn_period);
 434			ref_phase -= conn_period * div_factor;
 435		}
 436	}
 437
 438	*phase_offset = ref_phase * DPLL_PHASE_OFFSET_DIVIDER;
 439
 440	return rc;
 441}
 442
 443static int
 444zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin *dpll_pin,
 445					void *pin_priv,
 446					const struct dpll_device *dpll,
 447					void *dpll_priv,
 448					s32 *phase_adjust,
 449					struct netlink_ext_ack *extack)
 450{
 451	struct zl3073x_dpll *zldpll = dpll_priv;
 452	struct zl3073x_dev *zldev = zldpll->dev;
 453	struct zl3073x_dpll_pin *pin = pin_priv;
 454	const struct zl3073x_ref *ref;
 455	s64 phase_comp;
 456	u8 ref_id;
 457
 458	/* Read reference configuration */
 459	ref_id = zl3073x_input_pin_ref_get(pin->id);
 460	ref = zl3073x_ref_state_get(zldev, ref_id);
 461
 462	/* Perform sign extension based on register width */
 463	if (zl3073x_dev_is_ref_phase_comp_32bit(zldev))
 464		phase_comp = sign_extend64(ref->phase_comp, 31);
 465	else
 466		phase_comp = sign_extend64(ref->phase_comp, 47);
 467
 468	/* Reverse two's complement negation applied during set and convert
 469	 * to 32bit signed int
 470	 */
 471	*phase_adjust = (s32)-phase_comp;
 472
 473	return 0;
 474}
 475
 476static int
 477zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin *dpll_pin,
 478					void *pin_priv,
 479					const struct dpll_device *dpll,
 480					void *dpll_priv,
 481					s32 phase_adjust,
 482					struct netlink_ext_ack *extack)
 483{
 484	struct zl3073x_dpll *zldpll = dpll_priv;
 485	struct zl3073x_dev *zldev = zldpll->dev;
 486	struct zl3073x_dpll_pin *pin = pin_priv;
 487	struct zl3073x_ref ref;
 488	u8 ref_id;
 489
 490	/* Read reference configuration */
 491	ref_id = zl3073x_input_pin_ref_get(pin->id);
 492	ref = *zl3073x_ref_state_get(zldev, ref_id);
 493
 494	/* The value in the register is stored as two's complement negation
 495	 * of requested value.
 496	 */
 497	ref.phase_comp = -phase_adjust;
 498
 499	/* Update reference configuration */
 500	return zl3073x_ref_state_set(zldev, ref_id, &ref);
 501}
 502
 503/**
 504 * zl3073x_dpll_ref_prio_get - get priority for given input pin
 505 * @pin: pointer to pin
 506 * @prio: place to store priority
 507 *
 508 * Reads current priority for the given input pin and stores the value
 509 * to @prio.
 510 *
 511 * Return: 0 on success, <0 on error
 512 */
 513static int
 514zl3073x_dpll_ref_prio_get(struct zl3073x_dpll_pin *pin, u8 *prio)
 515{
 516	struct zl3073x_dpll *zldpll = pin->dpll;
 517	struct zl3073x_dev *zldev = zldpll->dev;
 518	u8 ref, ref_prio;
 519	int rc;
 520
 521	guard(mutex)(&zldev->multiop_lock);
 522
 523	/* Read DPLL configuration */
 524	rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD,
 525			   ZL_REG_DPLL_MB_MASK, BIT(zldpll->id));
 526	if (rc)
 527		return rc;
 528
 529	/* Read reference priority - one value for P&N pins (4 bits/pin) */
 530	ref = zl3073x_input_pin_ref_get(pin->id);
 531	rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2),
 532			     &ref_prio);
 533	if (rc)
 534		return rc;
 535
 536	/* Select nibble according pin type */
 537	if (zl3073x_dpll_is_p_pin(pin))
 538		*prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_P, ref_prio);
 539	else
 540		*prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_N, ref_prio);
 541
 542	return rc;
 543}
 544
 545/**
 546 * zl3073x_dpll_ref_prio_set - set priority for given input pin
 547 * @pin: pointer to pin
 548 * @prio: place to store priority
 549 *
 550 * Sets priority for the given input pin.
 551 *
 552 * Return: 0 on success, <0 on error
 553 */
 554static int
 555zl3073x_dpll_ref_prio_set(struct zl3073x_dpll_pin *pin, u8 prio)
 556{
 557	struct zl3073x_dpll *zldpll = pin->dpll;
 558	struct zl3073x_dev *zldev = zldpll->dev;
 559	u8 ref, ref_prio;
 560	int rc;
 561
 562	guard(mutex)(&zldev->multiop_lock);
 563
 564	/* Read DPLL configuration into mailbox */
 565	rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD,
 566			   ZL_REG_DPLL_MB_MASK, BIT(zldpll->id));
 567	if (rc)
 568		return rc;
 569
 570	/* Read reference priority - one value shared between P&N pins */
 571	ref = zl3073x_input_pin_ref_get(pin->id);
 572	rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), &ref_prio);
 573	if (rc)
 574		return rc;
 575
 576	/* Update nibble according pin type */
 577	if (zl3073x_dpll_is_p_pin(pin)) {
 578		ref_prio &= ~ZL_DPLL_REF_PRIO_REF_P;
 579		ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_P, prio);
 580	} else {
 581		ref_prio &= ~ZL_DPLL_REF_PRIO_REF_N;
 582		ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_N, prio);
 583	}
 584
 585	/* Update reference priority */
 586	rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), ref_prio);
 587	if (rc)
 588		return rc;
 589
 590	/* Commit configuration */
 591	return zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_WR,
 592			     ZL_REG_DPLL_MB_MASK, BIT(zldpll->id));
 593}
 594
 595/**
 596 * zl3073x_dpll_ref_state_get - get status for given input pin
 597 * @pin: pointer to pin
 598 * @state: place to store status
 599 *
 600 * Checks current status for the given input pin and stores the value
 601 * to @state.
 602 *
 603 * Return: 0 on success, <0 on error
 604 */
 605static int
 606zl3073x_dpll_ref_state_get(struct zl3073x_dpll_pin *pin,
 607			   enum dpll_pin_state *state)
 608{
 609	struct zl3073x_dpll *zldpll = pin->dpll;
 610	struct zl3073x_dev *zldev = zldpll->dev;
 611	u8 ref, ref_conn;
 612	int rc;
 613
 614	ref = zl3073x_input_pin_ref_get(pin->id);
 615
 616	/* Get currently connected reference */
 617	rc = zl3073x_dpll_connected_ref_get(zldpll, &ref_conn);
 618	if (rc)
 619		return rc;
 620
 621	if (ref == ref_conn) {
 622		*state = DPLL_PIN_STATE_CONNECTED;
 623		return 0;
 624	}
 625
 626	/* If the DPLL is running in automatic mode and the reference is
 627	 * selectable and its monitor does not report any error then report
 628	 * pin as selectable.
 629	 */
 630	if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_AUTO &&
 631	    zl3073x_dev_ref_is_status_ok(zldev, ref) && pin->selectable) {
 632		*state = DPLL_PIN_STATE_SELECTABLE;
 633		return 0;
 634	}
 635
 636	/* Otherwise report the pin as disconnected */
 637	*state = DPLL_PIN_STATE_DISCONNECTED;
 638
 639	return 0;
 640}
 641
 642static int
 643zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin,
 644					 void *pin_priv,
 645					 const struct dpll_device *dpll,
 646					 void *dpll_priv,
 647					 enum dpll_pin_state *state,
 648					 struct netlink_ext_ack *extack)
 649{
 650	struct zl3073x_dpll_pin *pin = pin_priv;
 651
 652	return zl3073x_dpll_ref_state_get(pin, state);
 653}
 654
 655static int
 656zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin *dpll_pin,
 657					 void *pin_priv,
 658					 const struct dpll_device *dpll,
 659					 void *dpll_priv,
 660					 enum dpll_pin_state state,
 661					 struct netlink_ext_ack *extack)
 662{
 663	struct zl3073x_dpll *zldpll = dpll_priv;
 664	struct zl3073x_dpll_pin *pin = pin_priv;
 665	u8 new_ref;
 666	int rc;
 667
 668	switch (zldpll->refsel_mode) {
 669	case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK:
 670	case ZL_DPLL_MODE_REFSEL_MODE_FREERUN:
 671	case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER:
 672		if (state == DPLL_PIN_STATE_CONNECTED) {
 673			/* Choose the pin as new selected reference */
 674			new_ref = zl3073x_input_pin_ref_get(pin->id);
 675		} else if (state == DPLL_PIN_STATE_DISCONNECTED) {
 676			/* No reference */
 677			new_ref = ZL3073X_DPLL_REF_NONE;
 678		} else {
 679			NL_SET_ERR_MSG_MOD(extack,
 680					   "Invalid pin state for manual mode");
 681			return -EINVAL;
 682		}
 683
 684		rc = zl3073x_dpll_selected_ref_set(zldpll, new_ref);
 685		break;
 686
 687	case ZL_DPLL_MODE_REFSEL_MODE_AUTO:
 688		if (state == DPLL_PIN_STATE_SELECTABLE) {
 689			if (pin->selectable)
 690				return 0; /* Pin is already selectable */
 691
 692			/* Restore pin priority in HW */
 693			rc = zl3073x_dpll_ref_prio_set(pin, pin->prio);
 694			if (rc)
 695				return rc;
 696
 697			/* Mark pin as selectable */
 698			pin->selectable = true;
 699		} else if (state == DPLL_PIN_STATE_DISCONNECTED) {
 700			if (!pin->selectable)
 701				return 0; /* Pin is already disconnected */
 702
 703			/* Set pin priority to none in HW */
 704			rc = zl3073x_dpll_ref_prio_set(pin,
 705						       ZL_DPLL_REF_PRIO_NONE);
 706			if (rc)
 707				return rc;
 708
 709			/* Mark pin as non-selectable */
 710			pin->selectable = false;
 711		} else {
 712			NL_SET_ERR_MSG(extack,
 713				       "Invalid pin state for automatic mode");
 714			return -EINVAL;
 715		}
 716		break;
 717
 718	default:
 719		/* In other modes we cannot change input reference */
 720		NL_SET_ERR_MSG(extack,
 721			       "Pin state cannot be changed in current mode");
 722		rc = -EOPNOTSUPP;
 723		break;
 724	}
 725
 726	return rc;
 727}
 728
 729static int
 730zl3073x_dpll_input_pin_prio_get(const struct dpll_pin *dpll_pin, void *pin_priv,
 731				const struct dpll_device *dpll, void *dpll_priv,
 732				u32 *prio, struct netlink_ext_ack *extack)
 733{
 734	struct zl3073x_dpll_pin *pin = pin_priv;
 735
 736	*prio = pin->prio;
 737
 738	return 0;
 739}
 740
 741static int
 742zl3073x_dpll_input_pin_prio_set(const struct dpll_pin *dpll_pin, void *pin_priv,
 743				const struct dpll_device *dpll, void *dpll_priv,
 744				u32 prio, struct netlink_ext_ack *extack)
 745{
 746	struct zl3073x_dpll_pin *pin = pin_priv;
 747	int rc;
 748
 749	if (prio > ZL_DPLL_REF_PRIO_MAX)
 750		return -EINVAL;
 751
 752	/* If the pin is selectable then update HW registers */
 753	if (pin->selectable) {
 754		rc = zl3073x_dpll_ref_prio_set(pin, prio);
 755		if (rc)
 756			return rc;
 757	}
 758
 759	/* Save priority */
 760	pin->prio = prio;
 761
 762	return 0;
 763}
 764
 765static int
 766zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin,
 767				  void *pin_priv,
 768				  const struct dpll_device *dpll,
 769				  void *dpll_priv,
 770				  struct dpll_pin_esync *esync,
 771				  struct netlink_ext_ack *extack)
 772{
 773	struct zl3073x_dpll *zldpll = dpll_priv;
 774	struct zl3073x_dev *zldev = zldpll->dev;
 775	struct zl3073x_dpll_pin *pin = pin_priv;
 776	const struct zl3073x_synth *synth;
 777	const struct zl3073x_out *out;
 778	u8 clock_type, out_id;
 779	u32 synth_freq;
 780
 781	out_id = zl3073x_output_pin_out_get(pin->id);
 782	out = zl3073x_out_state_get(zldev, out_id);
 783
 784	/* If N-division is enabled, esync is not supported. The register used
 785	 * for N-division is also used for the esync divider so both cannot
 786	 * be used.
 787	 */
 788	switch (zl3073x_out_signal_format_get(out)) {
 789	case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV:
 790	case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV:
 791		return -EOPNOTSUPP;
 792	default:
 793		break;
 794	}
 795
 796	/* Get attached synth frequency */
 797	synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(out));
 798	synth_freq = zl3073x_synth_freq_get(synth);
 799
 800	clock_type = FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, out->mode);
 801	if (clock_type != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) {
 802		/* No need to read esync data if it is not enabled */
 803		esync->freq = 0;
 804		esync->pulse = 0;
 805
 806		goto finish;
 807	}
 808
 809	/* Compute esync frequency */
 810	esync->freq = synth_freq / out->div / out->esync_n_period;
 811
 812	/* By comparing the esync_pulse_width to the half of the pulse width
 813	 * the esync pulse percentage can be determined.
 814	 * Note that half pulse width is in units of half synth cycles, which
 815	 * is why it reduces down to be output_div.
 816	 */
 817	esync->pulse = (50 * out->esync_n_width) / out->div;
 818
 819finish:
 820	/* Set supported esync ranges if the pin supports esync control and
 821	 * if the output frequency is > 1 Hz.
 822	 */
 823	if (pin->esync_control && (synth_freq / out->div) > 1) {
 824		esync->range = esync_freq_ranges;
 825		esync->range_num = ARRAY_SIZE(esync_freq_ranges);
 826	} else {
 827		esync->range = NULL;
 828		esync->range_num = 0;
 829	}
 830
 831	return 0;
 832}
 833
 834static int
 835zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin,
 836				  void *pin_priv,
 837				  const struct dpll_device *dpll,
 838				  void *dpll_priv, u64 freq,
 839				  struct netlink_ext_ack *extack)
 840{
 841	struct zl3073x_dpll *zldpll = dpll_priv;
 842	struct zl3073x_dev *zldev = zldpll->dev;
 843	struct zl3073x_dpll_pin *pin = pin_priv;
 844	const struct zl3073x_synth *synth;
 845	struct zl3073x_out out;
 846	u8 clock_type, out_id;
 847	u32 synth_freq;
 848
 849	out_id = zl3073x_output_pin_out_get(pin->id);
 850	out = *zl3073x_out_state_get(zldev, out_id);
 851
 852	/* If N-division is enabled, esync is not supported. The register used
 853	 * for N-division is also used for the esync divider so both cannot
 854	 * be used.
 855	 */
 856	switch (zl3073x_out_signal_format_get(&out)) {
 857	case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV:
 858	case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV:
 859		return -EOPNOTSUPP;
 860	default:
 861		break;
 862	}
 863
 864	/* Select clock type */
 865	if (freq)
 866		clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC;
 867	else
 868		clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL;
 869
 870	/* Update clock type in output mode */
 871	out.mode &= ~ZL_OUTPUT_MODE_CLOCK_TYPE;
 872	out.mode |= FIELD_PREP(ZL_OUTPUT_MODE_CLOCK_TYPE, clock_type);
 873
 874	/* If esync is being disabled just write mailbox and finish */
 875	if (!freq)
 876		goto write_mailbox;
 877
 878	/* Get attached synth frequency */
 879	synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(&out));
 880	synth_freq = zl3073x_synth_freq_get(synth);
 881
 882	/* Compute and update esync period */
 883	out.esync_n_period = synth_freq / (u32)freq / out.div;
 884
 885	/* Half of the period in units of 1/2 synth cycle can be represented by
 886	 * the output_div. To get the supported esync pulse width of 25% of the
 887	 * period the output_div can just be divided by 2. Note that this
 888	 * assumes that output_div is even, otherwise some resolution will be
 889	 * lost.
 890	 */
 891	out.esync_n_width = out.div / 2;
 892
 893write_mailbox:
 894	/* Commit output configuration */
 895	return zl3073x_out_state_set(zldev, out_id, &out);
 896}
 897
 898static int
 899zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin *dpll_pin,
 900				      void *pin_priv,
 901				      const struct dpll_device *dpll,
 902				      void *dpll_priv, u64 *frequency,
 903				      struct netlink_ext_ack *extack)
 904{
 905	struct zl3073x_dpll *zldpll = dpll_priv;
 906	struct zl3073x_dev *zldev = zldpll->dev;
 907	struct zl3073x_dpll_pin *pin = pin_priv;
 908	const struct zl3073x_synth *synth;
 909	const struct zl3073x_out *out;
 910	u32 synth_freq;
 911	u8 out_id;
 912
 913	out_id = zl3073x_output_pin_out_get(pin->id);
 914	out = zl3073x_out_state_get(zldev, out_id);
 915
 916	/* Get attached synth frequency */
 917	synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(out));
 918	synth_freq = zl3073x_synth_freq_get(synth);
 919
 920	switch (zl3073x_out_signal_format_get(out)) {
 921	case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV:
 922	case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV:
 923		/* In case of divided format we have to distiguish between
 924		 * given output pin type.
 925		 *
 926		 * For P-pin the resulting frequency is computed as simple
 927		 * division of synth frequency and output divisor.
 928		 *
 929		 * For N-pin we have to divide additionally by divisor stored
 930		 * in esync_n_period output mailbox register that is used as
 931		 * N-pin divisor for these modes.
 932		 */
 933		*frequency = synth_freq / out->div;
 934
 935		if (!zl3073x_dpll_is_p_pin(pin))
 936			*frequency = (u32)*frequency / out->esync_n_period;
 937
 938		break;
 939	default:
 940		/* In other modes the resulting frequency is computed as
 941		 * division of synth frequency and output divisor.
 942		 */
 943		*frequency = synth_freq / out->div;
 944		break;
 945	}
 946
 947	return 0;
 948}
 949
 950static int
 951zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin,
 952				      void *pin_priv,
 953				      const struct dpll_device *dpll,
 954				      void *dpll_priv, u64 frequency,
 955				      struct netlink_ext_ack *extack)
 956{
 957	struct zl3073x_dpll *zldpll = dpll_priv;
 958	struct zl3073x_dev *zldev = zldpll->dev;
 959	struct zl3073x_dpll_pin *pin = pin_priv;
 960	const struct zl3073x_synth *synth;
 961	u8 out_id, signal_format;
 962	u32 new_div, synth_freq;
 963	struct zl3073x_out out;
 964
 965	out_id = zl3073x_output_pin_out_get(pin->id);
 966	out = *zl3073x_out_state_get(zldev, out_id);
 967
 968	/* Get attached synth frequency and compute new divisor */
 969	synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(&out));
 970	synth_freq = zl3073x_synth_freq_get(synth);
 971	new_div = synth_freq / (u32)frequency;
 972
 973	/* Get used signal format for the given output */
 974	signal_format = zl3073x_out_signal_format_get(&out);
 975
 976	/* Check signal format */
 977	if (signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV &&
 978	    signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV) {
 979		/* For non N-divided signal formats the frequency is computed
 980		 * as division of synth frequency and output divisor.
 981		 */
 982		out.div = new_div;
 983
 984		/* For 50/50 duty cycle the divisor is equal to width */
 985		out.width = new_div;
 986
 987		/* Commit output configuration */
 988		return zl3073x_out_state_set(zldev, out_id, &out);
 989	}
 990
 991	if (zl3073x_dpll_is_p_pin(pin)) {
 992		/* We are going to change output frequency for P-pin but
 993		 * if the requested frequency is less than current N-pin
 994		 * frequency then indicate a failure as we are not able
 995		 * to compute N-pin divisor to keep its frequency unchanged.
 996		 *
 997		 * Update divisor for N-pin to keep N-pin frequency.
 998		 */
 999		out.esync_n_period = (out.esync_n_period * out.div) / new_div;
1000		if (!out.esync_n_period)
1001			return -EINVAL;
1002
1003		/* Update the output divisor */
1004		out.div = new_div;
1005
1006		/* For 50/50 duty cycle the divisor is equal to width */
1007		out.width = out.div;
1008	} else {
1009		/* We are going to change frequency of N-pin but if
1010		 * the requested freq is greater or equal than freq of P-pin
1011		 * in the output pair we cannot compute divisor for the N-pin.
1012		 * In this case indicate a failure.
1013		 *
1014		 * Update divisor for N-pin
1015		 */
1016		out.esync_n_period = div64_u64(synth_freq, frequency * out.div);
1017		if (!out.esync_n_period)
1018			return -EINVAL;
1019	}
1020
1021	/* For 50/50 duty cycle the divisor is equal to width */
1022	out.esync_n_width = out.esync_n_period;
1023
1024	/* Commit output configuration */
1025	return zl3073x_out_state_set(zldev, out_id, &out);
1026}
1027
1028static int
1029zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin,
1030					 void *pin_priv,
1031					 const struct dpll_device *dpll,
1032					 void *dpll_priv,
1033					 s32 *phase_adjust,
1034					 struct netlink_ext_ack *extack)
1035{
1036	struct zl3073x_dpll *zldpll = dpll_priv;
1037	struct zl3073x_dev *zldev = zldpll->dev;
1038	struct zl3073x_dpll_pin *pin = pin_priv;
1039	const struct zl3073x_out *out;
1040	u8 out_id;
1041
1042	out_id = zl3073x_output_pin_out_get(pin->id);
1043	out = zl3073x_out_state_get(zldev, out_id);
1044
1045	/* The value in the register is expressed in half synth clock cycles. */
1046	*phase_adjust = out->phase_comp * pin->phase_gran;
1047
1048	return 0;
1049}
1050
1051static int
1052zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin *dpll_pin,
1053					 void *pin_priv,
1054					 const struct dpll_device *dpll,
1055					 void *dpll_priv,
1056					 s32 phase_adjust,
1057					 struct netlink_ext_ack *extack)
1058{
1059	struct zl3073x_dpll *zldpll = dpll_priv;
1060	struct zl3073x_dev *zldev = zldpll->dev;
1061	struct zl3073x_dpll_pin *pin = pin_priv;
1062	struct zl3073x_out out;
1063	u8 out_id;
1064
1065	out_id = zl3073x_output_pin_out_get(pin->id);
1066	out = *zl3073x_out_state_get(zldev, out_id);
1067
1068	/* The value in the register is expressed in half synth clock cycles. */
1069	out.phase_comp = phase_adjust / pin->phase_gran;
1070
1071	/* Update output configuration from mailbox */
1072	return zl3073x_out_state_set(zldev, out_id, &out);
1073}
1074
1075static int
1076zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin,
1077					  void *pin_priv,
1078					  const struct dpll_device *dpll,
1079					  void *dpll_priv,
1080					  enum dpll_pin_state *state,
1081					  struct netlink_ext_ack *extack)
1082{
1083	/* If the output pin is registered then it is always connected */
1084	*state = DPLL_PIN_STATE_CONNECTED;
1085
1086	return 0;
1087}
1088
1089static int
1090zl3073x_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv,
1091			     enum dpll_lock_status *status,
1092			     enum dpll_lock_status_error *status_error,
1093			     struct netlink_ext_ack *extack)
1094{
1095	struct zl3073x_dpll *zldpll = dpll_priv;
1096	struct zl3073x_dev *zldev = zldpll->dev;
1097	u8 mon_status, state;
1098	int rc;
1099
1100	switch (zldpll->refsel_mode) {
1101	case ZL_DPLL_MODE_REFSEL_MODE_FREERUN:
1102	case ZL_DPLL_MODE_REFSEL_MODE_NCO:
1103		/* In FREERUN and NCO modes the DPLL is always unlocked */
1104		*status = DPLL_LOCK_STATUS_UNLOCKED;
1105
1106		return 0;
1107	default:
1108		break;
1109	}
1110
1111	/* Read DPLL monitor status */
1112	rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MON_STATUS(zldpll->id),
1113			     &mon_status);
1114	if (rc)
1115		return rc;
1116	state = FIELD_GET(ZL_DPLL_MON_STATUS_STATE, mon_status);
1117
1118	switch (state) {
1119	case ZL_DPLL_MON_STATUS_STATE_LOCK:
1120		if (FIELD_GET(ZL_DPLL_MON_STATUS_HO_READY, mon_status))
1121			*status = DPLL_LOCK_STATUS_LOCKED_HO_ACQ;
1122		else
1123			*status = DPLL_LOCK_STATUS_LOCKED;
1124		break;
1125	case ZL_DPLL_MON_STATUS_STATE_HOLDOVER:
1126	case ZL_DPLL_MON_STATUS_STATE_ACQUIRING:
1127		*status = DPLL_LOCK_STATUS_HOLDOVER;
1128		break;
1129	default:
1130		dev_warn(zldev->dev, "Unknown DPLL monitor status: 0x%02x\n",
1131			 mon_status);
1132		*status = DPLL_LOCK_STATUS_UNLOCKED;
1133		break;
1134	}
1135
1136	return 0;
1137}
1138
1139static int
1140zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv,
1141		      enum dpll_mode *mode, struct netlink_ext_ack *extack)
1142{
1143	struct zl3073x_dpll *zldpll = dpll_priv;
1144
1145	switch (zldpll->refsel_mode) {
1146	case ZL_DPLL_MODE_REFSEL_MODE_FREERUN:
1147	case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER:
1148	case ZL_DPLL_MODE_REFSEL_MODE_NCO:
1149	case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK:
1150		/* Use MANUAL for device FREERUN, HOLDOVER, NCO and
1151		 * REFLOCK modes
1152		 */
1153		*mode = DPLL_MODE_MANUAL;
1154		break;
1155	case ZL_DPLL_MODE_REFSEL_MODE_AUTO:
1156		/* Use AUTO for device AUTO mode */
1157		*mode = DPLL_MODE_AUTOMATIC;
1158		break;
1159	default:
1160		return -EINVAL;
1161	}
1162
1163	return 0;
1164}
1165
1166static int
1167zl3073x_dpll_phase_offset_avg_factor_get(const struct dpll_device *dpll,
1168					 void *dpll_priv, u32 *factor,
1169					 struct netlink_ext_ack *extack)
1170{
1171	struct zl3073x_dpll *zldpll = dpll_priv;
1172
1173	*factor = zl3073x_dev_phase_avg_factor_get(zldpll->dev);
1174
1175	return 0;
1176}
1177
1178static void
1179zl3073x_dpll_change_work(struct work_struct *work)
1180{
1181	struct zl3073x_dpll *zldpll;
1182
1183	zldpll = container_of(work, struct zl3073x_dpll, change_work);
1184	dpll_device_change_ntf(zldpll->dpll_dev);
1185}
1186
1187static int
1188zl3073x_dpll_phase_offset_avg_factor_set(const struct dpll_device *dpll,
1189					 void *dpll_priv, u32 factor,
1190					 struct netlink_ext_ack *extack)
1191{
1192	struct zl3073x_dpll *item, *zldpll = dpll_priv;
1193	int rc;
1194
1195	if (factor > 15) {
1196		NL_SET_ERR_MSG_FMT(extack,
1197				   "Phase offset average factor has to be from range <0,15>");
1198		return -EINVAL;
1199	}
1200
1201	rc = zl3073x_dev_phase_avg_factor_set(zldpll->dev, factor);
1202	if (rc) {
1203		NL_SET_ERR_MSG_FMT(extack,
1204				   "Failed to set phase offset averaging factor");
1205		return rc;
1206	}
1207
1208	/* The averaging factor is common for all DPLL channels so after change
1209	 * we have to send a notification for other DPLL devices.
1210	 */
1211	list_for_each_entry(item, &zldpll->dev->dplls, list) {
1212		if (item != zldpll)
1213			schedule_work(&item->change_work);
1214	}
1215
1216	return 0;
1217}
1218
1219static int
1220zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device *dpll,
1221				      void *dpll_priv,
1222				      enum dpll_feature_state *state,
1223				      struct netlink_ext_ack *extack)
1224{
1225	struct zl3073x_dpll *zldpll = dpll_priv;
1226
1227	if (zldpll->phase_monitor)
1228		*state = DPLL_FEATURE_STATE_ENABLE;
1229	else
1230		*state = DPLL_FEATURE_STATE_DISABLE;
1231
1232	return 0;
1233}
1234
1235static int
1236zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device *dpll,
1237				      void *dpll_priv,
1238				      enum dpll_feature_state state,
1239				      struct netlink_ext_ack *extack)
1240{
1241	struct zl3073x_dpll *zldpll = dpll_priv;
1242
1243	zldpll->phase_monitor = (state == DPLL_FEATURE_STATE_ENABLE);
1244
1245	return 0;
1246}
1247
1248static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops = {
1249	.direction_get = zl3073x_dpll_pin_direction_get,
1250	.esync_get = zl3073x_dpll_input_pin_esync_get,
1251	.esync_set = zl3073x_dpll_input_pin_esync_set,
1252	.ffo_get = zl3073x_dpll_input_pin_ffo_get,
1253	.frequency_get = zl3073x_dpll_input_pin_frequency_get,
1254	.frequency_set = zl3073x_dpll_input_pin_frequency_set,
1255	.phase_offset_get = zl3073x_dpll_input_pin_phase_offset_get,
1256	.phase_adjust_get = zl3073x_dpll_input_pin_phase_adjust_get,
1257	.phase_adjust_set = zl3073x_dpll_input_pin_phase_adjust_set,
1258	.prio_get = zl3073x_dpll_input_pin_prio_get,
1259	.prio_set = zl3073x_dpll_input_pin_prio_set,
1260	.state_on_dpll_get = zl3073x_dpll_input_pin_state_on_dpll_get,
1261	.state_on_dpll_set = zl3073x_dpll_input_pin_state_on_dpll_set,
1262};
1263
1264static const struct dpll_pin_ops zl3073x_dpll_output_pin_ops = {
1265	.direction_get = zl3073x_dpll_pin_direction_get,
1266	.esync_get = zl3073x_dpll_output_pin_esync_get,
1267	.esync_set = zl3073x_dpll_output_pin_esync_set,
1268	.frequency_get = zl3073x_dpll_output_pin_frequency_get,
1269	.frequency_set = zl3073x_dpll_output_pin_frequency_set,
1270	.phase_adjust_get = zl3073x_dpll_output_pin_phase_adjust_get,
1271	.phase_adjust_set = zl3073x_dpll_output_pin_phase_adjust_set,
1272	.state_on_dpll_get = zl3073x_dpll_output_pin_state_on_dpll_get,
1273};
1274
1275static const struct dpll_device_ops zl3073x_dpll_device_ops = {
1276	.lock_status_get = zl3073x_dpll_lock_status_get,
1277	.mode_get = zl3073x_dpll_mode_get,
1278	.phase_offset_avg_factor_get = zl3073x_dpll_phase_offset_avg_factor_get,
1279	.phase_offset_avg_factor_set = zl3073x_dpll_phase_offset_avg_factor_set,
1280	.phase_offset_monitor_get = zl3073x_dpll_phase_offset_monitor_get,
1281	.phase_offset_monitor_set = zl3073x_dpll_phase_offset_monitor_set,
1282};
1283
1284/**
1285 * zl3073x_dpll_pin_alloc - allocate DPLL pin
1286 * @zldpll: pointer to zl3073x_dpll
1287 * @dir: pin direction
1288 * @id: pin id
1289 *
1290 * Allocates and initializes zl3073x_dpll_pin structure for given
1291 * pin id and direction.
1292 *
1293 * Return: pointer to allocated structure on success, error pointer on error
1294 */
1295static struct zl3073x_dpll_pin *
1296zl3073x_dpll_pin_alloc(struct zl3073x_dpll *zldpll, enum dpll_pin_direction dir,
1297		       u8 id)
1298{
1299	struct zl3073x_dpll_pin *pin;
1300
1301	pin = kzalloc(sizeof(*pin), GFP_KERNEL);
1302	if (!pin)
1303		return ERR_PTR(-ENOMEM);
1304
1305	pin->dpll = zldpll;
1306	pin->dir = dir;
1307	pin->id = id;
1308
1309	return pin;
1310}
1311
1312/**
1313 * zl3073x_dpll_pin_free - deallocate DPLL pin
1314 * @pin: pin to free
1315 *
1316 * Deallocates DPLL pin previously allocated by @zl3073x_dpll_pin_alloc.
1317 */
1318static void
1319zl3073x_dpll_pin_free(struct zl3073x_dpll_pin *pin)
1320{
1321	WARN(pin->dpll_pin, "DPLL pin is still registered\n");
1322
1323	kfree(pin);
1324}
1325
1326/**
1327 * zl3073x_dpll_pin_register - register DPLL pin
1328 * @pin: pointer to DPLL pin
1329 * @index: absolute pin index for registration
1330 *
1331 * Registers given DPLL pin into DPLL sub-system.
1332 *
1333 * Return: 0 on success, <0 on error
1334 */
1335static int
1336zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index)
1337{
1338	struct zl3073x_dpll *zldpll = pin->dpll;
1339	struct zl3073x_pin_props *props;
1340	const struct dpll_pin_ops *ops;
1341	int rc;
1342
1343	/* Get pin properties */
1344	props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id);
1345	if (IS_ERR(props))
1346		return PTR_ERR(props);
1347
1348	/* Save package label, esync capability and phase adjust granularity */
1349	strscpy(pin->label, props->package_label);
1350	pin->esync_control = props->esync_control;
1351	pin->phase_gran = props->dpll_props.phase_gran;
1352
1353	if (zl3073x_dpll_is_input_pin(pin)) {
1354		rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio);
1355		if (rc)
1356			goto err_prio_get;
1357
1358		if (pin->prio == ZL_DPLL_REF_PRIO_NONE) {
1359			/* Clamp prio to max value & mark pin non-selectable */
1360			pin->prio = ZL_DPLL_REF_PRIO_MAX;
1361			pin->selectable = false;
1362		} else {
1363			/* Mark pin as selectable */
1364			pin->selectable = true;
1365		}
1366	}
1367
1368	/* Create or get existing DPLL pin */
1369	pin->dpll_pin = dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE,
1370				     &props->dpll_props);
1371	if (IS_ERR(pin->dpll_pin)) {
1372		rc = PTR_ERR(pin->dpll_pin);
1373		goto err_pin_get;
1374	}
1375
1376	if (zl3073x_dpll_is_input_pin(pin))
1377		ops = &zl3073x_dpll_input_pin_ops;
1378	else
1379		ops = &zl3073x_dpll_output_pin_ops;
1380
1381	/* Register the pin */
1382	rc = dpll_pin_register(zldpll->dpll_dev, pin->dpll_pin, ops, pin);
1383	if (rc)
1384		goto err_register;
1385
1386	/* Free pin properties */
1387	zl3073x_pin_props_put(props);
1388
1389	return 0;
1390
1391err_register:
1392	dpll_pin_put(pin->dpll_pin);
1393err_prio_get:
1394	pin->dpll_pin = NULL;
1395err_pin_get:
1396	zl3073x_pin_props_put(props);
1397
1398	return rc;
1399}
1400
1401/**
1402 * zl3073x_dpll_pin_unregister - unregister DPLL pin
1403 * @pin: pointer to DPLL pin
1404 *
1405 * Unregisters pin previously registered by @zl3073x_dpll_pin_register.
1406 */
1407static void
1408zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *pin)
1409{
1410	struct zl3073x_dpll *zldpll = pin->dpll;
1411	const struct dpll_pin_ops *ops;
1412
1413	WARN(!pin->dpll_pin, "DPLL pin is not registered\n");
1414
1415	if (zl3073x_dpll_is_input_pin(pin))
1416		ops = &zl3073x_dpll_input_pin_ops;
1417	else
1418		ops = &zl3073x_dpll_output_pin_ops;
1419
1420	/* Unregister the pin */
1421	dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin);
1422
1423	dpll_pin_put(pin->dpll_pin);
1424	pin->dpll_pin = NULL;
1425}
1426
1427/**
1428 * zl3073x_dpll_pins_unregister - unregister all registered DPLL pins
1429 * @zldpll: pointer to zl3073x_dpll structure
1430 *
1431 * Enumerates all DPLL pins registered to given DPLL device and
1432 * unregisters them.
1433 */
1434static void
1435zl3073x_dpll_pins_unregister(struct zl3073x_dpll *zldpll)
1436{
1437	struct zl3073x_dpll_pin *pin, *next;
1438
1439	list_for_each_entry_safe(pin, next, &zldpll->pins, list) {
1440		zl3073x_dpll_pin_unregister(pin);
1441		list_del(&pin->list);
1442		zl3073x_dpll_pin_free(pin);
1443	}
1444}
1445
1446/**
1447 * zl3073x_dpll_pin_is_registrable - check if the pin is registrable
1448 * @zldpll: pointer to zl3073x_dpll structure
1449 * @dir: pin direction
1450 * @index: pin index
1451 *
1452 * Checks if the given pin can be registered to given DPLL. For both
1453 * directions the pin can be registered if it is enabled. In case of
1454 * differential signal type only P-pin is reported as registrable.
1455 * And additionally for the output pin, the pin can be registered only
1456 * if it is connected to synthesizer that is driven by given DPLL.
1457 *
1458 * Return: true if the pin is registrable, false if not
1459 */
1460static bool
1461zl3073x_dpll_pin_is_registrable(struct zl3073x_dpll *zldpll,
1462				enum dpll_pin_direction dir, u8 index)
1463{
1464	struct zl3073x_dev *zldev = zldpll->dev;
1465	bool is_diff, is_enabled;
1466	const char *name;
1467
1468	if (dir == DPLL_PIN_DIRECTION_INPUT) {
1469		u8 ref_id = zl3073x_input_pin_ref_get(index);
1470		const struct zl3073x_ref *ref;
1471
1472		/* Skip the pin if the DPLL is running in NCO mode */
1473		if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_NCO)
1474			return false;
1475
1476		name = "REF";
1477		ref = zl3073x_ref_state_get(zldev, ref_id);
1478		is_diff = zl3073x_ref_is_diff(ref);
1479		is_enabled = zl3073x_ref_is_enabled(ref);
1480	} else {
1481		/* Output P&N pair shares single HW output */
1482		u8 out = zl3073x_output_pin_out_get(index);
1483
1484		/* Skip the pin if it is connected to different DPLL channel */
1485		if (zl3073x_dev_out_dpll_get(zldev, out) != zldpll->id) {
1486			dev_dbg(zldev->dev,
1487				"OUT%u is driven by different DPLL\n", out);
1488
1489			return false;
1490		}
1491
1492		name = "OUT";
1493		is_diff = zl3073x_dev_out_is_diff(zldev, out);
1494		is_enabled = zl3073x_dev_output_pin_is_enabled(zldev, index);
1495	}
1496
1497	/* Skip N-pin if the corresponding input/output is differential */
1498	if (is_diff && zl3073x_is_n_pin(index)) {
1499		dev_dbg(zldev->dev, "%s%u is differential, skipping N-pin\n",
1500			name, index / 2);
1501
1502		return false;
1503	}
1504
1505	/* Skip the pin if it is disabled */
1506	if (!is_enabled) {
1507		dev_dbg(zldev->dev, "%s%u%c is disabled\n", name, index / 2,
1508			zl3073x_is_p_pin(index) ? 'P' : 'N');
1509
1510		return false;
1511	}
1512
1513	return true;
1514}
1515
1516/**
1517 * zl3073x_dpll_pins_register - register all registerable DPLL pins
1518 * @zldpll: pointer to zl3073x_dpll structure
1519 *
1520 * Enumerates all possible input/output pins and registers all of them
1521 * that are registrable.
1522 *
1523 * Return: 0 on success, <0 on error
1524 */
1525static int
1526zl3073x_dpll_pins_register(struct zl3073x_dpll *zldpll)
1527{
1528	struct zl3073x_dpll_pin *pin;
1529	enum dpll_pin_direction dir;
1530	u8 id, index;
1531	int rc;
1532
1533	/* Process input pins */
1534	for (index = 0; index < ZL3073X_NUM_PINS; index++) {
1535		/* First input pins and then output pins */
1536		if (index < ZL3073X_NUM_INPUT_PINS) {
1537			id = index;
1538			dir = DPLL_PIN_DIRECTION_INPUT;
1539		} else {
1540			id = index - ZL3073X_NUM_INPUT_PINS;
1541			dir = DPLL_PIN_DIRECTION_OUTPUT;
1542		}
1543
1544		/* Check if the pin registrable to this DPLL */
1545		if (!zl3073x_dpll_pin_is_registrable(zldpll, dir, id))
1546			continue;
1547
1548		pin = zl3073x_dpll_pin_alloc(zldpll, dir, id);
1549		if (IS_ERR(pin)) {
1550			rc = PTR_ERR(pin);
1551			goto error;
1552		}
1553
1554		rc = zl3073x_dpll_pin_register(pin, index);
1555		if (rc)
1556			goto error;
1557
1558		list_add(&pin->list, &zldpll->pins);
1559	}
1560
1561	return 0;
1562
1563error:
1564	zl3073x_dpll_pins_unregister(zldpll);
1565
1566	return rc;
1567}
1568
1569/**
1570 * zl3073x_dpll_device_register - register DPLL device
1571 * @zldpll: pointer to zl3073x_dpll structure
1572 *
1573 * Registers given DPLL device into DPLL sub-system.
1574 *
1575 * Return: 0 on success, <0 on error
1576 */
1577static int
1578zl3073x_dpll_device_register(struct zl3073x_dpll *zldpll)
1579{
1580	struct zl3073x_dev *zldev = zldpll->dev;
1581	u8 dpll_mode_refsel;
1582	int rc;
1583
1584	/* Read DPLL mode and forcibly selected reference */
1585	rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id),
1586			     &dpll_mode_refsel);
1587	if (rc)
1588		return rc;
1589
1590	/* Extract mode and selected input reference */
1591	zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE,
1592					dpll_mode_refsel);
1593	zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF,
1594				       dpll_mode_refsel);
1595
1596	zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id,
1597					   THIS_MODULE);
1598	if (IS_ERR(zldpll->dpll_dev)) {
1599		rc = PTR_ERR(zldpll->dpll_dev);
1600		zldpll->dpll_dev = NULL;
1601
1602		return rc;
1603	}
1604
1605	rc = dpll_device_register(zldpll->dpll_dev,
1606				  zl3073x_prop_dpll_type_get(zldev, zldpll->id),
1607				  &zl3073x_dpll_device_ops, zldpll);
1608	if (rc) {
1609		dpll_device_put(zldpll->dpll_dev);
1610		zldpll->dpll_dev = NULL;
1611	}
1612
1613	return rc;
1614}
1615
1616/**
1617 * zl3073x_dpll_device_unregister - unregister DPLL device
1618 * @zldpll: pointer to zl3073x_dpll structure
1619 *
1620 * Unregisters given DPLL device from DPLL sub-system previously registered
1621 * by @zl3073x_dpll_device_register.
1622 */
1623static void
1624zl3073x_dpll_device_unregister(struct zl3073x_dpll *zldpll)
1625{
1626	WARN(!zldpll->dpll_dev, "DPLL device is not registered\n");
1627
1628	cancel_work_sync(&zldpll->change_work);
1629
1630	dpll_device_unregister(zldpll->dpll_dev, &zl3073x_dpll_device_ops,
1631			       zldpll);
1632	dpll_device_put(zldpll->dpll_dev);
1633	zldpll->dpll_dev = NULL;
1634}
1635
1636/**
1637 * zl3073x_dpll_pin_phase_offset_check - check for pin phase offset change
1638 * @pin: pin to check
1639 *
1640 * Check for the change of DPLL to connected pin phase offset change.
1641 *
1642 * Return: true on phase offset change, false otherwise
1643 */
1644static bool
1645zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dpll_pin *pin)
1646{
1647	struct zl3073x_dpll *zldpll = pin->dpll;
1648	struct zl3073x_dev *zldev = zldpll->dev;
1649	unsigned int reg;
1650	s64 phase_offset;
1651	u8 ref_id;
1652	int rc;
1653
1654	/* No phase offset if the ref monitor reports signal errors */
1655	ref_id = zl3073x_input_pin_ref_get(pin->id);
1656	if (!zl3073x_dev_ref_is_status_ok(zldev, ref_id))
1657		return false;
1658
1659	/* Select register to read phase offset value depending on pin and
1660	 * phase monitor state:
1661	 * 1) For connected pin use dpll_phase_err_data register
1662	 * 2) For other pins use appropriate ref_phase register if the phase
1663	 *    monitor feature is enabled.
1664	 */
1665	if (pin->pin_state == DPLL_PIN_STATE_CONNECTED)
1666		reg = ZL_REG_DPLL_PHASE_ERR_DATA(zldpll->id);
1667	else if (zldpll->phase_monitor)
1668		reg = ZL_REG_REF_PHASE(ref_id);
1669	else
1670		return false;
1671
1672	/* Read measured phase offset value */
1673	rc = zl3073x_read_u48(zldev, reg, &phase_offset);
1674	if (rc) {
1675		dev_err(zldev->dev, "Failed to read ref phase offset: %pe\n",
1676			ERR_PTR(rc));
1677
1678		return false;
1679	}
1680
1681	/* Convert to ps */
1682	phase_offset = div_s64(sign_extend64(phase_offset, 47), 100);
1683
1684	/* Compare with previous value */
1685	if (phase_offset != pin->phase_offset) {
1686		dev_dbg(zldev->dev, "%s phase offset changed: %lld -> %lld\n",
1687			pin->label, pin->phase_offset, phase_offset);
1688		pin->phase_offset = phase_offset;
1689
1690		return true;
1691	}
1692
1693	return false;
1694}
1695
1696/**
1697 * zl3073x_dpll_pin_ffo_check - check for pin fractional frequency offset change
1698 * @pin: pin to check
1699 *
1700 * Check for the given pin's fractional frequency change.
1701 *
1702 * Return: true on fractional frequency offset change, false otherwise
1703 */
1704static bool
1705zl3073x_dpll_pin_ffo_check(struct zl3073x_dpll_pin *pin)
1706{
1707	struct zl3073x_dpll *zldpll = pin->dpll;
1708	struct zl3073x_dev *zldev = zldpll->dev;
1709	const struct zl3073x_ref *ref;
1710	u8 ref_id;
1711
1712	/* Get reference monitor status */
1713	ref_id = zl3073x_input_pin_ref_get(pin->id);
1714	ref = zl3073x_ref_state_get(zldev, ref_id);
1715
1716	/* Do not report ffo changes if the reference monitor report errors */
1717	if (!zl3073x_ref_is_status_ok(ref))
1718		return false;
1719
1720	/* Compare with previous value */
1721	if (pin->freq_offset != ref->ffo) {
1722		dev_dbg(zldev->dev, "%s freq offset changed: %lld -> %lld\n",
1723			pin->label, pin->freq_offset, ref->ffo);
1724		pin->freq_offset = ref->ffo;
1725
1726		return true;
1727	}
1728
1729	return false;
1730}
1731
1732/**
1733 * zl3073x_dpll_changes_check - check for changes and send notifications
1734 * @zldpll: pointer to zl3073x_dpll structure
1735 *
1736 * Checks for changes on given DPLL device and its registered DPLL pins
1737 * and sends notifications about them.
1738 *
1739 * This function is periodically called from @zl3073x_dev_periodic_work.
1740 */
1741void
1742zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll)
1743{
1744	struct zl3073x_dev *zldev = zldpll->dev;
1745	enum dpll_lock_status lock_status;
1746	struct device *dev = zldev->dev;
1747	struct zl3073x_dpll_pin *pin;
1748	int rc;
1749
1750	zldpll->check_count++;
1751
1752	/* Get current lock status for the DPLL */
1753	rc = zl3073x_dpll_lock_status_get(zldpll->dpll_dev, zldpll,
1754					  &lock_status, NULL, NULL);
1755	if (rc) {
1756		dev_err(dev, "Failed to get DPLL%u lock status: %pe\n",
1757			zldpll->id, ERR_PTR(rc));
1758		return;
1759	}
1760
1761	/* If lock status was changed then notify DPLL core */
1762	if (zldpll->lock_status != lock_status) {
1763		zldpll->lock_status = lock_status;
1764		dpll_device_change_ntf(zldpll->dpll_dev);
1765	}
1766
1767	/* Input pin monitoring does make sense only in automatic
1768	 * or forced reference modes.
1769	 */
1770	if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_AUTO &&
1771	    zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_REFLOCK)
1772		return;
1773
1774	/* Update phase offset latch registers for this DPLL if the phase
1775	 * offset monitor feature is enabled.
1776	 */
1777	if (zldpll->phase_monitor) {
1778		rc = zl3073x_ref_phase_offsets_update(zldev, zldpll->id);
1779		if (rc) {
1780			dev_err(zldev->dev,
1781				"Failed to update phase offsets: %pe\n",
1782				ERR_PTR(rc));
1783			return;
1784		}
1785	}
1786
1787	list_for_each_entry(pin, &zldpll->pins, list) {
1788		enum dpll_pin_state state;
1789		bool pin_changed = false;
1790
1791		/* Output pins change checks are not necessary because output
1792		 * states are constant.
1793		 */
1794		if (!zl3073x_dpll_is_input_pin(pin))
1795			continue;
1796
1797		rc = zl3073x_dpll_ref_state_get(pin, &state);
1798		if (rc) {
1799			dev_err(dev,
1800				"Failed to get %s on DPLL%u state: %pe\n",
1801				pin->label, zldpll->id, ERR_PTR(rc));
1802			return;
1803		}
1804
1805		if (state != pin->pin_state) {
1806			dev_dbg(dev, "%s state changed: %u->%u\n", pin->label,
1807				pin->pin_state, state);
1808			pin->pin_state = state;
1809			pin_changed = true;
1810		}
1811
1812		/* Check for phase offset and ffo change once per second */
1813		if (zldpll->check_count % 2 == 0) {
1814			if (zl3073x_dpll_pin_phase_offset_check(pin))
1815				pin_changed = true;
1816
1817			if (zl3073x_dpll_pin_ffo_check(pin))
1818				pin_changed = true;
1819		}
1820
1821		if (pin_changed)
1822			dpll_pin_change_ntf(pin->dpll_pin);
1823	}
1824}
1825
1826/**
1827 * zl3073x_dpll_init_fine_phase_adjust - do initial fine phase adjustments
1828 * @zldev: pointer to zl3073x device
1829 *
1830 * Performs initial fine phase adjustments needed per datasheet.
1831 *
1832 * Return: 0 on success, <0 on error
1833 */
1834int
1835zl3073x_dpll_init_fine_phase_adjust(struct zl3073x_dev *zldev)
1836{
1837	int rc;
1838
1839	rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_MASK, 0x1f);
1840	if (rc)
1841		return rc;
1842
1843	rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_INTVL, 0x01);
1844	if (rc)
1845		return rc;
1846
1847	rc = zl3073x_write_u16(zldev, ZL_REG_SYNTH_PHASE_SHIFT_DATA, 0xffff);
1848	if (rc)
1849		return rc;
1850
1851	rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_CTRL, 0x01);
1852	if (rc)
1853		return rc;
1854
1855	return rc;
1856}
1857
1858/**
1859 * zl3073x_dpll_alloc - allocate DPLL device
1860 * @zldev: pointer to zl3073x device
1861 * @ch: DPLL channel number
1862 *
1863 * Allocates DPLL device structure for given DPLL channel.
1864 *
1865 * Return: pointer to DPLL device on success, error pointer on error
1866 */
1867struct zl3073x_dpll *
1868zl3073x_dpll_alloc(struct zl3073x_dev *zldev, u8 ch)
1869{
1870	struct zl3073x_dpll *zldpll;
1871
1872	zldpll = kzalloc(sizeof(*zldpll), GFP_KERNEL);
1873	if (!zldpll)
1874		return ERR_PTR(-ENOMEM);
1875
1876	zldpll->dev = zldev;
1877	zldpll->id = ch;
1878	INIT_LIST_HEAD(&zldpll->pins);
1879	INIT_WORK(&zldpll->change_work, zl3073x_dpll_change_work);
1880
1881	return zldpll;
1882}
1883
1884/**
1885 * zl3073x_dpll_free - free DPLL device
1886 * @zldpll: pointer to zl3073x_dpll structure
1887 *
1888 * Deallocates given DPLL device previously allocated by @zl3073x_dpll_alloc.
1889 */
1890void
1891zl3073x_dpll_free(struct zl3073x_dpll *zldpll)
1892{
1893	WARN(zldpll->dpll_dev, "DPLL device is still registered\n");
1894
1895	kfree(zldpll);
1896}
1897
1898/**
1899 * zl3073x_dpll_register - register DPLL device and all its pins
1900 * @zldpll: pointer to zl3073x_dpll structure
1901 *
1902 * Registers given DPLL device and all its pins into DPLL sub-system.
1903 *
1904 * Return: 0 on success, <0 on error
1905 */
1906int
1907zl3073x_dpll_register(struct zl3073x_dpll *zldpll)
1908{
1909	int rc;
1910
1911	rc = zl3073x_dpll_device_register(zldpll);
1912	if (rc)
1913		return rc;
1914
1915	rc = zl3073x_dpll_pins_register(zldpll);
1916	if (rc) {
1917		zl3073x_dpll_device_unregister(zldpll);
1918		return rc;
1919	}
1920
1921	return 0;
1922}
1923
1924/**
1925 * zl3073x_dpll_unregister - unregister DPLL device and its pins
1926 * @zldpll: pointer to zl3073x_dpll structure
1927 *
1928 * Unregisters given DPLL device and all its pins from DPLL sub-system
1929 * previously registered by @zl3073x_dpll_register.
1930 */
1931void
1932zl3073x_dpll_unregister(struct zl3073x_dpll *zldpll)
1933{
1934	/* Unregister all pins and dpll */
1935	zl3073x_dpll_pins_unregister(zldpll);
1936	zl3073x_dpll_device_unregister(zldpll);
1937}