core.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2
   3#include <linux/array_size.h>
   4#include <linux/bitfield.h>
   5#include <linux/bits.h>
   6#include <linux/dev_printk.h>
   7#include <linux/device.h>
   8#include <linux/export.h>
   9#include <linux/math64.h>
  10#include <linux/module.h>
  11#include <linux/netlink.h>
  12#include <linux/regmap.h>
  13#include <linux/sprintf.h>
  14#include <linux/string_choices.h>
  15#include <linux/unaligned.h>
  16#include <net/devlink.h>
  17
  18#include "core.h"
  19#include "devlink.h"
  20#include "dpll.h"
  21#include "regs.h"
  22
  23/* Chip IDs for zl30731 */
  24static const u16 zl30731_ids[] = {
  25	0x0E93,
  26	0x1E93,
  27	0x2E93,
  28};
  29
  30const struct zl3073x_chip_info zl30731_chip_info = {
  31	.ids = zl30731_ids,
  32	.num_ids = ARRAY_SIZE(zl30731_ids),
  33	.num_channels = 1,
  34};
  35EXPORT_SYMBOL_NS_GPL(zl30731_chip_info, "ZL3073X");
  36
  37/* Chip IDs for zl30732 */
  38static const u16 zl30732_ids[] = {
  39	0x0E30,
  40	0x0E94,
  41	0x1E94,
  42	0x1F60,
  43	0x2E94,
  44	0x3FC4,
  45};
  46
  47const struct zl3073x_chip_info zl30732_chip_info = {
  48	.ids = zl30732_ids,
  49	.num_ids = ARRAY_SIZE(zl30732_ids),
  50	.num_channels = 2,
  51};
  52EXPORT_SYMBOL_NS_GPL(zl30732_chip_info, "ZL3073X");
  53
  54/* Chip IDs for zl30733 */
  55static const u16 zl30733_ids[] = {
  56	0x0E95,
  57	0x1E95,
  58	0x2E95,
  59};
  60
  61const struct zl3073x_chip_info zl30733_chip_info = {
  62	.ids = zl30733_ids,
  63	.num_ids = ARRAY_SIZE(zl30733_ids),
  64	.num_channels = 3,
  65};
  66EXPORT_SYMBOL_NS_GPL(zl30733_chip_info, "ZL3073X");
  67
  68/* Chip IDs for zl30734 */
  69static const u16 zl30734_ids[] = {
  70	0x0E96,
  71	0x1E96,
  72	0x2E96,
  73};
  74
  75const struct zl3073x_chip_info zl30734_chip_info = {
  76	.ids = zl30734_ids,
  77	.num_ids = ARRAY_SIZE(zl30734_ids),
  78	.num_channels = 4,
  79};
  80EXPORT_SYMBOL_NS_GPL(zl30734_chip_info, "ZL3073X");
  81
  82/* Chip IDs for zl30735 */
  83static const u16 zl30735_ids[] = {
  84	0x0E97,
  85	0x1E97,
  86	0x2E97,
  87};
  88
  89const struct zl3073x_chip_info zl30735_chip_info = {
  90	.ids = zl30735_ids,
  91	.num_ids = ARRAY_SIZE(zl30735_ids),
  92	.num_channels = 5,
  93};
  94EXPORT_SYMBOL_NS_GPL(zl30735_chip_info, "ZL3073X");
  95
  96#define ZL_RANGE_OFFSET		0x80
  97#define ZL_PAGE_SIZE		0x80
  98#define ZL_NUM_PAGES		256
  99#define ZL_PAGE_SEL		0x7F
 100#define ZL_PAGE_SEL_MASK	GENMASK(7, 0)
 101#define ZL_NUM_REGS		(ZL_NUM_PAGES * ZL_PAGE_SIZE)
 102
 103/* Regmap range configuration */
 104static const struct regmap_range_cfg zl3073x_regmap_range = {
 105	.range_min	= ZL_RANGE_OFFSET,
 106	.range_max	= ZL_RANGE_OFFSET + ZL_NUM_REGS - 1,
 107	.selector_reg	= ZL_PAGE_SEL,
 108	.selector_mask	= ZL_PAGE_SEL_MASK,
 109	.selector_shift	= 0,
 110	.window_start	= 0,
 111	.window_len	= ZL_PAGE_SIZE,
 112};
 113
 114static bool
 115zl3073x_is_volatile_reg(struct device *dev __maybe_unused, unsigned int reg)
 116{
 117	/* Only page selector is non-volatile */
 118	return reg != ZL_PAGE_SEL;
 119}
 120
 121const struct regmap_config zl3073x_regmap_config = {
 122	.reg_bits	= 8,
 123	.val_bits	= 8,
 124	.max_register	= ZL_RANGE_OFFSET + ZL_NUM_REGS - 1,
 125	.ranges		= &zl3073x_regmap_range,
 126	.num_ranges	= 1,
 127	.cache_type	= REGCACHE_MAPLE,
 128	.volatile_reg	= zl3073x_is_volatile_reg,
 129};
 130EXPORT_SYMBOL_NS_GPL(zl3073x_regmap_config, "ZL3073X");
 131
 132static bool
 133zl3073x_check_reg(struct zl3073x_dev *zldev, unsigned int reg, size_t size)
 134{
 135	/* Check that multiop lock is held when accessing registers
 136	 * from page 10 and above except the page 255 that does not
 137	 * need this protection.
 138	 */
 139	if (ZL_REG_PAGE(reg) >= 10 && ZL_REG_PAGE(reg) < 255)
 140		lockdep_assert_held(&zldev->multiop_lock);
 141
 142	/* Check the index is in valid range for indexed register */
 143	if (ZL_REG_OFFSET(reg) > ZL_REG_MAX_OFFSET(reg)) {
 144		dev_err(zldev->dev, "Index out of range for reg 0x%04lx\n",
 145			ZL_REG_ADDR(reg));
 146		return false;
 147	}
 148	/* Check the requested size corresponds to register size */
 149	if (ZL_REG_SIZE(reg) != size) {
 150		dev_err(zldev->dev, "Invalid size %zu for reg 0x%04lx\n",
 151			size, ZL_REG_ADDR(reg));
 152		return false;
 153	}
 154
 155	return true;
 156}
 157
 158static int
 159zl3073x_read_reg(struct zl3073x_dev *zldev, unsigned int reg, void *val,
 160		 size_t size)
 161{
 162	int rc;
 163
 164	if (!zl3073x_check_reg(zldev, reg, size))
 165		return -EINVAL;
 166
 167	/* Map the register address to virtual range */
 168	reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET;
 169
 170	rc = regmap_bulk_read(zldev->regmap, reg, val, size);
 171	if (rc) {
 172		dev_err(zldev->dev, "Failed to read reg 0x%04x: %pe\n", reg,
 173			ERR_PTR(rc));
 174		return rc;
 175	}
 176
 177	return 0;
 178}
 179
 180static int
 181zl3073x_write_reg(struct zl3073x_dev *zldev, unsigned int reg, const void *val,
 182		  size_t size)
 183{
 184	int rc;
 185
 186	if (!zl3073x_check_reg(zldev, reg, size))
 187		return -EINVAL;
 188
 189	/* Map the register address to virtual range */
 190	reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET;
 191
 192	rc = regmap_bulk_write(zldev->regmap, reg, val, size);
 193	if (rc) {
 194		dev_err(zldev->dev, "Failed to write reg 0x%04x: %pe\n", reg,
 195			ERR_PTR(rc));
 196		return rc;
 197	}
 198
 199	return 0;
 200}
 201
 202/**
 203 * zl3073x_read_u8 - read value from 8bit register
 204 * @zldev: zl3073x device pointer
 205 * @reg: register to write to
 206 * @val: value to write
 207 *
 208 * Reads value from given 8bit register.
 209 *
 210 * Returns: 0 on success, <0 on error
 211 */
 212int zl3073x_read_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 *val)
 213{
 214	return zl3073x_read_reg(zldev, reg, val, sizeof(*val));
 215}
 216
 217/**
 218 * zl3073x_write_u8 - write value to 16bit register
 219 * @zldev: zl3073x device pointer
 220 * @reg: register to write to
 221 * @val: value to write
 222 *
 223 * Writes value into given 8bit register.
 224 *
 225 * Returns: 0 on success, <0 on error
 226 */
 227int zl3073x_write_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 val)
 228{
 229	return zl3073x_write_reg(zldev, reg, &val, sizeof(val));
 230}
 231
 232/**
 233 * zl3073x_read_u16 - read value from 16bit register
 234 * @zldev: zl3073x device pointer
 235 * @reg: register to write to
 236 * @val: value to write
 237 *
 238 * Reads value from given 16bit register.
 239 *
 240 * Returns: 0 on success, <0 on error
 241 */
 242int zl3073x_read_u16(struct zl3073x_dev *zldev, unsigned int reg, u16 *val)
 243{
 244	int rc;
 245
 246	rc = zl3073x_read_reg(zldev, reg, val, sizeof(*val));
 247	if (!rc)
 248		be16_to_cpus(val);
 249
 250	return rc;
 251}
 252
 253/**
 254 * zl3073x_write_u16 - write value to 16bit register
 255 * @zldev: zl3073x device pointer
 256 * @reg: register to write to
 257 * @val: value to write
 258 *
 259 * Writes value into given 16bit register.
 260 *
 261 * Returns: 0 on success, <0 on error
 262 */
 263int zl3073x_write_u16(struct zl3073x_dev *zldev, unsigned int reg, u16 val)
 264{
 265	cpu_to_be16s(&val);
 266
 267	return zl3073x_write_reg(zldev, reg, &val, sizeof(val));
 268}
 269
 270/**
 271 * zl3073x_read_u32 - read value from 32bit register
 272 * @zldev: zl3073x device pointer
 273 * @reg: register to write to
 274 * @val: value to write
 275 *
 276 * Reads value from given 32bit register.
 277 *
 278 * Returns: 0 on success, <0 on error
 279 */
 280int zl3073x_read_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 *val)
 281{
 282	int rc;
 283
 284	rc = zl3073x_read_reg(zldev, reg, val, sizeof(*val));
 285	if (!rc)
 286		be32_to_cpus(val);
 287
 288	return rc;
 289}
 290
 291/**
 292 * zl3073x_write_u32 - write value to 32bit register
 293 * @zldev: zl3073x device pointer
 294 * @reg: register to write to
 295 * @val: value to write
 296 *
 297 * Writes value into given 32bit register.
 298 *
 299 * Returns: 0 on success, <0 on error
 300 */
 301int zl3073x_write_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 val)
 302{
 303	cpu_to_be32s(&val);
 304
 305	return zl3073x_write_reg(zldev, reg, &val, sizeof(val));
 306}
 307
 308/**
 309 * zl3073x_read_u48 - read value from 48bit register
 310 * @zldev: zl3073x device pointer
 311 * @reg: register to write to
 312 * @val: value to write
 313 *
 314 * Reads value from given 48bit register.
 315 *
 316 * Returns: 0 on success, <0 on error
 317 */
 318int zl3073x_read_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 *val)
 319{
 320	u8 buf[6];
 321	int rc;
 322
 323	rc = zl3073x_read_reg(zldev, reg, buf, sizeof(buf));
 324	if (!rc)
 325		*val = get_unaligned_be48(buf);
 326
 327	return rc;
 328}
 329
 330/**
 331 * zl3073x_write_u48 - write value to 48bit register
 332 * @zldev: zl3073x device pointer
 333 * @reg: register to write to
 334 * @val: value to write
 335 *
 336 * Writes value into given 48bit register.
 337 * The value must be from the interval -S48_MIN to U48_MAX.
 338 *
 339 * Returns: 0 on success, <0 on error
 340 */
 341int zl3073x_write_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 val)
 342{
 343	u8 buf[6];
 344
 345	/* Check the value belongs to <S48_MIN, U48_MAX>
 346	 * Any value >= S48_MIN has bits 47..63 set.
 347	 */
 348	if (val > GENMASK_ULL(47, 0) && val < GENMASK_ULL(63, 47)) {
 349		dev_err(zldev->dev, "Value 0x%0llx out of range\n", val);
 350		return -EINVAL;
 351	}
 352
 353	put_unaligned_be48(val, buf);
 354
 355	return zl3073x_write_reg(zldev, reg, buf, sizeof(buf));
 356}
 357
 358/**
 359 * zl3073x_poll_zero_u8 - wait for register to be cleared by device
 360 * @zldev: zl3073x device pointer
 361 * @reg: register to poll (has to be 8bit register)
 362 * @mask: bit mask for polling
 363 *
 364 * Waits for bits specified by @mask in register @reg value to be cleared
 365 * by the device.
 366 *
 367 * Returns: 0 on success, <0 on error
 368 */
 369int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 mask)
 370{
 371	/* Register polling sleep & timeout */
 372#define ZL_POLL_SLEEP_US   10
 373#define ZL_POLL_TIMEOUT_US 2000000
 374	unsigned int val;
 375
 376	/* Check the register is 8bit */
 377	if (ZL_REG_SIZE(reg) != 1) {
 378		dev_err(zldev->dev, "Invalid reg 0x%04lx size for polling\n",
 379			ZL_REG_ADDR(reg));
 380		return -EINVAL;
 381	}
 382
 383	/* Map the register address to virtual range */
 384	reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET;
 385
 386	return regmap_read_poll_timeout(zldev->regmap, reg, val, !(val & mask),
 387					ZL_POLL_SLEEP_US, ZL_POLL_TIMEOUT_US);
 388}
 389
 390int zl3073x_mb_op(struct zl3073x_dev *zldev, unsigned int op_reg, u8 op_val,
 391		  unsigned int mask_reg, u16 mask_val)
 392{
 393	int rc;
 394
 395	/* Set mask for the operation */
 396	rc = zl3073x_write_u16(zldev, mask_reg, mask_val);
 397	if (rc)
 398		return rc;
 399
 400	/* Trigger the operation */
 401	rc = zl3073x_write_u8(zldev, op_reg, op_val);
 402	if (rc)
 403		return rc;
 404
 405	/* Wait for the operation to actually finish */
 406	return zl3073x_poll_zero_u8(zldev, op_reg, op_val);
 407}
 408
 409/**
 410 * zl3073x_do_hwreg_op - Perform HW register read/write operation
 411 * @zldev: zl3073x device pointer
 412 * @op: operation to perform
 413 *
 414 * Performs requested operation and waits for its completion.
 415 *
 416 * Return: 0 on success, <0 on error
 417 */
 418static int
 419zl3073x_do_hwreg_op(struct zl3073x_dev *zldev, u8 op)
 420{
 421	int rc;
 422
 423	/* Set requested operation and set pending bit */
 424	rc = zl3073x_write_u8(zldev, ZL_REG_HWREG_OP, op | ZL_HWREG_OP_PENDING);
 425	if (rc)
 426		return rc;
 427
 428	/* Poll for completion - pending bit cleared */
 429	return zl3073x_poll_zero_u8(zldev, ZL_REG_HWREG_OP,
 430				    ZL_HWREG_OP_PENDING);
 431}
 432
 433/**
 434 * zl3073x_read_hwreg - Read HW register
 435 * @zldev: zl3073x device pointer
 436 * @addr: HW register address
 437 * @value: Value of the HW register
 438 *
 439 * Reads HW register value and stores it into @value.
 440 *
 441 * Return: 0 on success, <0 on error
 442 */
 443int zl3073x_read_hwreg(struct zl3073x_dev *zldev, u32 addr, u32 *value)
 444{
 445	int rc;
 446
 447	/* Set address to read data from */
 448	rc = zl3073x_write_u32(zldev, ZL_REG_HWREG_ADDR, addr);
 449	if (rc)
 450		return rc;
 451
 452	/* Perform the read operation */
 453	rc = zl3073x_do_hwreg_op(zldev, ZL_HWREG_OP_READ);
 454	if (rc)
 455		return rc;
 456
 457	/* Read the received data */
 458	return zl3073x_read_u32(zldev, ZL_REG_HWREG_READ_DATA, value);
 459}
 460
 461/**
 462 * zl3073x_write_hwreg - Write value to HW register
 463 * @zldev: zl3073x device pointer
 464 * @addr: HW registers address
 465 * @value: Value to be written to HW register
 466 *
 467 * Stores the requested value into HW register.
 468 *
 469 * Return: 0 on success, <0 on error
 470 */
 471int zl3073x_write_hwreg(struct zl3073x_dev *zldev, u32 addr, u32 value)
 472{
 473	int rc;
 474
 475	/* Set address to write data to */
 476	rc = zl3073x_write_u32(zldev, ZL_REG_HWREG_ADDR, addr);
 477	if (rc)
 478		return rc;
 479
 480	/* Set data to be written */
 481	rc = zl3073x_write_u32(zldev, ZL_REG_HWREG_WRITE_DATA, value);
 482	if (rc)
 483		return rc;
 484
 485	/* Perform the write operation */
 486	return zl3073x_do_hwreg_op(zldev, ZL_HWREG_OP_WRITE);
 487}
 488
 489/**
 490 * zl3073x_update_hwreg - Update certain bits in HW register
 491 * @zldev: zl3073x device pointer
 492 * @addr: HW register address
 493 * @value: Value to be written into HW register
 494 * @mask: Bitmask indicating bits to be updated
 495 *
 496 * Reads given HW register, updates requested bits specified by value and
 497 * mask and writes result back to HW register.
 498 *
 499 * Return: 0 on success, <0 on error
 500 */
 501int zl3073x_update_hwreg(struct zl3073x_dev *zldev, u32 addr, u32 value,
 502			 u32 mask)
 503{
 504	u32 tmp;
 505	int rc;
 506
 507	rc = zl3073x_read_hwreg(zldev, addr, &tmp);
 508	if (rc)
 509		return rc;
 510
 511	tmp &= ~mask;
 512	tmp |= value & mask;
 513
 514	return zl3073x_write_hwreg(zldev, addr, tmp);
 515}
 516
 517/**
 518 * zl3073x_write_hwreg_seq - Write HW registers sequence
 519 * @zldev: pointer to device structure
 520 * @seq: pointer to first sequence item
 521 * @num_items: number of items in sequence
 522 *
 523 * Writes given HW registers sequence.
 524 *
 525 * Return: 0 on success, <0 on error
 526 */
 527int zl3073x_write_hwreg_seq(struct zl3073x_dev *zldev,
 528			    const struct zl3073x_hwreg_seq_item *seq,
 529			    size_t num_items)
 530{
 531	int i, rc = 0;
 532
 533	for (i = 0; i < num_items; i++) {
 534		dev_dbg(zldev->dev, "Write 0x%0x [0x%0x] to 0x%0x",
 535			seq[i].value, seq[i].mask, seq[i].addr);
 536
 537		if (seq[i].mask == U32_MAX)
 538			/* Write value directly */
 539			rc = zl3073x_write_hwreg(zldev, seq[i].addr,
 540						 seq[i].value);
 541		else
 542			/* Update only bits specified by the mask */
 543			rc = zl3073x_update_hwreg(zldev, seq[i].addr,
 544						  seq[i].value, seq[i].mask);
 545		if (rc)
 546			return rc;
 547
 548		if (seq->wait)
 549			msleep(seq->wait);
 550	}
 551
 552	return rc;
 553}
 554
 555static int
 556zl3073x_dev_state_fetch(struct zl3073x_dev *zldev)
 557{
 558	int rc;
 559	u8 i;
 560
 561	for (i = 0; i < ZL3073X_NUM_REFS; i++) {
 562		rc = zl3073x_ref_state_fetch(zldev, i);
 563		if (rc) {
 564			dev_err(zldev->dev,
 565				"Failed to fetch input state: %pe\n",
 566				ERR_PTR(rc));
 567			return rc;
 568		}
 569	}
 570
 571	for (i = 0; i < ZL3073X_NUM_SYNTHS; i++) {
 572		rc = zl3073x_synth_state_fetch(zldev, i);
 573		if (rc) {
 574			dev_err(zldev->dev,
 575				"Failed to fetch synth state: %pe\n",
 576				ERR_PTR(rc));
 577			return rc;
 578		}
 579	}
 580
 581	for (i = 0; i < ZL3073X_NUM_OUTS; i++) {
 582		rc = zl3073x_out_state_fetch(zldev, i);
 583		if (rc) {
 584			dev_err(zldev->dev,
 585				"Failed to fetch output state: %pe\n",
 586				ERR_PTR(rc));
 587			return rc;
 588		}
 589	}
 590
 591	return rc;
 592}
 593
 594static void
 595zl3073x_dev_ref_status_update(struct zl3073x_dev *zldev)
 596{
 597	int i, rc;
 598
 599	for (i = 0; i < ZL3073X_NUM_REFS; i++) {
 600		rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(i),
 601				     &zldev->ref[i].mon_status);
 602		if (rc)
 603			dev_warn(zldev->dev,
 604				 "Failed to get REF%u status: %pe\n", i,
 605				 ERR_PTR(rc));
 606	}
 607}
 608
 609/**
 610 * zl3073x_ref_phase_offsets_update - update reference phase offsets
 611 * @zldev: pointer to zl3073x_dev structure
 612 * @channel: DPLL channel number or -1
 613 *
 614 * The function asks device to update phase offsets latch registers with
 615 * the latest measured values. There are 2 sets of latch registers:
 616 *
 617 * 1) Up to 5 DPLL-to-connected-ref registers that contain phase offset
 618 *    values between particular DPLL channel and its *connected* input
 619 *    reference.
 620 *
 621 * 2) 10 selected-DPLL-to-all-ref registers that contain phase offset values
 622 *    between selected DPLL channel and all input references.
 623 *
 624 * If the caller is interested in 2) then it has to pass DPLL channel number
 625 * in @channel parameter. If it is interested only in 1) then it should pass
 626 * @channel parameter with value of -1.
 627 *
 628 * Return: 0 on success, <0 on error
 629 */
 630int zl3073x_ref_phase_offsets_update(struct zl3073x_dev *zldev, int channel)
 631{
 632	int rc;
 633
 634	/* Per datasheet we have to wait for 'dpll_ref_phase_err_rqst_rd'
 635	 * to be zero to ensure that the measured data are coherent.
 636	 */
 637	rc = zl3073x_poll_zero_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST,
 638				  ZL_REF_PHASE_ERR_READ_RQST_RD);
 639	if (rc)
 640		return rc;
 641
 642	/* Select DPLL channel if it is specified */
 643	if (channel != -1) {
 644		rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_IDX, channel);
 645		if (rc)
 646			return rc;
 647	}
 648
 649	/* Request to update phase offsets measurement values */
 650	rc = zl3073x_write_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST,
 651			      ZL_REF_PHASE_ERR_READ_RQST_RD);
 652	if (rc)
 653		return rc;
 654
 655	/* Wait for finish */
 656	return zl3073x_poll_zero_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST,
 657				    ZL_REF_PHASE_ERR_READ_RQST_RD);
 658}
 659
 660/**
 661 * zl3073x_ref_ffo_update - update reference fractional frequency offsets
 662 * @zldev: pointer to zl3073x_dev structure
 663 *
 664 * The function asks device to update fractional frequency offsets latch
 665 * registers the latest measured values, reads and stores them into
 666 *
 667 * Return: 0 on success, <0 on error
 668 */
 669static int
 670zl3073x_ref_ffo_update(struct zl3073x_dev *zldev)
 671{
 672	int i, rc;
 673
 674	/* Per datasheet we have to wait for 'ref_freq_meas_ctrl' to be zero
 675	 * to ensure that the measured data are coherent.
 676	 */
 677	rc = zl3073x_poll_zero_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL,
 678				  ZL_REF_FREQ_MEAS_CTRL);
 679	if (rc)
 680		return rc;
 681
 682	/* Select all references for measurement */
 683	rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_3_0,
 684			      GENMASK(7, 0)); /* REF0P..REF3N */
 685	if (rc)
 686		return rc;
 687	rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_4,
 688			      GENMASK(1, 0)); /* REF4P..REF4N */
 689	if (rc)
 690		return rc;
 691
 692	/* Request frequency offset measurement */
 693	rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL,
 694			      ZL_REF_FREQ_MEAS_CTRL_REF_FREQ_OFF);
 695	if (rc)
 696		return rc;
 697
 698	/* Wait for finish */
 699	rc = zl3073x_poll_zero_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL,
 700				  ZL_REF_FREQ_MEAS_CTRL);
 701	if (rc)
 702		return rc;
 703
 704	/* Read DPLL-to-REFx frequency offset measurements */
 705	for (i = 0; i < ZL3073X_NUM_REFS; i++) {
 706		s32 value;
 707
 708		/* Read value stored in units of 2^-32 signed */
 709		rc = zl3073x_read_u32(zldev, ZL_REG_REF_FREQ(i), &value);
 710		if (rc)
 711			return rc;
 712
 713		/* Convert to ppm -> ffo = (10^6 * value) / 2^32 */
 714		zldev->ref[i].ffo = mul_s64_u64_shr(value, 1000000, 32);
 715	}
 716
 717	return 0;
 718}
 719
 720static void
 721zl3073x_dev_periodic_work(struct kthread_work *work)
 722{
 723	struct zl3073x_dev *zldev = container_of(work, struct zl3073x_dev,
 724						 work.work);
 725	struct zl3073x_dpll *zldpll;
 726	int rc;
 727
 728	/* Update input references status */
 729	zl3073x_dev_ref_status_update(zldev);
 730
 731	/* Update DPLL-to-connected-ref phase offsets registers */
 732	rc = zl3073x_ref_phase_offsets_update(zldev, -1);
 733	if (rc)
 734		dev_warn(zldev->dev, "Failed to update phase offsets: %pe\n",
 735			 ERR_PTR(rc));
 736
 737	/* Update references' fractional frequency offsets */
 738	rc = zl3073x_ref_ffo_update(zldev);
 739	if (rc)
 740		dev_warn(zldev->dev,
 741			 "Failed to update fractional frequency offsets: %pe\n",
 742			 ERR_PTR(rc));
 743
 744	list_for_each_entry(zldpll, &zldev->dplls, list)
 745		zl3073x_dpll_changes_check(zldpll);
 746
 747	/* Run twice a second */
 748	kthread_queue_delayed_work(zldev->kworker, &zldev->work,
 749				   msecs_to_jiffies(500));
 750}
 751
 752int zl3073x_dev_phase_avg_factor_set(struct zl3073x_dev *zldev, u8 factor)
 753{
 754	u8 dpll_meas_ctrl, value;
 755	int rc;
 756
 757	/* Read DPLL phase measurement control register */
 758	rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, &dpll_meas_ctrl);
 759	if (rc)
 760		return rc;
 761
 762	/* Convert requested factor to register value */
 763	value = (factor + 1) & 0x0f;
 764
 765	/* Update phase measurement control register */
 766	dpll_meas_ctrl &= ~ZL_DPLL_MEAS_CTRL_AVG_FACTOR;
 767	dpll_meas_ctrl |= FIELD_PREP(ZL_DPLL_MEAS_CTRL_AVG_FACTOR, value);
 768	rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl);
 769	if (rc)
 770		return rc;
 771
 772	/* Save the new factor */
 773	zldev->phase_avg_factor = factor;
 774
 775	return 0;
 776}
 777
 778/**
 779 * zl3073x_dev_phase_meas_setup - setup phase offset measurement
 780 * @zldev: pointer to zl3073x_dev structure
 781 *
 782 * Enable phase offset measurement block, set measurement averaging factor
 783 * and enable DPLL-to-its-ref phase measurement for all DPLLs.
 784 *
 785 * Returns: 0 on success, <0 on error
 786 */
 787static int
 788zl3073x_dev_phase_meas_setup(struct zl3073x_dev *zldev)
 789{
 790	struct zl3073x_dpll *zldpll;
 791	u8 dpll_meas_ctrl, mask = 0;
 792	int rc;
 793
 794	/* Setup phase measurement averaging factor */
 795	rc = zl3073x_dev_phase_avg_factor_set(zldev, zldev->phase_avg_factor);
 796	if (rc)
 797		return rc;
 798
 799	/* Read DPLL phase measurement control register */
 800	rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, &dpll_meas_ctrl);
 801	if (rc)
 802		return rc;
 803
 804	/* Enable DPLL measurement block */
 805	dpll_meas_ctrl |= ZL_DPLL_MEAS_CTRL_EN;
 806
 807	/* Update phase measurement control register */
 808	rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl);
 809	if (rc)
 810		return rc;
 811
 812	/* Enable DPLL-to-connected-ref measurement for each channel */
 813	list_for_each_entry(zldpll, &zldev->dplls, list)
 814		mask |= BIT(zldpll->id);
 815
 816	return zl3073x_write_u8(zldev, ZL_REG_DPLL_PHASE_ERR_READ_MASK, mask);
 817}
 818
 819/**
 820 * zl3073x_dev_start - Start normal operation
 821 * @zldev: zl3073x device pointer
 822 * @full: perform full initialization
 823 *
 824 * The function starts normal operation, which means registering all DPLLs and
 825 * their pins, and starting monitoring. If full initialization is requested,
 826 * the function additionally initializes the phase offset measurement block and
 827 * fetches hardware-invariant parameters.
 828 *
 829 * Return: 0 on success, <0 on error
 830 */
 831int zl3073x_dev_start(struct zl3073x_dev *zldev, bool full)
 832{
 833	struct zl3073x_dpll *zldpll;
 834	u8 info;
 835	int rc;
 836
 837	rc = zl3073x_read_u8(zldev, ZL_REG_INFO, &info);
 838	if (rc) {
 839		dev_err(zldev->dev, "Failed to read device status info\n");
 840		return rc;
 841	}
 842
 843	if (!FIELD_GET(ZL_INFO_READY, info)) {
 844		/* The ready bit indicates that the firmware was successfully
 845		 * configured and is ready for normal operation. If it is
 846		 * cleared then the configuration stored in flash is wrong
 847		 * or missing. In this situation the driver will expose
 848		 * only devlink interface to give an opportunity to flash
 849		 * the correct config.
 850		 */
 851		dev_info(zldev->dev,
 852			 "FW not fully ready - missing or corrupted config\n");
 853
 854		return 0;
 855	}
 856
 857	if (full) {
 858		/* Fetch device state */
 859		rc = zl3073x_dev_state_fetch(zldev);
 860		if (rc)
 861			return rc;
 862
 863		/* Setup phase offset measurement block */
 864		rc = zl3073x_dev_phase_meas_setup(zldev);
 865		if (rc) {
 866			dev_err(zldev->dev,
 867				"Failed to setup phase measurement\n");
 868			return rc;
 869		}
 870	}
 871
 872	/* Register all DPLLs */
 873	list_for_each_entry(zldpll, &zldev->dplls, list) {
 874		rc = zl3073x_dpll_register(zldpll);
 875		if (rc) {
 876			dev_err_probe(zldev->dev, rc,
 877				      "Failed to register DPLL%u\n",
 878				      zldpll->id);
 879			return rc;
 880		}
 881	}
 882
 883	/* Perform initial firmware fine phase correction */
 884	rc = zl3073x_dpll_init_fine_phase_adjust(zldev);
 885	if (rc) {
 886		dev_err_probe(zldev->dev, rc,
 887			      "Failed to init fine phase correction\n");
 888		return rc;
 889	}
 890
 891	/* Start monitoring */
 892	kthread_queue_delayed_work(zldev->kworker, &zldev->work, 0);
 893
 894	return 0;
 895}
 896
 897/**
 898 * zl3073x_dev_stop - Stop normal operation
 899 * @zldev: zl3073x device pointer
 900 *
 901 * The function stops the normal operation that mean deregistration of all
 902 * DPLLs and their pins and stop monitoring.
 903 *
 904 * Return: 0 on success, <0 on error
 905 */
 906void zl3073x_dev_stop(struct zl3073x_dev *zldev)
 907{
 908	struct zl3073x_dpll *zldpll;
 909
 910	/* Stop monitoring */
 911	kthread_cancel_delayed_work_sync(&zldev->work);
 912
 913	/* Unregister all DPLLs */
 914	list_for_each_entry(zldpll, &zldev->dplls, list) {
 915		if (zldpll->dpll_dev)
 916			zl3073x_dpll_unregister(zldpll);
 917	}
 918}
 919
 920static void zl3073x_dev_dpll_fini(void *ptr)
 921{
 922	struct zl3073x_dpll *zldpll, *next;
 923	struct zl3073x_dev *zldev = ptr;
 924
 925	/* Stop monitoring and unregister DPLLs */
 926	zl3073x_dev_stop(zldev);
 927
 928	/* Destroy monitoring thread */
 929	if (zldev->kworker) {
 930		kthread_destroy_worker(zldev->kworker);
 931		zldev->kworker = NULL;
 932	}
 933
 934	/* Free all DPLLs */
 935	list_for_each_entry_safe(zldpll, next, &zldev->dplls, list) {
 936		list_del(&zldpll->list);
 937		zl3073x_dpll_free(zldpll);
 938	}
 939}
 940
 941static int
 942zl3073x_devm_dpll_init(struct zl3073x_dev *zldev, u8 num_dplls)
 943{
 944	struct kthread_worker *kworker;
 945	struct zl3073x_dpll *zldpll;
 946	unsigned int i;
 947	int rc;
 948
 949	INIT_LIST_HEAD(&zldev->dplls);
 950
 951	/* Allocate all DPLLs */
 952	for (i = 0; i < num_dplls; i++) {
 953		zldpll = zl3073x_dpll_alloc(zldev, i);
 954		if (IS_ERR(zldpll)) {
 955			dev_err_probe(zldev->dev, PTR_ERR(zldpll),
 956				      "Failed to alloc DPLL%u\n", i);
 957			rc = PTR_ERR(zldpll);
 958			goto error;
 959		}
 960
 961		list_add_tail(&zldpll->list, &zldev->dplls);
 962	}
 963
 964	/* Initialize monitoring thread */
 965	kthread_init_delayed_work(&zldev->work, zl3073x_dev_periodic_work);
 966	kworker = kthread_run_worker(0, "zl3073x-%s", dev_name(zldev->dev));
 967	if (IS_ERR(kworker)) {
 968		rc = PTR_ERR(kworker);
 969		goto error;
 970	}
 971	zldev->kworker = kworker;
 972
 973	/* Start normal operation */
 974	rc = zl3073x_dev_start(zldev, true);
 975	if (rc) {
 976		dev_err_probe(zldev->dev, rc, "Failed to start device\n");
 977		goto error;
 978	}
 979
 980	/* Add devres action to release DPLL related resources */
 981	return devm_add_action_or_reset(zldev->dev, zl3073x_dev_dpll_fini, zldev);
 982
 983error:
 984	zl3073x_dev_dpll_fini(zldev);
 985
 986	return rc;
 987}
 988
 989/**
 990 * zl3073x_dev_probe - initialize zl3073x device
 991 * @zldev: pointer to zl3073x device
 992 * @chip_info: chip info based on compatible
 993 *
 994 * Common initialization of zl3073x device structure.
 995 *
 996 * Returns: 0 on success, <0 on error
 997 */
 998int zl3073x_dev_probe(struct zl3073x_dev *zldev,
 999		      const struct zl3073x_chip_info *chip_info)
1000{
1001	u16 id, revision, fw_ver;
1002	unsigned int i;
1003	u32 cfg_ver;
1004	int rc;
1005
1006	/* Read chip ID */
1007	rc = zl3073x_read_u16(zldev, ZL_REG_ID, &id);
1008	if (rc)
1009		return rc;
1010
1011	/* Check it matches */
1012	for (i = 0; i < chip_info->num_ids; i++) {
1013		if (id == chip_info->ids[i])
1014			break;
1015	}
1016
1017	if (i == chip_info->num_ids) {
1018		return dev_err_probe(zldev->dev, -ENODEV,
1019				     "Unknown or non-match chip ID: 0x%0x\n",
1020				     id);
1021	}
1022	zldev->chip_id = id;
1023
1024	/* Read revision, firmware version and custom config version */
1025	rc = zl3073x_read_u16(zldev, ZL_REG_REVISION, &revision);
1026	if (rc)
1027		return rc;
1028	rc = zl3073x_read_u16(zldev, ZL_REG_FW_VER, &fw_ver);
1029	if (rc)
1030		return rc;
1031	rc = zl3073x_read_u32(zldev, ZL_REG_CUSTOM_CONFIG_VER, &cfg_ver);
1032	if (rc)
1033		return rc;
1034
1035	dev_dbg(zldev->dev, "ChipID(%X), ChipRev(%X), FwVer(%u)\n", id,
1036		revision, fw_ver);
1037	dev_dbg(zldev->dev, "Custom config version: %lu.%lu.%lu.%lu\n",
1038		FIELD_GET(GENMASK(31, 24), cfg_ver),
1039		FIELD_GET(GENMASK(23, 16), cfg_ver),
1040		FIELD_GET(GENMASK(15, 8), cfg_ver),
1041		FIELD_GET(GENMASK(7, 0), cfg_ver));
1042
1043	/* Generate random clock ID as the device has not such property that
1044	 * could be used for this purpose. A user can later change this value
1045	 * using devlink.
1046	 */
1047	zldev->clock_id = get_random_u64();
1048
1049	/* Default phase offset averaging factor */
1050	zldev->phase_avg_factor = 2;
1051
1052	/* Initialize mutex for operations where multiple reads, writes
1053	 * and/or polls are required to be done atomically.
1054	 */
1055	rc = devm_mutex_init(zldev->dev, &zldev->multiop_lock);
1056	if (rc)
1057		return dev_err_probe(zldev->dev, rc,
1058				     "Failed to initialize mutex\n");
1059
1060	/* Register DPLL channels */
1061	rc = zl3073x_devm_dpll_init(zldev, chip_info->num_channels);
1062	if (rc)
1063		return rc;
1064
1065	/* Register the devlink instance and parameters */
1066	rc = zl3073x_devlink_register(zldev);
1067	if (rc)
1068		return dev_err_probe(zldev->dev, rc,
1069				     "Failed to register devlink instance\n");
1070
1071	return 0;
1072}
1073EXPORT_SYMBOL_NS_GPL(zl3073x_dev_probe, "ZL3073X");
1074
1075MODULE_AUTHOR("Ivan Vecera <ivecera@redhat.com>");
1076MODULE_DESCRIPTION("Microchip ZL3073x core driver");
1077MODULE_LICENSE("GPL");