xdma-regs.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * Copyright (C) 2017-2020 Xilinx, Inc. All rights reserved.
  4 * Copyright (C) 2022, Advanced Micro Devices, Inc.
  5 */
  6
  7#ifndef __DMA_XDMA_REGS_H
  8#define __DMA_XDMA_REGS_H
  9
 10/* The length of register space exposed to host */
 11#define XDMA_REG_SPACE_LEN	65536
 12#define XDMA_MAX_REG_OFFSET	(XDMA_REG_SPACE_LEN - 4)
 13
 14/*
 15 * maximum number of DMA channels for each direction:
 16 * Host to Card (H2C) or Card to Host (C2H)
 17 */
 18#define XDMA_MAX_CHANNELS	4
 19
 20/*
 21 * macros to define the number of descriptor blocks can be used in one
 22 * DMA transfer request.
 23 * the DMA engine uses a linked list of descriptor blocks that specify the
 24 * source, destination, and length of the DMA transfers.
 25 */
 26#define XDMA_DESC_BLOCK_NUM		BIT(7)
 27#define XDMA_DESC_BLOCK_MASK		(XDMA_DESC_BLOCK_NUM - 1)
 28
 29/* descriptor definitions */
 30#define XDMA_DESC_ADJACENT		32
 31#define XDMA_DESC_ADJACENT_MASK		(XDMA_DESC_ADJACENT - 1)
 32#define XDMA_DESC_ADJACENT_BITS		GENMASK(13, 8)
 33#define XDMA_DESC_MAGIC			0xad4bUL
 34#define XDMA_DESC_MAGIC_BITS		GENMASK(31, 16)
 35#define XDMA_DESC_FLAGS_BITS		GENMASK(7, 0)
 36#define XDMA_DESC_STOPPED		BIT(0)
 37#define XDMA_DESC_COMPLETED		BIT(1)
 38#define XDMA_DESC_BLEN_BITS		28
 39#define XDMA_DESC_BLEN_MAX		(BIT(XDMA_DESC_BLEN_BITS) - PAGE_SIZE)
 40
 41/* macros to construct the descriptor control word */
 42#define XDMA_DESC_CONTROL(adjacent, flag)				\
 43	(FIELD_PREP(XDMA_DESC_MAGIC_BITS, XDMA_DESC_MAGIC) |		\
 44	 FIELD_PREP(XDMA_DESC_ADJACENT_BITS, (adjacent) - 1) |		\
 45	 FIELD_PREP(XDMA_DESC_FLAGS_BITS, (flag)))
 46#define XDMA_DESC_CONTROL_LAST						\
 47	XDMA_DESC_CONTROL(1, XDMA_DESC_STOPPED | XDMA_DESC_COMPLETED)
 48#define XDMA_DESC_CONTROL_CYCLIC					\
 49	XDMA_DESC_CONTROL(1, XDMA_DESC_COMPLETED)
 50
 51/*
 52 * Descriptor for a single contiguous memory block transfer.
 53 *
 54 * Multiple descriptors are linked by means of the next pointer. An additional
 55 * extra adjacent number gives the amount of extra contiguous descriptors.
 56 *
 57 * The descriptors are in root complex memory, and the bytes in the 32-bit
 58 * words must be in little-endian byte ordering.
 59 */
 60struct xdma_hw_desc {
 61	__le32		control;
 62	__le32		bytes;
 63	__le64		src_addr;
 64	__le64		dst_addr;
 65	__le64		next_desc;
 66};
 67
 68#define XDMA_DESC_SIZE			sizeof(struct xdma_hw_desc)
 69#define XDMA_DESC_BLOCK_SIZE		(XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)
 70#define XDMA_DESC_BLOCK_ALIGN		32
 71#define XDMA_DESC_BLOCK_BOUNDARY	4096
 72
 73/*
 74 * Channel registers
 75 */
 76#define XDMA_CHAN_IDENTIFIER		0x0
 77#define XDMA_CHAN_CONTROL		0x4
 78#define XDMA_CHAN_CONTROL_W1S		0x8
 79#define XDMA_CHAN_CONTROL_W1C		0xc
 80#define XDMA_CHAN_STATUS		0x40
 81#define XDMA_CHAN_STATUS_RC		0x44
 82#define XDMA_CHAN_COMPLETED_DESC	0x48
 83#define XDMA_CHAN_ALIGNMENTS		0x4c
 84#define XDMA_CHAN_INTR_ENABLE		0x90
 85#define XDMA_CHAN_INTR_ENABLE_W1S	0x94
 86#define XDMA_CHAN_INTR_ENABLE_W1C	0x9c
 87
 88#define XDMA_CHAN_STRIDE	0x100
 89#define XDMA_CHAN_H2C_OFFSET	0x0
 90#define XDMA_CHAN_C2H_OFFSET	0x1000
 91#define XDMA_CHAN_H2C_TARGET	0x0
 92#define XDMA_CHAN_C2H_TARGET	0x1
 93
 94/* macro to check if channel is available */
 95#define XDMA_CHAN_MAGIC		0x1fc0
 96#define XDMA_CHAN_CHECK_TARGET(id, target)		\
 97	(((u32)(id) >> 16) == XDMA_CHAN_MAGIC + (target))
 98
 99/* bits of the channel control register */
100#define CHAN_CTRL_RUN_STOP			BIT(0)
101#define CHAN_CTRL_IE_DESC_STOPPED		BIT(1)
102#define CHAN_CTRL_IE_DESC_COMPLETED		BIT(2)
103#define CHAN_CTRL_IE_DESC_ALIGN_MISMATCH	BIT(3)
104#define CHAN_CTRL_IE_MAGIC_STOPPED		BIT(4)
105#define CHAN_CTRL_IE_IDLE_STOPPED		BIT(6)
106#define CHAN_CTRL_IE_READ_ERROR			GENMASK(13, 9)
107#define CHAN_CTRL_IE_WRITE_ERROR		GENMASK(18, 14)
108#define CHAN_CTRL_IE_DESC_ERROR			GENMASK(23, 19)
109#define CHAN_CTRL_NON_INCR_ADDR			BIT(25)
110#define CHAN_CTRL_POLL_MODE_WB			BIT(26)
111
112#define CHAN_CTRL_START	(CHAN_CTRL_RUN_STOP |				\
113			 CHAN_CTRL_IE_DESC_STOPPED |			\
114			 CHAN_CTRL_IE_DESC_COMPLETED |			\
115			 CHAN_CTRL_IE_DESC_ALIGN_MISMATCH |		\
116			 CHAN_CTRL_IE_MAGIC_STOPPED |			\
117			 CHAN_CTRL_IE_READ_ERROR |			\
118			 CHAN_CTRL_IE_WRITE_ERROR |			\
119			 CHAN_CTRL_IE_DESC_ERROR)
120
121/* bits of the channel status register */
122#define XDMA_CHAN_STATUS_BUSY			BIT(0)
123
124#define XDMA_CHAN_STATUS_MASK CHAN_CTRL_START
125
126#define XDMA_CHAN_ERROR_MASK (CHAN_CTRL_IE_DESC_ALIGN_MISMATCH |	\
127			      CHAN_CTRL_IE_MAGIC_STOPPED |		\
128			      CHAN_CTRL_IE_READ_ERROR |			\
129			      CHAN_CTRL_IE_WRITE_ERROR |		\
130			      CHAN_CTRL_IE_DESC_ERROR)
131
132/* bits of the channel interrupt enable mask */
133#define CHAN_IM_DESC_ERROR			BIT(19)
134#define CHAN_IM_READ_ERROR			BIT(9)
135#define CHAN_IM_IDLE_STOPPED			BIT(6)
136#define CHAN_IM_MAGIC_STOPPED			BIT(4)
137#define CHAN_IM_DESC_COMPLETED			BIT(2)
138#define CHAN_IM_DESC_STOPPED			BIT(1)
139
140#define CHAN_IM_ALL	(CHAN_IM_DESC_ERROR | CHAN_IM_READ_ERROR |	\
141			 CHAN_IM_IDLE_STOPPED | CHAN_IM_MAGIC_STOPPED | \
142			 CHAN_IM_DESC_COMPLETED | CHAN_IM_DESC_STOPPED)
143
144/*
145 * Channel SGDMA registers
146 */
147#define XDMA_SGDMA_IDENTIFIER	0x4000
148#define XDMA_SGDMA_DESC_LO	0x4080
149#define XDMA_SGDMA_DESC_HI	0x4084
150#define XDMA_SGDMA_DESC_ADJ	0x4088
151#define XDMA_SGDMA_DESC_CREDIT	0x408c
152
153/*
154 * interrupt registers
155 */
156#define XDMA_IRQ_IDENTIFIER		0x2000
157#define XDMA_IRQ_USER_INT_EN		0x2004
158#define XDMA_IRQ_USER_INT_EN_W1S	0x2008
159#define XDMA_IRQ_USER_INT_EN_W1C	0x200c
160#define XDMA_IRQ_CHAN_INT_EN		0x2010
161#define XDMA_IRQ_CHAN_INT_EN_W1S	0x2014
162#define XDMA_IRQ_CHAN_INT_EN_W1C	0x2018
163#define XDMA_IRQ_USER_INT_REQ		0x2040
164#define XDMA_IRQ_CHAN_INT_REQ		0x2044
165#define XDMA_IRQ_USER_INT_PEND		0x2048
166#define XDMA_IRQ_CHAN_INT_PEND		0x204c
167#define XDMA_IRQ_USER_VEC_NUM		0x2080
168#define XDMA_IRQ_CHAN_VEC_NUM		0x20a0
169
170#define XDMA_IRQ_VEC_SHIFT		8
171
172#endif /* __DMA_XDMA_REGS_H */