hw.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
  4 */
  5#ifndef _IOAT_HW_H_
  6#define _IOAT_HW_H_
  7
  8/* PCI Configuration Space Values */
  9#define IOAT_MMIO_BAR		0
 10
 11/* CB device ID's */
 12#define PCI_DEVICE_ID_INTEL_IOAT_IVB0	0x0e20
 13#define PCI_DEVICE_ID_INTEL_IOAT_IVB1	0x0e21
 14#define PCI_DEVICE_ID_INTEL_IOAT_IVB2	0x0e22
 15#define PCI_DEVICE_ID_INTEL_IOAT_IVB3	0x0e23
 16#define PCI_DEVICE_ID_INTEL_IOAT_IVB4	0x0e24
 17#define PCI_DEVICE_ID_INTEL_IOAT_IVB5	0x0e25
 18#define PCI_DEVICE_ID_INTEL_IOAT_IVB6	0x0e26
 19#define PCI_DEVICE_ID_INTEL_IOAT_IVB7	0x0e27
 20#define PCI_DEVICE_ID_INTEL_IOAT_IVB8	0x0e2e
 21#define PCI_DEVICE_ID_INTEL_IOAT_IVB9	0x0e2f
 22
 23#define PCI_DEVICE_ID_INTEL_IOAT_HSW0	0x2f20
 24#define PCI_DEVICE_ID_INTEL_IOAT_HSW1	0x2f21
 25#define PCI_DEVICE_ID_INTEL_IOAT_HSW2	0x2f22
 26#define PCI_DEVICE_ID_INTEL_IOAT_HSW3	0x2f23
 27#define PCI_DEVICE_ID_INTEL_IOAT_HSW4	0x2f24
 28#define PCI_DEVICE_ID_INTEL_IOAT_HSW5	0x2f25
 29#define PCI_DEVICE_ID_INTEL_IOAT_HSW6	0x2f26
 30#define PCI_DEVICE_ID_INTEL_IOAT_HSW7	0x2f27
 31#define PCI_DEVICE_ID_INTEL_IOAT_HSW8	0x2f2e
 32#define PCI_DEVICE_ID_INTEL_IOAT_HSW9	0x2f2f
 33
 34#define PCI_DEVICE_ID_INTEL_IOAT_BWD0	0x0C50
 35#define PCI_DEVICE_ID_INTEL_IOAT_BWD1	0x0C51
 36#define PCI_DEVICE_ID_INTEL_IOAT_BWD2	0x0C52
 37#define PCI_DEVICE_ID_INTEL_IOAT_BWD3	0x0C53
 38
 39#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0	0x6f50
 40#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1	0x6f51
 41#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2	0x6f52
 42#define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3	0x6f53
 43
 44#define PCI_DEVICE_ID_INTEL_IOAT_BDX0	0x6f20
 45#define PCI_DEVICE_ID_INTEL_IOAT_BDX1	0x6f21
 46#define PCI_DEVICE_ID_INTEL_IOAT_BDX2	0x6f22
 47#define PCI_DEVICE_ID_INTEL_IOAT_BDX3	0x6f23
 48#define PCI_DEVICE_ID_INTEL_IOAT_BDX4	0x6f24
 49#define PCI_DEVICE_ID_INTEL_IOAT_BDX5	0x6f25
 50#define PCI_DEVICE_ID_INTEL_IOAT_BDX6	0x6f26
 51#define PCI_DEVICE_ID_INTEL_IOAT_BDX7	0x6f27
 52#define PCI_DEVICE_ID_INTEL_IOAT_BDX8	0x6f2e
 53#define PCI_DEVICE_ID_INTEL_IOAT_BDX9	0x6f2f
 54
 55#define PCI_DEVICE_ID_INTEL_IOAT_SKX	0x2021
 56
 57#define PCI_DEVICE_ID_INTEL_IOAT_ICX	0x0b00
 58
 59#define IOAT_VER_1_2            0x12    /* Version 1.2 */
 60#define IOAT_VER_2_0            0x20    /* Version 2.0 */
 61#define IOAT_VER_3_0            0x30    /* Version 3.0 */
 62#define IOAT_VER_3_2            0x32    /* Version 3.2 */
 63#define IOAT_VER_3_3            0x33    /* Version 3.3 */
 64#define IOAT_VER_3_4		0x34	/* Version 3.4 */
 65
 66#define IOAT_DESC_SZ	64
 67
 68struct ioat_dma_descriptor {
 69	uint32_t	size;
 70	union {
 71		uint32_t ctl;
 72		struct {
 73			unsigned int int_en:1;
 74			unsigned int src_snoop_dis:1;
 75			unsigned int dest_snoop_dis:1;
 76			unsigned int compl_write:1;
 77			unsigned int fence:1;
 78			unsigned int null:1;
 79			unsigned int src_brk:1;
 80			unsigned int dest_brk:1;
 81			unsigned int bundle:1;
 82			unsigned int dest_dca:1;
 83			unsigned int hint:1;
 84			unsigned int rsvd2:13;
 85			#define IOAT_OP_COPY 0x00
 86			unsigned int op:8;
 87		} ctl_f;
 88	};
 89	uint64_t	src_addr;
 90	uint64_t	dst_addr;
 91	uint64_t	next;
 92	uint64_t	rsv1;
 93	uint64_t	rsv2;
 94	/* store some driver data in an unused portion of the descriptor */
 95	union {
 96		uint64_t	user1;
 97		uint64_t	tx_cnt;
 98	};
 99	uint64_t	user2;
100};
101
102struct ioat_xor_descriptor {
103	uint32_t	size;
104	union {
105		uint32_t ctl;
106		struct {
107			unsigned int int_en:1;
108			unsigned int src_snoop_dis:1;
109			unsigned int dest_snoop_dis:1;
110			unsigned int compl_write:1;
111			unsigned int fence:1;
112			unsigned int src_cnt:3;
113			unsigned int bundle:1;
114			unsigned int dest_dca:1;
115			unsigned int hint:1;
116			unsigned int rsvd:13;
117			#define IOAT_OP_XOR 0x87
118			#define IOAT_OP_XOR_VAL 0x88
119			unsigned int op:8;
120		} ctl_f;
121	};
122	uint64_t	src_addr;
123	uint64_t	dst_addr;
124	uint64_t	next;
125	uint64_t	src_addr2;
126	uint64_t	src_addr3;
127	uint64_t	src_addr4;
128	uint64_t	src_addr5;
129};
130
131struct ioat_xor_ext_descriptor {
132	uint64_t	src_addr6;
133	uint64_t	src_addr7;
134	uint64_t	src_addr8;
135	uint64_t	next;
136	uint64_t	rsvd[4];
137};
138
139struct ioat_pq_descriptor {
140	union {
141		uint32_t	size;
142		uint32_t	dwbes;
143		struct {
144			unsigned int rsvd:25;
145			unsigned int p_val_err:1;
146			unsigned int q_val_err:1;
147			unsigned int rsvd1:4;
148			unsigned int wbes:1;
149		} dwbes_f;
150	};
151	union {
152		uint32_t ctl;
153		struct {
154			unsigned int int_en:1;
155			unsigned int src_snoop_dis:1;
156			unsigned int dest_snoop_dis:1;
157			unsigned int compl_write:1;
158			unsigned int fence:1;
159			unsigned int src_cnt:3;
160			unsigned int bundle:1;
161			unsigned int dest_dca:1;
162			unsigned int hint:1;
163			unsigned int p_disable:1;
164			unsigned int q_disable:1;
165			unsigned int rsvd2:2;
166			unsigned int wb_en:1;
167			unsigned int prl_en:1;
168			unsigned int rsvd3:7;
169			#define IOAT_OP_PQ 0x89
170			#define IOAT_OP_PQ_VAL 0x8a
171			#define IOAT_OP_PQ_16S 0xa0
172			#define IOAT_OP_PQ_VAL_16S 0xa1
173			unsigned int op:8;
174		} ctl_f;
175	};
176	uint64_t	src_addr;
177	uint64_t	p_addr;
178	uint64_t	next;
179	uint64_t	src_addr2;
180	union {
181		uint64_t	src_addr3;
182		uint64_t	sed_addr;
183	};
184	uint8_t		coef[8];
185	uint64_t	q_addr;
186};
187
188struct ioat_pq_ext_descriptor {
189	uint64_t	src_addr4;
190	uint64_t	src_addr5;
191	uint64_t	src_addr6;
192	uint64_t	next;
193	uint64_t	src_addr7;
194	uint64_t	src_addr8;
195	uint64_t	rsvd[2];
196};
197
198struct ioat_pq_update_descriptor {
199	uint32_t	size;
200	union {
201		uint32_t ctl;
202		struct {
203			unsigned int int_en:1;
204			unsigned int src_snoop_dis:1;
205			unsigned int dest_snoop_dis:1;
206			unsigned int compl_write:1;
207			unsigned int fence:1;
208			unsigned int src_cnt:3;
209			unsigned int bundle:1;
210			unsigned int dest_dca:1;
211			unsigned int hint:1;
212			unsigned int p_disable:1;
213			unsigned int q_disable:1;
214			unsigned int rsvd:3;
215			unsigned int coef:8;
216			#define IOAT_OP_PQ_UP 0x8b
217			unsigned int op:8;
218		} ctl_f;
219	};
220	uint64_t	src_addr;
221	uint64_t	p_addr;
222	uint64_t	next;
223	uint64_t	src_addr2;
224	uint64_t	p_src;
225	uint64_t	q_src;
226	uint64_t	q_addr;
227};
228
229struct ioat_raw_descriptor {
230	uint64_t	field[8];
231};
232
233struct ioat_pq16a_descriptor {
234	uint8_t coef[8];
235	uint64_t src_addr3;
236	uint64_t src_addr4;
237	uint64_t src_addr5;
238	uint64_t src_addr6;
239	uint64_t src_addr7;
240	uint64_t src_addr8;
241	uint64_t src_addr9;
242};
243
244struct ioat_pq16b_descriptor {
245	uint64_t src_addr10;
246	uint64_t src_addr11;
247	uint64_t src_addr12;
248	uint64_t src_addr13;
249	uint64_t src_addr14;
250	uint64_t src_addr15;
251	uint64_t src_addr16;
252	uint64_t rsvd;
253};
254
255union ioat_sed_pq_descriptor {
256	struct ioat_pq16a_descriptor a;
257	struct ioat_pq16b_descriptor b;
258};
259
260#define SED_SIZE	64
261
262struct ioat_sed_raw_descriptor {
263	uint64_t	a[8];
264	uint64_t	b[8];
265	uint64_t	c[8];
266};
267
268#endif