dma.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
  4 */
  5#ifndef IOATDMA_H
  6#define IOATDMA_H
  7
  8#include <linux/dmaengine.h>
  9#include <linux/init.h>
 10#include <linux/dmapool.h>
 11#include <linux/cache.h>
 12#include <linux/pci_ids.h>
 13#include <linux/circ_buf.h>
 14#include <linux/interrupt.h>
 15#include "registers.h"
 16#include "hw.h"
 17
 18#define IOAT_DMA_VERSION  "5.00"
 19
 20#define IOAT_DMA_DCA_ANY_CPU		~0
 21
 22int system_has_dca_enabled(struct pci_dev *pdev);
 23
 24#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, dma_dev)
 25#define to_dev(ioat_chan) (&(ioat_chan)->ioat_dma->pdev->dev)
 26#define to_pdev(ioat_chan) ((ioat_chan)->ioat_dma->pdev)
 27
 28#define chan_num(ch) ((int)((ch)->reg_base - (ch)->ioat_dma->reg_base) / 0x80)
 29
 30/* ioat hardware assumes at least two sources for raid operations */
 31#define src_cnt_to_sw(x) ((x) + 2)
 32#define src_cnt_to_hw(x) ((x) - 2)
 33#define ndest_to_sw(x) ((x) + 1)
 34#define ndest_to_hw(x) ((x) - 1)
 35#define src16_cnt_to_sw(x) ((x) + 9)
 36#define src16_cnt_to_hw(x) ((x) - 9)
 37
 38/*
 39 * workaround for IOAT ver.3.0 null descriptor issue
 40 * (channel returns error when size is 0)
 41 */
 42#define NULL_DESC_BUFFER_SIZE 1
 43
 44enum ioat_irq_mode {
 45	IOAT_NOIRQ = 0,
 46	IOAT_MSIX,
 47	IOAT_MSI,
 48	IOAT_INTX
 49};
 50
 51/**
 52 * struct ioatdma_device - internal representation of a IOAT device
 53 * @pdev: PCI-Express device
 54 * @reg_base: MMIO register space base address
 55 * @completion_pool: DMA buffers for completion ops
 56 * @sed_hw_pool: DMA super descriptor pools
 57 * @dma_dev: embedded struct dma_device
 58 * @version: version of ioatdma device
 59 * @msix_entries: irq handlers
 60 * @idx: per channel data
 61 * @dca: direct cache access context
 62 * @irq_mode: interrupt mode (INTX, MSI, MSIX)
 63 * @cap: read DMA capabilities register
 64 */
 65struct ioatdma_device {
 66	struct pci_dev *pdev;
 67	void __iomem *reg_base;
 68	struct dma_pool *completion_pool;
 69#define MAX_SED_POOLS	5
 70	struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
 71	struct dma_device dma_dev;
 72	u8 version;
 73#define IOAT_MAX_CHANS 4
 74	struct msix_entry msix_entries[IOAT_MAX_CHANS];
 75	struct ioatdma_chan *idx[IOAT_MAX_CHANS];
 76	struct dca_provider *dca;
 77	enum ioat_irq_mode irq_mode;
 78	u32 cap;
 79	int chancnt;
 80
 81	/* shadow version for CB3.3 chan reset errata workaround */
 82	u64 msixtba0;
 83	u64 msixdata0;
 84	u32 msixpba;
 85};
 86
 87#define IOAT_MAX_ORDER 16
 88#define IOAT_MAX_DESCS (1 << IOAT_MAX_ORDER)
 89#define IOAT_CHUNK_SIZE (SZ_512K)
 90#define IOAT_DESCS_PER_CHUNK (IOAT_CHUNK_SIZE / IOAT_DESC_SZ)
 91
 92struct ioat_descs {
 93	void *virt;
 94	dma_addr_t hw;
 95};
 96
 97struct ioatdma_chan {
 98	struct dma_chan dma_chan;
 99	void __iomem *reg_base;
100	dma_addr_t last_completion;
101	spinlock_t cleanup_lock;
102	unsigned long state;
103	#define IOAT_CHAN_DOWN 0
104	#define IOAT_COMPLETION_ACK 1
105	#define IOAT_RESET_PENDING 2
106	#define IOAT_KOBJ_INIT_FAIL 3
107	#define IOAT_RUN 5
108	#define IOAT_CHAN_ACTIVE 6
109	struct timer_list timer;
110	#define RESET_DELAY msecs_to_jiffies(100)
111	struct ioatdma_device *ioat_dma;
112	dma_addr_t completion_dma;
113	u64 *completion;
114	struct tasklet_struct cleanup_task;
115	struct kobject kobj;
116
117/* ioat v2 / v3 channel attributes
118 * @xfercap_log; log2 of channel max transfer length (for fast division)
119 * @head: allocated index
120 * @issued: hardware notification point
121 * @tail: cleanup index
122 * @dmacount: identical to 'head' except for occasionally resetting to zero
123 * @alloc_order: log2 of the number of allocated descriptors
124 * @produce: number of descriptors to produce at submit time
125 * @ring: software ring buffer implementation of hardware ring
126 * @prep_lock: serializes descriptor preparation (producers)
127 */
128	size_t xfercap_log;
129	u16 head;
130	u16 issued;
131	u16 tail;
132	u16 dmacount;
133	u16 alloc_order;
134	u16 produce;
135	struct ioat_ring_ent **ring;
136	spinlock_t prep_lock;
137	struct ioat_descs descs[IOAT_MAX_DESCS / IOAT_DESCS_PER_CHUNK];
138	int desc_chunks;
139	int intr_coalesce;
140	int prev_intr_coalesce;
141};
142
143struct ioat_sysfs_entry {
144	struct attribute attr;
145	ssize_t (*show)(struct dma_chan *, char *);
146	ssize_t (*store)(struct dma_chan *, const char *, size_t);
147};
148
149/**
150 * struct ioat_sed_ent - wrapper around super extended hardware descriptor
151 * @hw: hardware SED
152 * @dma: dma address for the SED
153 * @parent: point to the dma descriptor that's the parent
154 * @hw_pool: descriptor pool index
155 */
156struct ioat_sed_ent {
157	struct ioat_sed_raw_descriptor *hw;
158	dma_addr_t dma;
159	struct ioat_ring_ent *parent;
160	unsigned int hw_pool;
161};
162
163/**
164 * struct ioat_ring_ent - wrapper around hardware descriptor
165 * @hw: hardware DMA descriptor (for memcpy)
166 * @xor: hardware xor descriptor
167 * @xor_ex: hardware xor extension descriptor
168 * @pq: hardware pq descriptor
169 * @pq_ex: hardware pq extension descriptor
170 * @pqu: hardware pq update descriptor
171 * @raw: hardware raw (un-typed) descriptor
172 * @txd: the generic software descriptor for all engines
173 * @len: total transaction length for unmap
174 * @result: asynchronous result of validate operations
175 * @id: identifier for debug
176 * @sed: pointer to super extended descriptor sw desc
177 */
178
179struct ioat_ring_ent {
180	union {
181		struct ioat_dma_descriptor *hw;
182		struct ioat_xor_descriptor *xor;
183		struct ioat_xor_ext_descriptor *xor_ex;
184		struct ioat_pq_descriptor *pq;
185		struct ioat_pq_ext_descriptor *pq_ex;
186		struct ioat_pq_update_descriptor *pqu;
187		struct ioat_raw_descriptor *raw;
188	};
189	size_t len;
190	struct dma_async_tx_descriptor txd;
191	enum sum_check_flags *result;
192	#ifdef DEBUG
193	int id;
194	#endif
195	struct ioat_sed_ent *sed;
196};
197
198extern const struct sysfs_ops ioat_sysfs_ops;
199extern struct ioat_sysfs_entry ioat_version_attr;
200extern struct ioat_sysfs_entry ioat_cap_attr;
201extern int ioat_pending_level;
202extern struct kobj_type ioat_ktype;
203extern struct kmem_cache *ioat_cache;
204extern struct kmem_cache *ioat_sed_cache;
205
206static inline struct ioatdma_chan *to_ioat_chan(struct dma_chan *c)
207{
208	return container_of(c, struct ioatdma_chan, dma_chan);
209}
210
211/* wrapper around hardware descriptor format + additional software fields */
212#ifdef DEBUG
213#define set_desc_id(desc, i) ((desc)->id = (i))
214#define desc_id(desc) ((desc)->id)
215#else
216#define set_desc_id(desc, i)
217#define desc_id(desc) (0)
218#endif
219
220static inline void
221__dump_desc_dbg(struct ioatdma_chan *ioat_chan, struct ioat_dma_descriptor *hw,
222		struct dma_async_tx_descriptor *tx, int id)
223{
224	struct device *dev = to_dev(ioat_chan);
225
226	dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
227		" ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
228		(unsigned long long) tx->phys,
229		(unsigned long long) hw->next, tx->cookie, tx->flags,
230		hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
231}
232
233#define dump_desc_dbg(c, d) \
234	({ if (d) __dump_desc_dbg(c, d->hw, &d->txd, desc_id(d)); 0; })
235
236static inline struct ioatdma_chan *
237ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index)
238{
239	return ioat_dma->idx[index];
240}
241
242static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan)
243{
244	return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET);
245}
246
247static inline u64 ioat_chansts_to_addr(u64 status)
248{
249	return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
250}
251
252static inline u32 ioat_chanerr(struct ioatdma_chan *ioat_chan)
253{
254	return readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
255}
256
257static inline void ioat_suspend(struct ioatdma_chan *ioat_chan)
258{
259	u8 ver = ioat_chan->ioat_dma->version;
260
261	writeb(IOAT_CHANCMD_SUSPEND,
262	       ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
263}
264
265static inline void ioat_reset(struct ioatdma_chan *ioat_chan)
266{
267	u8 ver = ioat_chan->ioat_dma->version;
268
269	writeb(IOAT_CHANCMD_RESET,
270	       ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
271}
272
273static inline bool ioat_reset_pending(struct ioatdma_chan *ioat_chan)
274{
275	u8 ver = ioat_chan->ioat_dma->version;
276	u8 cmd;
277
278	cmd = readb(ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
279	return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
280}
281
282static inline bool is_ioat_active(unsigned long status)
283{
284	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
285}
286
287static inline bool is_ioat_idle(unsigned long status)
288{
289	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
290}
291
292static inline bool is_ioat_halted(unsigned long status)
293{
294	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
295}
296
297static inline bool is_ioat_suspended(unsigned long status)
298{
299	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
300}
301
302/* channel was fatally programmed */
303static inline bool is_ioat_bug(unsigned long err)
304{
305	return !!err;
306}
307
308
309static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan)
310{
311	return 1 << ioat_chan->alloc_order;
312}
313
314/* count of descriptors in flight with the engine */
315static inline u16 ioat_ring_active(struct ioatdma_chan *ioat_chan)
316{
317	return CIRC_CNT(ioat_chan->head, ioat_chan->tail,
318			ioat_ring_size(ioat_chan));
319}
320
321/* count of descriptors pending submission to hardware */
322static inline u16 ioat_ring_pending(struct ioatdma_chan *ioat_chan)
323{
324	return CIRC_CNT(ioat_chan->head, ioat_chan->issued,
325			ioat_ring_size(ioat_chan));
326}
327
328static inline u32 ioat_ring_space(struct ioatdma_chan *ioat_chan)
329{
330	return ioat_ring_size(ioat_chan) - ioat_ring_active(ioat_chan);
331}
332
333static inline u16
334ioat_xferlen_to_descs(struct ioatdma_chan *ioat_chan, size_t len)
335{
336	u16 num_descs = len >> ioat_chan->xfercap_log;
337
338	num_descs += !!(len & ((1 << ioat_chan->xfercap_log) - 1));
339	return num_descs;
340}
341
342static inline struct ioat_ring_ent *
343ioat_get_ring_ent(struct ioatdma_chan *ioat_chan, u16 idx)
344{
345	return ioat_chan->ring[idx & (ioat_ring_size(ioat_chan) - 1)];
346}
347
348static inline void
349ioat_set_chainaddr(struct ioatdma_chan *ioat_chan, u64 addr)
350{
351	writel(addr & 0x00000000FFFFFFFF,
352	       ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
353	writel(addr >> 32,
354	       ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
355}
356
357/* IOAT Prep functions */
358struct dma_async_tx_descriptor *
359ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
360			   dma_addr_t dma_src, size_t len, unsigned long flags);
361struct dma_async_tx_descriptor *
362ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags);
363struct dma_async_tx_descriptor *
364ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
365	       unsigned int src_cnt, size_t len, unsigned long flags);
366struct dma_async_tx_descriptor *
367ioat_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
368		    unsigned int src_cnt, size_t len,
369		    enum sum_check_flags *result, unsigned long flags);
370struct dma_async_tx_descriptor *
371ioat_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
372	      unsigned int src_cnt, const unsigned char *scf, size_t len,
373	      unsigned long flags);
374struct dma_async_tx_descriptor *
375ioat_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
376		  unsigned int src_cnt, const unsigned char *scf, size_t len,
377		  enum sum_check_flags *pqres, unsigned long flags);
378struct dma_async_tx_descriptor *
379ioat_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
380		 unsigned int src_cnt, size_t len, unsigned long flags);
381struct dma_async_tx_descriptor *
382ioat_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src,
383		     unsigned int src_cnt, size_t len,
384		     enum sum_check_flags *result, unsigned long flags);
385
386/* IOAT Operation functions */
387irqreturn_t ioat_dma_do_interrupt(int irq, void *data);
388irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data);
389struct ioat_ring_ent **
390ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags);
391void ioat_start_null_desc(struct ioatdma_chan *ioat_chan);
392void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan);
393int ioat_reset_hw(struct ioatdma_chan *ioat_chan);
394enum dma_status
395ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
396		struct dma_tx_state *txstate);
397void ioat_cleanup_event(struct tasklet_struct *t);
398void ioat_timer_event(struct timer_list *t);
399int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs);
400void ioat_issue_pending(struct dma_chan *chan);
401
402/* IOAT Init functions */
403bool is_bwd_ioat(struct pci_dev *pdev);
404struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
405void ioat_kobject_add(struct ioatdma_device *ioat_dma, struct kobj_type *type);
406void ioat_kobject_del(struct ioatdma_device *ioat_dma);
407int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma);
408void ioat_stop(struct ioatdma_chan *ioat_chan);
409#endif /* IOATDMA_H */