device.c

   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
   3#include <linux/init.h>
   4#include <linux/kernel.h>
   5#include <linux/module.h>
   6#include <linux/pci.h>
   7#include <linux/io-64-nonatomic-lo-hi.h>
   8#include <linux/dmaengine.h>
   9#include <linux/irq.h>
  10#include <uapi/linux/idxd.h>
  11#include "../dmaengine.h"
  12#include "idxd.h"
  13#include "registers.h"
  14
  15static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
  16			  u32 *status);
  17static void idxd_device_wqs_clear_state(struct idxd_device *idxd);
  18static void idxd_wq_disable_cleanup(struct idxd_wq *wq);
  19static int idxd_wq_config_write(struct idxd_wq *wq);
  20
  21/* Interrupt control bits */
  22void idxd_unmask_error_interrupts(struct idxd_device *idxd)
  23{
  24	union genctrl_reg genctrl;
  25
  26	genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
  27	genctrl.softerr_int_en = 1;
  28	genctrl.halt_int_en = 1;
  29	iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
  30}
  31
  32void idxd_mask_error_interrupts(struct idxd_device *idxd)
  33{
  34	union genctrl_reg genctrl;
  35
  36	genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
  37	genctrl.softerr_int_en = 0;
  38	genctrl.halt_int_en = 0;
  39	iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
  40}
  41
  42static void free_hw_descs(struct idxd_wq *wq)
  43{
  44	int i;
  45
  46	for (i = 0; i < wq->num_descs; i++)
  47		kfree(wq->hw_descs[i]);
  48
  49	kfree(wq->hw_descs);
  50}
  51
  52static int alloc_hw_descs(struct idxd_wq *wq, int num)
  53{
  54	struct device *dev = &wq->idxd->pdev->dev;
  55	int i;
  56	int node = dev_to_node(dev);
  57
  58	wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *),
  59				    GFP_KERNEL, node);
  60	if (!wq->hw_descs)
  61		return -ENOMEM;
  62
  63	for (i = 0; i < num; i++) {
  64		wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]),
  65					       GFP_KERNEL, node);
  66		if (!wq->hw_descs[i]) {
  67			free_hw_descs(wq);
  68			return -ENOMEM;
  69		}
  70	}
  71
  72	return 0;
  73}
  74
  75static void free_descs(struct idxd_wq *wq)
  76{
  77	int i;
  78
  79	for (i = 0; i < wq->num_descs; i++)
  80		kfree(wq->descs[i]);
  81
  82	kfree(wq->descs);
  83}
  84
  85static int alloc_descs(struct idxd_wq *wq, int num)
  86{
  87	struct device *dev = &wq->idxd->pdev->dev;
  88	int i;
  89	int node = dev_to_node(dev);
  90
  91	wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *),
  92				 GFP_KERNEL, node);
  93	if (!wq->descs)
  94		return -ENOMEM;
  95
  96	for (i = 0; i < num; i++) {
  97		wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]),
  98					    GFP_KERNEL, node);
  99		if (!wq->descs[i]) {
 100			free_descs(wq);
 101			return -ENOMEM;
 102		}
 103	}
 104
 105	return 0;
 106}
 107
 108/* WQ control bits */
 109int idxd_wq_alloc_resources(struct idxd_wq *wq)
 110{
 111	struct idxd_device *idxd = wq->idxd;
 112	struct device *dev = &idxd->pdev->dev;
 113	int rc, num_descs, i;
 114
 115	if (wq->type != IDXD_WQT_KERNEL)
 116		return 0;
 117
 118	num_descs = wq_dedicated(wq) ? wq->size : wq->threshold;
 119	wq->num_descs = num_descs;
 120
 121	rc = alloc_hw_descs(wq, num_descs);
 122	if (rc < 0)
 123		return rc;
 124
 125	wq->compls_size = num_descs * idxd->data->compl_size;
 126	wq->compls = dma_alloc_coherent(dev, wq->compls_size, &wq->compls_addr, GFP_KERNEL);
 127	if (!wq->compls) {
 128		rc = -ENOMEM;
 129		goto fail_alloc_compls;
 130	}
 131
 132	rc = alloc_descs(wq, num_descs);
 133	if (rc < 0)
 134		goto fail_alloc_descs;
 135
 136	rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL,
 137				     dev_to_node(dev));
 138	if (rc < 0)
 139		goto fail_sbitmap_init;
 140
 141	for (i = 0; i < num_descs; i++) {
 142		struct idxd_desc *desc = wq->descs[i];
 143
 144		desc->hw = wq->hw_descs[i];
 145		if (idxd->data->type == IDXD_TYPE_DSA)
 146			desc->completion = &wq->compls[i];
 147		else if (idxd->data->type == IDXD_TYPE_IAX)
 148			desc->iax_completion = &wq->iax_compls[i];
 149		desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i;
 150		desc->id = i;
 151		desc->wq = wq;
 152		desc->cpu = -1;
 153	}
 154
 155	return 0;
 156
 157 fail_sbitmap_init:
 158	free_descs(wq);
 159 fail_alloc_descs:
 160	dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr);
 161 fail_alloc_compls:
 162	free_hw_descs(wq);
 163	return rc;
 164}
 165EXPORT_SYMBOL_NS_GPL(idxd_wq_alloc_resources, "IDXD");
 166
 167void idxd_wq_free_resources(struct idxd_wq *wq)
 168{
 169	struct device *dev = &wq->idxd->pdev->dev;
 170
 171	if (wq->type != IDXD_WQT_KERNEL)
 172		return;
 173
 174	free_hw_descs(wq);
 175	free_descs(wq);
 176	dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr);
 177	sbitmap_queue_free(&wq->sbq);
 178	wq->type = IDXD_WQT_NONE;
 179}
 180EXPORT_SYMBOL_NS_GPL(idxd_wq_free_resources, "IDXD");
 181
 182int idxd_wq_enable(struct idxd_wq *wq)
 183{
 184	struct idxd_device *idxd = wq->idxd;
 185	struct device *dev = &idxd->pdev->dev;
 186	u32 status;
 187
 188	if (wq->state == IDXD_WQ_ENABLED) {
 189		dev_dbg(dev, "WQ %d already enabled\n", wq->id);
 190		return 0;
 191	}
 192
 193	idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status);
 194
 195	if (status != IDXD_CMDSTS_SUCCESS &&
 196	    status != IDXD_CMDSTS_ERR_WQ_ENABLED) {
 197		dev_dbg(dev, "WQ enable failed: %#x\n", status);
 198		return -ENXIO;
 199	}
 200
 201	wq->state = IDXD_WQ_ENABLED;
 202	set_bit(wq->id, idxd->wq_enable_map);
 203	dev_dbg(dev, "WQ %d enabled\n", wq->id);
 204	return 0;
 205}
 206
 207int idxd_wq_disable(struct idxd_wq *wq, bool reset_config)
 208{
 209	struct idxd_device *idxd = wq->idxd;
 210	struct device *dev = &idxd->pdev->dev;
 211	u32 status, operand;
 212
 213	dev_dbg(dev, "Disabling WQ %d\n", wq->id);
 214
 215	if (wq->state != IDXD_WQ_ENABLED) {
 216		dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
 217		return 0;
 218	}
 219
 220	/*
 221	 * Disable WQ does not drain address translations, if WQ attributes are
 222	 * changed before translations are drained, pending translations can
 223	 * be issued using updated WQ attibutes, resulting in invalid
 224	 * translations being cached in the device translation cache.
 225	 *
 226	 * To make sure pending translations are drained before WQ
 227	 * attributes are changed, we use a WQ Drain followed by WQ Reset and
 228	 * then restore the WQ configuration.
 229	 */
 230	idxd_wq_drain(wq);
 231
 232	operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
 233	idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, &status);
 234
 235	if (status != IDXD_CMDSTS_SUCCESS) {
 236		dev_dbg(dev, "WQ reset failed: %#x\n", status);
 237		return -ENXIO;
 238	}
 239
 240	idxd_wq_config_write(wq);
 241
 242	if (reset_config)
 243		idxd_wq_disable_cleanup(wq);
 244	clear_bit(wq->id, idxd->wq_enable_map);
 245	wq->state = IDXD_WQ_DISABLED;
 246	dev_dbg(dev, "WQ %d disabled\n", wq->id);
 247	return 0;
 248}
 249
 250void idxd_wq_drain(struct idxd_wq *wq)
 251{
 252	struct idxd_device *idxd = wq->idxd;
 253	struct device *dev = &idxd->pdev->dev;
 254	u32 operand;
 255
 256	if (wq->state != IDXD_WQ_ENABLED) {
 257		dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
 258		return;
 259	}
 260
 261	dev_dbg(dev, "Draining WQ %d\n", wq->id);
 262	operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
 263	idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL);
 264}
 265
 266void idxd_wq_reset(struct idxd_wq *wq)
 267{
 268	struct idxd_device *idxd = wq->idxd;
 269	struct device *dev = &idxd->pdev->dev;
 270	u32 operand;
 271
 272	if (wq->state != IDXD_WQ_ENABLED) {
 273		dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
 274		return;
 275	}
 276
 277	operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
 278	idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL);
 279	idxd_wq_disable_cleanup(wq);
 280}
 281
 282int idxd_wq_map_portal(struct idxd_wq *wq)
 283{
 284	struct idxd_device *idxd = wq->idxd;
 285	struct pci_dev *pdev = idxd->pdev;
 286	struct device *dev = &pdev->dev;
 287	resource_size_t start;
 288
 289	start = pci_resource_start(pdev, IDXD_WQ_BAR);
 290	start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED);
 291
 292	wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE);
 293	if (!wq->portal)
 294		return -ENOMEM;
 295
 296	return 0;
 297}
 298
 299void idxd_wq_unmap_portal(struct idxd_wq *wq)
 300{
 301	struct device *dev = &wq->idxd->pdev->dev;
 302
 303	devm_iounmap(dev, wq->portal);
 304	wq->portal = NULL;
 305	wq->portal_offset = 0;
 306}
 307
 308void idxd_wqs_unmap_portal(struct idxd_device *idxd)
 309{
 310	int i;
 311
 312	for (i = 0; i < idxd->max_wqs; i++) {
 313		struct idxd_wq *wq = idxd->wqs[i];
 314
 315		if (wq->portal)
 316			idxd_wq_unmap_portal(wq);
 317	}
 318}
 319
 320static void __idxd_wq_set_pasid_locked(struct idxd_wq *wq, int pasid)
 321{
 322	struct idxd_device *idxd = wq->idxd;
 323	union wqcfg wqcfg;
 324	unsigned int offset;
 325
 326	offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
 327	spin_lock(&idxd->dev_lock);
 328	wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
 329	wqcfg.pasid_en = 1;
 330	wqcfg.pasid = pasid;
 331	wq->wqcfg->bits[WQCFG_PASID_IDX] = wqcfg.bits[WQCFG_PASID_IDX];
 332	iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
 333	spin_unlock(&idxd->dev_lock);
 334}
 335
 336int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid)
 337{
 338	int rc;
 339
 340	rc = idxd_wq_disable(wq, false);
 341	if (rc < 0)
 342		return rc;
 343
 344	__idxd_wq_set_pasid_locked(wq, pasid);
 345
 346	rc = idxd_wq_enable(wq);
 347	if (rc < 0)
 348		return rc;
 349
 350	return 0;
 351}
 352
 353int idxd_wq_disable_pasid(struct idxd_wq *wq)
 354{
 355	struct idxd_device *idxd = wq->idxd;
 356	int rc;
 357	union wqcfg wqcfg;
 358	unsigned int offset;
 359
 360	rc = idxd_wq_disable(wq, false);
 361	if (rc < 0)
 362		return rc;
 363
 364	offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
 365	spin_lock(&idxd->dev_lock);
 366	wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
 367	wqcfg.pasid_en = 0;
 368	wqcfg.pasid = 0;
 369	iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
 370	spin_unlock(&idxd->dev_lock);
 371
 372	rc = idxd_wq_enable(wq);
 373	if (rc < 0)
 374		return rc;
 375
 376	return 0;
 377}
 378
 379static void idxd_wq_disable_cleanup(struct idxd_wq *wq)
 380{
 381	struct idxd_device *idxd = wq->idxd;
 382
 383	lockdep_assert_held(&wq->wq_lock);
 384	wq->state = IDXD_WQ_DISABLED;
 385	memset(wq->wqcfg, 0, idxd->wqcfg_size);
 386	wq->threshold = 0;
 387	wq->priority = 0;
 388	wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;
 389	wq->flags = 0;
 390	memset(wq->name, 0, WQ_NAME_SIZE);
 391	wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
 392	idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH);
 393	if (wq->opcap_bmap)
 394		bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS);
 395}
 396
 397static void idxd_wq_device_reset_cleanup(struct idxd_wq *wq)
 398{
 399	lockdep_assert_held(&wq->wq_lock);
 400
 401	wq->size = 0;
 402	wq->group = NULL;
 403}
 404
 405static void idxd_wq_ref_release(struct percpu_ref *ref)
 406{
 407	struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active);
 408
 409	complete(&wq->wq_dead);
 410}
 411
 412int idxd_wq_init_percpu_ref(struct idxd_wq *wq)
 413{
 414	int rc;
 415
 416	memset(&wq->wq_active, 0, sizeof(wq->wq_active));
 417	rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release,
 418			     PERCPU_REF_ALLOW_REINIT, GFP_KERNEL);
 419	if (rc < 0)
 420		return rc;
 421	reinit_completion(&wq->wq_dead);
 422	reinit_completion(&wq->wq_resurrect);
 423	return 0;
 424}
 425EXPORT_SYMBOL_NS_GPL(idxd_wq_init_percpu_ref, "IDXD");
 426
 427void __idxd_wq_quiesce(struct idxd_wq *wq)
 428{
 429	lockdep_assert_held(&wq->wq_lock);
 430	reinit_completion(&wq->wq_resurrect);
 431	percpu_ref_kill(&wq->wq_active);
 432	complete_all(&wq->wq_resurrect);
 433	wait_for_completion(&wq->wq_dead);
 434}
 435EXPORT_SYMBOL_NS_GPL(__idxd_wq_quiesce, "IDXD");
 436
 437void idxd_wq_quiesce(struct idxd_wq *wq)
 438{
 439	mutex_lock(&wq->wq_lock);
 440	__idxd_wq_quiesce(wq);
 441	mutex_unlock(&wq->wq_lock);
 442}
 443EXPORT_SYMBOL_NS_GPL(idxd_wq_quiesce, "IDXD");
 444
 445/* Device control bits */
 446static inline bool idxd_is_enabled(struct idxd_device *idxd)
 447{
 448	union gensts_reg gensts;
 449
 450	gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
 451
 452	if (gensts.state == IDXD_DEVICE_STATE_ENABLED)
 453		return true;
 454	return false;
 455}
 456
 457static inline bool idxd_device_is_halted(struct idxd_device *idxd)
 458{
 459	union gensts_reg gensts;
 460
 461	gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
 462
 463	return (gensts.state == IDXD_DEVICE_STATE_HALT);
 464}
 465
 466/*
 467 * This is function is only used for reset during probe and will
 468 * poll for completion. Once the device is setup with interrupts,
 469 * all commands will be done via interrupt completion.
 470 */
 471int idxd_device_init_reset(struct idxd_device *idxd)
 472{
 473	struct device *dev = &idxd->pdev->dev;
 474	union idxd_command_reg cmd;
 475
 476	if (idxd_device_is_halted(idxd)) {
 477		dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
 478		return -ENXIO;
 479	}
 480
 481	memset(&cmd, 0, sizeof(cmd));
 482	cmd.cmd = IDXD_CMD_RESET_DEVICE;
 483	dev_dbg(dev, "%s: sending reset for init.\n", __func__);
 484	spin_lock(&idxd->cmd_lock);
 485	iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
 486
 487	while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) &
 488	       IDXD_CMDSTS_ACTIVE)
 489		cpu_relax();
 490	spin_unlock(&idxd->cmd_lock);
 491	return 0;
 492}
 493
 494static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
 495			  u32 *status)
 496{
 497	union idxd_command_reg cmd;
 498	DECLARE_COMPLETION_ONSTACK(done);
 499	u32 stat;
 500	unsigned long flags;
 501
 502	if (idxd_device_is_halted(idxd)) {
 503		dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
 504		if (status)
 505			*status = IDXD_CMDSTS_HW_ERR;
 506		return;
 507	}
 508
 509	memset(&cmd, 0, sizeof(cmd));
 510	cmd.cmd = cmd_code;
 511	cmd.operand = operand;
 512	cmd.int_req = 1;
 513
 514	spin_lock_irqsave(&idxd->cmd_lock, flags);
 515	wait_event_lock_irq(idxd->cmd_waitq,
 516			    !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags),
 517			    idxd->cmd_lock);
 518
 519	dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n",
 520		__func__, cmd_code, operand);
 521
 522	idxd->cmd_status = 0;
 523	__set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
 524	idxd->cmd_done = &done;
 525	iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
 526
 527	/*
 528	 * After command submitted, release lock and go to sleep until
 529	 * the command completes via interrupt.
 530	 */
 531	spin_unlock_irqrestore(&idxd->cmd_lock, flags);
 532	wait_for_completion(&done);
 533	stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
 534	spin_lock(&idxd->cmd_lock);
 535	if (status)
 536		*status = stat;
 537	idxd->cmd_status = stat & GENMASK(7, 0);
 538
 539	__clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
 540	/* Wake up other pending commands */
 541	wake_up(&idxd->cmd_waitq);
 542	spin_unlock(&idxd->cmd_lock);
 543}
 544
 545int idxd_device_enable(struct idxd_device *idxd)
 546{
 547	struct device *dev = &idxd->pdev->dev;
 548	u32 status;
 549
 550	if (idxd_is_enabled(idxd)) {
 551		dev_dbg(dev, "Device already enabled\n");
 552		return -ENXIO;
 553	}
 554
 555	idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status);
 556
 557	/* If the command is successful or if the device was enabled */
 558	if (status != IDXD_CMDSTS_SUCCESS &&
 559	    status != IDXD_CMDSTS_ERR_DEV_ENABLED) {
 560		dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
 561		return -ENXIO;
 562	}
 563
 564	idxd->state = IDXD_DEV_ENABLED;
 565	return 0;
 566}
 567
 568int idxd_device_disable(struct idxd_device *idxd)
 569{
 570	struct device *dev = &idxd->pdev->dev;
 571	u32 status;
 572
 573	if (!idxd_is_enabled(idxd)) {
 574		dev_dbg(dev, "Device is not enabled\n");
 575		return 0;
 576	}
 577
 578	idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status);
 579
 580	/* If the command is successful or if the device was disabled */
 581	if (status != IDXD_CMDSTS_SUCCESS &&
 582	    !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) {
 583		dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
 584		return -ENXIO;
 585	}
 586
 587	idxd_device_clear_state(idxd);
 588	return 0;
 589}
 590
 591void idxd_device_reset(struct idxd_device *idxd)
 592{
 593	idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL);
 594	idxd_device_clear_state(idxd);
 595	spin_lock(&idxd->dev_lock);
 596	idxd_unmask_error_interrupts(idxd);
 597	spin_unlock(&idxd->dev_lock);
 598}
 599
 600void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid)
 601{
 602	struct device *dev = &idxd->pdev->dev;
 603	u32 operand;
 604
 605	operand = pasid;
 606	dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand);
 607	idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL);
 608	dev_dbg(dev, "pasid %d drained\n", pasid);
 609}
 610
 611int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle,
 612				   enum idxd_interrupt_type irq_type)
 613{
 614	struct device *dev = &idxd->pdev->dev;
 615	u32 operand, status;
 616
 617	if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)))
 618		return -EOPNOTSUPP;
 619
 620	dev_dbg(dev, "get int handle, idx %d\n", idx);
 621
 622	operand = idx & GENMASK(15, 0);
 623	if (irq_type == IDXD_IRQ_IMS)
 624		operand |= CMD_INT_HANDLE_IMS;
 625
 626	dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand);
 627
 628	idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status);
 629
 630	if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
 631		dev_dbg(dev, "request int handle failed: %#x\n", status);
 632		return -ENXIO;
 633	}
 634
 635	*handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0);
 636
 637	dev_dbg(dev, "int handle acquired: %u\n", *handle);
 638	return 0;
 639}
 640
 641int idxd_device_release_int_handle(struct idxd_device *idxd, int handle,
 642				   enum idxd_interrupt_type irq_type)
 643{
 644	struct device *dev = &idxd->pdev->dev;
 645	u32 operand, status;
 646	union idxd_command_reg cmd;
 647
 648	if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE)))
 649		return -EOPNOTSUPP;
 650
 651	dev_dbg(dev, "release int handle, handle %d\n", handle);
 652
 653	memset(&cmd, 0, sizeof(cmd));
 654	operand = handle & GENMASK(15, 0);
 655
 656	if (irq_type == IDXD_IRQ_IMS)
 657		operand |= CMD_INT_HANDLE_IMS;
 658
 659	cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE;
 660	cmd.operand = operand;
 661
 662	dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand);
 663
 664	spin_lock(&idxd->cmd_lock);
 665	iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
 666
 667	while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE)
 668		cpu_relax();
 669	status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
 670	spin_unlock(&idxd->cmd_lock);
 671
 672	if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
 673		dev_dbg(dev, "release int handle failed: %#x\n", status);
 674		return -ENXIO;
 675	}
 676
 677	dev_dbg(dev, "int handle released.\n");
 678	return 0;
 679}
 680
 681/* Device configuration bits */
 682static void idxd_engines_clear_state(struct idxd_device *idxd)
 683{
 684	struct idxd_engine *engine;
 685	int i;
 686
 687	lockdep_assert_held(&idxd->dev_lock);
 688	for (i = 0; i < idxd->max_engines; i++) {
 689		engine = idxd->engines[i];
 690		engine->group = NULL;
 691	}
 692}
 693
 694static void idxd_groups_clear_state(struct idxd_device *idxd)
 695{
 696	struct idxd_group *group;
 697	int i;
 698
 699	lockdep_assert_held(&idxd->dev_lock);
 700	for (i = 0; i < idxd->max_groups; i++) {
 701		group = idxd->groups[i];
 702		memset(&group->grpcfg, 0, sizeof(group->grpcfg));
 703		group->num_engines = 0;
 704		group->num_wqs = 0;
 705		group->use_rdbuf_limit = false;
 706		/*
 707		 * The default value is the same as the value of
 708		 * total read buffers in GRPCAP.
 709		 */
 710		group->rdbufs_allowed = idxd->max_rdbufs;
 711		group->rdbufs_reserved = 0;
 712		if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) {
 713			group->tc_a = 1;
 714			group->tc_b = 1;
 715		} else {
 716			group->tc_a = -1;
 717			group->tc_b = -1;
 718		}
 719		group->desc_progress_limit = 0;
 720		group->batch_progress_limit = 0;
 721	}
 722}
 723
 724static void idxd_device_wqs_clear_state(struct idxd_device *idxd)
 725{
 726	int i;
 727
 728	for (i = 0; i < idxd->max_wqs; i++) {
 729		struct idxd_wq *wq = idxd->wqs[i];
 730
 731		mutex_lock(&wq->wq_lock);
 732		idxd_wq_disable_cleanup(wq);
 733		idxd_wq_device_reset_cleanup(wq);
 734		mutex_unlock(&wq->wq_lock);
 735	}
 736}
 737
 738void idxd_device_clear_state(struct idxd_device *idxd)
 739{
 740	/* IDXD is always disabled. Other states are cleared only when IDXD is configurable. */
 741	if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
 742		/*
 743		 * Clearing wq state is protected by wq lock.
 744		 * So no need to be protected by device lock.
 745		 */
 746		idxd_device_wqs_clear_state(idxd);
 747
 748		spin_lock(&idxd->dev_lock);
 749		idxd_groups_clear_state(idxd);
 750		idxd_engines_clear_state(idxd);
 751	} else {
 752		spin_lock(&idxd->dev_lock);
 753	}
 754
 755	idxd->state = IDXD_DEV_DISABLED;
 756	spin_unlock(&idxd->dev_lock);
 757}
 758
 759static int idxd_device_evl_setup(struct idxd_device *idxd)
 760{
 761	union gencfg_reg gencfg;
 762	union evlcfg_reg evlcfg;
 763	union genctrl_reg genctrl;
 764	struct device *dev = &idxd->pdev->dev;
 765	void *addr;
 766	dma_addr_t dma_addr;
 767	int size;
 768	struct idxd_evl *evl = idxd->evl;
 769	unsigned long *bmap;
 770	int rc;
 771
 772	if (!evl)
 773		return 0;
 774
 775	size = evl_size(idxd);
 776
 777	bmap = bitmap_zalloc(size, GFP_KERNEL);
 778	if (!bmap) {
 779		rc = -ENOMEM;
 780		goto err_bmap;
 781	}
 782
 783	/*
 784	 * Address needs to be page aligned. However, dma_alloc_coherent() provides
 785	 * at minimal page size aligned address. No manual alignment required.
 786	 */
 787	addr = dma_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
 788	if (!addr) {
 789		rc = -ENOMEM;
 790		goto err_alloc;
 791	}
 792
 793	mutex_lock(&evl->lock);
 794	evl->log = addr;
 795	evl->dma = dma_addr;
 796	evl->log_size = size;
 797	evl->bmap = bmap;
 798
 799	memset(&evlcfg, 0, sizeof(evlcfg));
 800	evlcfg.bits[0] = dma_addr & GENMASK(63, 12);
 801	evlcfg.size = evl->size;
 802
 803	iowrite64(evlcfg.bits[0], idxd->reg_base + IDXD_EVLCFG_OFFSET);
 804	iowrite64(evlcfg.bits[1], idxd->reg_base + IDXD_EVLCFG_OFFSET + 8);
 805
 806	genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
 807	genctrl.evl_int_en = 1;
 808	iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
 809
 810	gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
 811	gencfg.evl_en = 1;
 812	iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
 813
 814	mutex_unlock(&evl->lock);
 815	return 0;
 816
 817err_alloc:
 818	bitmap_free(bmap);
 819err_bmap:
 820	return rc;
 821}
 822
 823static void idxd_device_evl_free(struct idxd_device *idxd)
 824{
 825	void *evl_log;
 826	unsigned int evl_log_size;
 827	dma_addr_t evl_dma;
 828	union gencfg_reg gencfg;
 829	union genctrl_reg genctrl;
 830	struct device *dev = &idxd->pdev->dev;
 831	struct idxd_evl *evl = idxd->evl;
 832
 833	if (!evl)
 834		return;
 835
 836	mutex_lock(&evl->lock);
 837	gencfg.evl_en = 0;
 838	iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
 839
 840	genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
 841	genctrl.evl_int_en = 0;
 842	iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
 843
 844	iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET);
 845	iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET + 8);
 846
 847	bitmap_free(evl->bmap);
 848	evl_log = evl->log;
 849	evl_log_size = evl->log_size;
 850	evl_dma = evl->dma;
 851	evl->log = NULL;
 852	evl->size = IDXD_EVL_SIZE_MIN;
 853	mutex_unlock(&evl->lock);
 854
 855	dma_free_coherent(dev, evl_log_size, evl_log, evl_dma);
 856}
 857
 858static void idxd_group_config_write(struct idxd_group *group)
 859{
 860	struct idxd_device *idxd = group->idxd;
 861	struct device *dev = &idxd->pdev->dev;
 862	int i;
 863	u32 grpcfg_offset;
 864
 865	dev_dbg(dev, "Writing group %d cfg registers\n", group->id);
 866
 867	/* setup GRPWQCFG */
 868	for (i = 0; i < GRPWQCFG_STRIDES; i++) {
 869		grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
 870		iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset);
 871		dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
 872			group->id, i, grpcfg_offset,
 873			ioread64(idxd->reg_base + grpcfg_offset));
 874	}
 875
 876	/* setup GRPENGCFG */
 877	grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
 878	iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset);
 879	dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
 880		grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset));
 881
 882	/* setup GRPFLAGS */
 883	grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
 884	iowrite64(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset);
 885	dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#llx\n",
 886		group->id, grpcfg_offset,
 887		ioread64(idxd->reg_base + grpcfg_offset));
 888}
 889
 890static int idxd_groups_config_write(struct idxd_device *idxd)
 891
 892{
 893	union gencfg_reg reg;
 894	int i;
 895	struct device *dev = &idxd->pdev->dev;
 896
 897	/* Setup bandwidth rdbuf limit */
 898	if (idxd->hw.gen_cap.config_en && idxd->rdbuf_limit) {
 899		reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
 900		reg.rdbuf_limit = idxd->rdbuf_limit;
 901		iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
 902	}
 903
 904	dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET,
 905		ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET));
 906
 907	for (i = 0; i < idxd->max_groups; i++) {
 908		struct idxd_group *group = idxd->groups[i];
 909
 910		idxd_group_config_write(group);
 911	}
 912
 913	return 0;
 914}
 915
 916static bool idxd_device_pasid_priv_enabled(struct idxd_device *idxd)
 917{
 918	struct pci_dev *pdev = idxd->pdev;
 919
 920	if (pdev->pasid_enabled && (pdev->pasid_features & PCI_PASID_CAP_PRIV))
 921		return true;
 922	return false;
 923}
 924
 925static int idxd_wq_config_write(struct idxd_wq *wq)
 926{
 927	struct idxd_device *idxd = wq->idxd;
 928	struct device *dev = &idxd->pdev->dev;
 929	u32 wq_offset;
 930	int i, n;
 931
 932	if (!wq->group)
 933		return 0;
 934
 935	/*
 936	 * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after
 937	 * wq reset. This will copy back the sticky values that are present on some devices.
 938	 */
 939	for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
 940		wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
 941		wq->wqcfg->bits[i] |= ioread32(idxd->reg_base + wq_offset);
 942	}
 943
 944	if (wq->size == 0 && wq->type != IDXD_WQT_NONE)
 945		wq->size = WQ_DEFAULT_QUEUE_DEPTH;
 946
 947	/* byte 0-3 */
 948	wq->wqcfg->wq_size = wq->size;
 949
 950	/* bytes 4-7 */
 951	wq->wqcfg->wq_thresh = wq->threshold;
 952
 953	/* byte 8-11 */
 954	if (wq_dedicated(wq))
 955		wq->wqcfg->mode = 1;
 956
 957	/*
 958	 * The WQ priv bit is set depending on the WQ type. priv = 1 if the
 959	 * WQ type is kernel to indicate privileged access. This setting only
 960	 * matters for dedicated WQ. According to the DSA spec:
 961	 * If the WQ is in dedicated mode, WQ PASID Enable is 1, and the
 962	 * Privileged Mode Enable field of the PCI Express PASID capability
 963	 * is 0, this field must be 0.
 964	 *
 965	 * In the case of a dedicated kernel WQ that is not able to support
 966	 * the PASID cap, then the configuration will be rejected.
 967	 */
 968	if (wq_dedicated(wq) && wq->wqcfg->pasid_en &&
 969	    !idxd_device_pasid_priv_enabled(idxd) &&
 970	    wq->type == IDXD_WQT_KERNEL) {
 971		idxd->cmd_status = IDXD_SCMD_WQ_NO_PRIV;
 972		return -EOPNOTSUPP;
 973	}
 974
 975	wq->wqcfg->priority = wq->priority;
 976
 977	if (idxd->hw.gen_cap.block_on_fault &&
 978	    test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags) &&
 979	    !test_bit(WQ_FLAG_PRS_DISABLE, &wq->flags))
 980		wq->wqcfg->bof = 1;
 981
 982	if (idxd->hw.wq_cap.wq_ats_support)
 983		wq->wqcfg->wq_ats_disable = test_bit(WQ_FLAG_ATS_DISABLE, &wq->flags);
 984
 985	if (idxd->hw.wq_cap.wq_prs_support)
 986		wq->wqcfg->wq_prs_disable = test_bit(WQ_FLAG_PRS_DISABLE, &wq->flags);
 987
 988	/* bytes 12-15 */
 989	wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes);
 990	idxd_wqcfg_set_max_batch_shift(idxd->data->type, wq->wqcfg, ilog2(wq->max_batch_size));
 991
 992	/* bytes 32-63 */
 993	if (idxd->hw.wq_cap.op_config && wq->opcap_bmap) {
 994		memset(wq->wqcfg->op_config, 0, IDXD_MAX_OPCAP_BITS / 8);
 995		for_each_set_bit(n, wq->opcap_bmap, IDXD_MAX_OPCAP_BITS) {
 996			int pos = n % BITS_PER_LONG_LONG;
 997			int idx = n / BITS_PER_LONG_LONG;
 998
 999			wq->wqcfg->op_config[idx] |= BIT(pos);
1000		}
1001	}
1002
1003	dev_dbg(dev, "WQ %d CFGs\n", wq->id);
1004	for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
1005		wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
1006		iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset);
1007		dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n",
1008			wq->id, i, wq_offset,
1009			ioread32(idxd->reg_base + wq_offset));
1010	}
1011
1012	return 0;
1013}
1014
1015static int idxd_wqs_config_write(struct idxd_device *idxd)
1016{
1017	int i, rc;
1018
1019	for (i = 0; i < idxd->max_wqs; i++) {
1020		struct idxd_wq *wq = idxd->wqs[i];
1021
1022		rc = idxd_wq_config_write(wq);
1023		if (rc < 0)
1024			return rc;
1025	}
1026
1027	return 0;
1028}
1029
1030static void idxd_group_flags_setup(struct idxd_device *idxd)
1031{
1032	int i;
1033
1034	/* TC-A 0 and TC-B 1 should be defaults */
1035	for (i = 0; i < idxd->max_groups; i++) {
1036		struct idxd_group *group = idxd->groups[i];
1037
1038		if (group->tc_a == -1)
1039			group->tc_a = group->grpcfg.flags.tc_a = 0;
1040		else
1041			group->grpcfg.flags.tc_a = group->tc_a;
1042		if (group->tc_b == -1)
1043			group->tc_b = group->grpcfg.flags.tc_b = 1;
1044		else
1045			group->grpcfg.flags.tc_b = group->tc_b;
1046		group->grpcfg.flags.use_rdbuf_limit = group->use_rdbuf_limit;
1047		group->grpcfg.flags.rdbufs_reserved = group->rdbufs_reserved;
1048		group->grpcfg.flags.rdbufs_allowed = group->rdbufs_allowed;
1049		group->grpcfg.flags.desc_progress_limit = group->desc_progress_limit;
1050		group->grpcfg.flags.batch_progress_limit = group->batch_progress_limit;
1051	}
1052}
1053
1054static int idxd_engines_setup(struct idxd_device *idxd)
1055{
1056	int i, engines = 0;
1057	struct idxd_engine *eng;
1058	struct idxd_group *group;
1059
1060	for (i = 0; i < idxd->max_groups; i++) {
1061		group = idxd->groups[i];
1062		group->grpcfg.engines = 0;
1063	}
1064
1065	for (i = 0; i < idxd->max_engines; i++) {
1066		eng = idxd->engines[i];
1067		group = eng->group;
1068
1069		if (!group)
1070			continue;
1071
1072		group->grpcfg.engines |= BIT(eng->id);
1073		engines++;
1074	}
1075
1076	if (!engines)
1077		return -EINVAL;
1078
1079	return 0;
1080}
1081
1082static int idxd_wqs_setup(struct idxd_device *idxd)
1083{
1084	struct idxd_wq *wq;
1085	struct idxd_group *group;
1086	int i, j, configured = 0;
1087	struct device *dev = &idxd->pdev->dev;
1088
1089	for (i = 0; i < idxd->max_groups; i++) {
1090		group = idxd->groups[i];
1091		for (j = 0; j < 4; j++)
1092			group->grpcfg.wqs[j] = 0;
1093	}
1094
1095	for (i = 0; i < idxd->max_wqs; i++) {
1096		wq = idxd->wqs[i];
1097		group = wq->group;
1098
1099		if (!wq->group)
1100			continue;
1101
1102		if (wq_shared(wq) && !wq_shared_supported(wq)) {
1103			idxd->cmd_status = IDXD_SCMD_WQ_NO_SWQ_SUPPORT;
1104			dev_warn(dev, "No shared wq support but configured.\n");
1105			return -EINVAL;
1106		}
1107
1108		group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64);
1109		configured++;
1110	}
1111
1112	if (configured == 0) {
1113		idxd->cmd_status = IDXD_SCMD_WQ_NONE_CONFIGURED;
1114		return -EINVAL;
1115	}
1116
1117	return 0;
1118}
1119
1120int idxd_device_config(struct idxd_device *idxd)
1121{
1122	int rc;
1123
1124	guard(spinlock)(&idxd->dev_lock);
1125
1126	if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1127		return 0;
1128
1129	rc = idxd_wqs_setup(idxd);
1130	if (rc < 0)
1131		return rc;
1132
1133	rc = idxd_engines_setup(idxd);
1134	if (rc < 0)
1135		return rc;
1136
1137	idxd_group_flags_setup(idxd);
1138
1139	rc = idxd_wqs_config_write(idxd);
1140	if (rc < 0)
1141		return rc;
1142
1143	rc = idxd_groups_config_write(idxd);
1144	if (rc < 0)
1145		return rc;
1146
1147	return 0;
1148}
1149
1150static int idxd_wq_load_config(struct idxd_wq *wq)
1151{
1152	struct idxd_device *idxd = wq->idxd;
1153	struct device *dev = &idxd->pdev->dev;
1154	int wqcfg_offset;
1155	int i;
1156
1157	wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0);
1158	memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size);
1159
1160	wq->size = wq->wqcfg->wq_size;
1161	wq->threshold = wq->wqcfg->wq_thresh;
1162
1163	/* The driver does not support shared WQ mode in read-only config yet */
1164	if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en)
1165		return -EOPNOTSUPP;
1166
1167	set_bit(WQ_FLAG_DEDICATED, &wq->flags);
1168
1169	wq->priority = wq->wqcfg->priority;
1170
1171	wq->max_xfer_bytes = 1ULL << wq->wqcfg->max_xfer_shift;
1172	idxd_wq_set_max_batch_size(idxd->data->type, wq, 1U << wq->wqcfg->max_batch_shift);
1173
1174	for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
1175		wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i);
1176		dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]);
1177	}
1178
1179	return 0;
1180}
1181
1182static void idxd_group_load_config(struct idxd_group *group)
1183{
1184	struct idxd_device *idxd = group->idxd;
1185	struct device *dev = &idxd->pdev->dev;
1186	int i, j, grpcfg_offset;
1187
1188	/*
1189	 * Load WQS bit fields
1190	 * Iterate through all 256 bits 64 bits at a time
1191	 */
1192	for (i = 0; i < GRPWQCFG_STRIDES; i++) {
1193		struct idxd_wq *wq;
1194
1195		grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
1196		group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset);
1197		dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
1198			group->id, i, grpcfg_offset, group->grpcfg.wqs[i]);
1199
1200		if (i * 64 >= idxd->max_wqs)
1201			break;
1202
1203		/* Iterate through all 64 bits and check for wq set */
1204		for (j = 0; j < 64; j++) {
1205			int id = i * 64 + j;
1206
1207			/* No need to check beyond max wqs */
1208			if (id >= idxd->max_wqs)
1209				break;
1210
1211			/* Set group assignment for wq if wq bit is set */
1212			if (group->grpcfg.wqs[i] & BIT(j)) {
1213				wq = idxd->wqs[id];
1214				wq->group = group;
1215			}
1216		}
1217	}
1218
1219	grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
1220	group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset);
1221	dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
1222		grpcfg_offset, group->grpcfg.engines);
1223
1224	/* Iterate through all 64 bits to check engines set */
1225	for (i = 0; i < 64; i++) {
1226		if (i >= idxd->max_engines)
1227			break;
1228
1229		if (group->grpcfg.engines & BIT(i)) {
1230			struct idxd_engine *engine = idxd->engines[i];
1231
1232			engine->group = group;
1233		}
1234	}
1235
1236	grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
1237	group->grpcfg.flags.bits = ioread64(idxd->reg_base + grpcfg_offset);
1238	dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#llx\n",
1239		group->id, grpcfg_offset, group->grpcfg.flags.bits);
1240}
1241
1242int idxd_device_load_config(struct idxd_device *idxd)
1243{
1244	union gencfg_reg reg;
1245	int i, rc;
1246
1247	reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
1248	idxd->rdbuf_limit = reg.rdbuf_limit;
1249
1250	for (i = 0; i < idxd->max_groups; i++) {
1251		struct idxd_group *group = idxd->groups[i];
1252
1253		idxd_group_load_config(group);
1254	}
1255
1256	for (i = 0; i < idxd->max_wqs; i++) {
1257		struct idxd_wq *wq = idxd->wqs[i];
1258
1259		rc = idxd_wq_load_config(wq);
1260		if (rc < 0)
1261			return rc;
1262	}
1263
1264	return 0;
1265}
1266
1267static void idxd_flush_pending_descs(struct idxd_irq_entry *ie)
1268{
1269	struct idxd_desc *desc, *itr;
1270	struct llist_node *head;
1271	LIST_HEAD(flist);
1272	enum idxd_complete_type ctype;
1273
1274	spin_lock(&ie->list_lock);
1275	head = llist_del_all(&ie->pending_llist);
1276	if (head) {
1277		llist_for_each_entry_safe(desc, itr, head, llnode)
1278			list_add_tail(&desc->list, &ie->work_list);
1279	}
1280
1281	list_for_each_entry_safe(desc, itr, &ie->work_list, list)
1282		list_move_tail(&desc->list, &flist);
1283	spin_unlock(&ie->list_lock);
1284
1285	list_for_each_entry_safe(desc, itr, &flist, list) {
1286		struct dma_async_tx_descriptor *tx;
1287
1288		list_del(&desc->list);
1289		ctype = desc->completion->status ? IDXD_COMPLETE_NORMAL : IDXD_COMPLETE_ABORT;
1290		/*
1291		 * wq is being disabled. Any remaining descriptors are
1292		 * likely to be stuck and can be dropped. callback could
1293		 * point to code that is no longer accessible, for example
1294		 * if dmatest module has been unloaded.
1295		 */
1296		tx = &desc->txd;
1297		tx->callback = NULL;
1298		tx->callback_result = NULL;
1299		idxd_dma_complete_txd(desc, ctype, true, NULL, NULL);
1300	}
1301}
1302
1303static void idxd_device_set_perm_entry(struct idxd_device *idxd,
1304				       struct idxd_irq_entry *ie)
1305{
1306	union msix_perm mperm;
1307
1308	if (ie->pasid == IOMMU_PASID_INVALID)
1309		return;
1310
1311	mperm.bits = 0;
1312	mperm.pasid = ie->pasid;
1313	mperm.pasid_en = 1;
1314	iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8);
1315}
1316
1317static void idxd_device_clear_perm_entry(struct idxd_device *idxd,
1318					 struct idxd_irq_entry *ie)
1319{
1320	iowrite32(0, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8);
1321}
1322
1323void idxd_wq_free_irq(struct idxd_wq *wq)
1324{
1325	struct idxd_device *idxd = wq->idxd;
1326	struct idxd_irq_entry *ie = &wq->ie;
1327
1328	if (wq->type != IDXD_WQT_KERNEL)
1329		return;
1330
1331	free_irq(ie->vector, ie);
1332	idxd_flush_pending_descs(ie);
1333	if (idxd->request_int_handles)
1334		idxd_device_release_int_handle(idxd, ie->int_handle, IDXD_IRQ_MSIX);
1335	idxd_device_clear_perm_entry(idxd, ie);
1336	ie->vector = -1;
1337	ie->int_handle = INVALID_INT_HANDLE;
1338	ie->pasid = IOMMU_PASID_INVALID;
1339}
1340
1341int idxd_wq_request_irq(struct idxd_wq *wq)
1342{
1343	struct idxd_device *idxd = wq->idxd;
1344	struct pci_dev *pdev = idxd->pdev;
1345	struct device *dev = &pdev->dev;
1346	struct idxd_irq_entry *ie;
1347	int rc;
1348
1349	if (wq->type != IDXD_WQT_KERNEL)
1350		return 0;
1351
1352	ie = &wq->ie;
1353	ie->vector = pci_irq_vector(pdev, ie->id);
1354	ie->pasid = device_pasid_enabled(idxd) ? idxd->pasid : IOMMU_PASID_INVALID;
1355	idxd_device_set_perm_entry(idxd, ie);
1356
1357	rc = request_threaded_irq(ie->vector, NULL, idxd_wq_thread, 0, "idxd-portal", ie);
1358	if (rc < 0) {
1359		dev_err(dev, "Failed to request irq %d.\n", ie->vector);
1360		goto err_irq;
1361	}
1362
1363	if (idxd->request_int_handles) {
1364		rc = idxd_device_request_int_handle(idxd, ie->id, &ie->int_handle,
1365						    IDXD_IRQ_MSIX);
1366		if (rc < 0)
1367			goto err_int_handle;
1368	} else {
1369		ie->int_handle = ie->id;
1370	}
1371
1372	return 0;
1373
1374err_int_handle:
1375	ie->int_handle = INVALID_INT_HANDLE;
1376	free_irq(ie->vector, ie);
1377err_irq:
1378	idxd_device_clear_perm_entry(idxd, ie);
1379	ie->pasid = IOMMU_PASID_INVALID;
1380	return rc;
1381}
1382
1383int idxd_drv_enable_wq(struct idxd_wq *wq)
1384{
1385	struct idxd_device *idxd = wq->idxd;
1386	struct device *dev = &idxd->pdev->dev;
1387	int rc = -ENXIO;
1388
1389	lockdep_assert_held(&wq->wq_lock);
1390
1391	if (idxd->state != IDXD_DEV_ENABLED) {
1392		idxd->cmd_status = IDXD_SCMD_DEV_NOT_ENABLED;
1393		goto err;
1394	}
1395
1396	if (wq->state != IDXD_WQ_DISABLED) {
1397		dev_dbg(dev, "wq %d already enabled.\n", wq->id);
1398		idxd->cmd_status = IDXD_SCMD_WQ_ENABLED;
1399		rc = -EBUSY;
1400		goto err;
1401	}
1402
1403	if (!wq->group) {
1404		dev_dbg(dev, "wq %d not attached to group.\n", wq->id);
1405		idxd->cmd_status = IDXD_SCMD_WQ_NO_GRP;
1406		goto err;
1407	}
1408
1409	if (strlen(wq->name) == 0) {
1410		idxd->cmd_status = IDXD_SCMD_WQ_NO_NAME;
1411		dev_dbg(dev, "wq %d name not set.\n", wq->id);
1412		goto err;
1413	}
1414
1415	/* Shared WQ checks */
1416	if (wq_shared(wq)) {
1417		if (!wq_shared_supported(wq)) {
1418			idxd->cmd_status = IDXD_SCMD_WQ_NO_SVM;
1419			dev_dbg(dev, "PASID not enabled and shared wq.\n");
1420			goto err;
1421		}
1422		/*
1423		 * Shared wq with the threshold set to 0 means the user
1424		 * did not set the threshold or transitioned from a
1425		 * dedicated wq but did not set threshold. A value
1426		 * of 0 would effectively disable the shared wq. The
1427		 * driver does not allow a value of 0 to be set for
1428		 * threshold via sysfs.
1429		 */
1430		if (wq->threshold == 0) {
1431			idxd->cmd_status = IDXD_SCMD_WQ_NO_THRESH;
1432			dev_dbg(dev, "Shared wq and threshold 0.\n");
1433			goto err;
1434		}
1435	}
1436
1437	/*
1438	 * In the event that the WQ is configurable for pasid, the driver
1439	 * should setup the pasid, pasid_en bit. This is true for both kernel
1440	 * and user shared workqueues. There is no need to setup priv bit in
1441	 * that in-kernel DMA will also do user privileged requests.
1442	 * A dedicated wq that is not 'kernel' type will configure pasid and
1443	 * pasid_en later on so there is no need to setup.
1444	 */
1445	if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
1446		if (wq_pasid_enabled(wq)) {
1447			if (is_idxd_wq_kernel(wq) || wq_shared(wq)) {
1448				u32 pasid = wq_dedicated(wq) ? idxd->pasid : 0;
1449
1450				__idxd_wq_set_pasid_locked(wq, pasid);
1451			}
1452		}
1453	}
1454
1455	rc = idxd_device_config(idxd);
1456	if (rc < 0) {
1457		dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc);
1458		goto err;
1459	}
1460
1461	rc = idxd_wq_enable(wq);
1462	if (rc < 0) {
1463		dev_dbg(dev, "wq %d enabling failed: %d\n", wq->id, rc);
1464		goto err;
1465	}
1466
1467	rc = idxd_wq_map_portal(wq);
1468	if (rc < 0) {
1469		idxd->cmd_status = IDXD_SCMD_WQ_PORTAL_ERR;
1470		dev_dbg(dev, "wq %d portal mapping failed: %d\n", wq->id, rc);
1471		goto err_map_portal;
1472	}
1473
1474	wq->client_count = 0;
1475
1476	rc = idxd_wq_request_irq(wq);
1477	if (rc < 0) {
1478		idxd->cmd_status = IDXD_SCMD_WQ_IRQ_ERR;
1479		dev_dbg(dev, "WQ %d irq setup failed: %d\n", wq->id, rc);
1480		goto err_irq;
1481	}
1482
1483	rc = idxd_wq_alloc_resources(wq);
1484	if (rc < 0) {
1485		idxd->cmd_status = IDXD_SCMD_WQ_RES_ALLOC_ERR;
1486		dev_dbg(dev, "WQ resource alloc failed\n");
1487		goto err_res_alloc;
1488	}
1489
1490	rc = idxd_wq_init_percpu_ref(wq);
1491	if (rc < 0) {
1492		idxd->cmd_status = IDXD_SCMD_PERCPU_ERR;
1493		dev_dbg(dev, "percpu_ref setup failed\n");
1494		goto err_ref;
1495	}
1496
1497	return 0;
1498
1499err_ref:
1500	idxd_wq_free_resources(wq);
1501err_res_alloc:
1502	idxd_wq_free_irq(wq);
1503err_irq:
1504	idxd_wq_unmap_portal(wq);
1505err_map_portal:
1506	if (idxd_wq_disable(wq, false))
1507		dev_dbg(dev, "wq %s disable failed\n", dev_name(wq_confdev(wq)));
1508err:
1509	return rc;
1510}
1511EXPORT_SYMBOL_NS_GPL(idxd_drv_enable_wq, "IDXD");
1512
1513void idxd_drv_disable_wq(struct idxd_wq *wq)
1514{
1515	struct idxd_device *idxd = wq->idxd;
1516	struct device *dev = &idxd->pdev->dev;
1517
1518	lockdep_assert_held(&wq->wq_lock);
1519
1520	if (idxd_wq_refcount(wq))
1521		dev_warn(dev, "Clients has claim on wq %d: %d\n",
1522			 wq->id, idxd_wq_refcount(wq));
1523
1524	idxd_wq_unmap_portal(wq);
1525	idxd_wq_drain(wq);
1526	idxd_wq_free_irq(wq);
1527	idxd_wq_reset(wq);
1528	idxd_wq_free_resources(wq);
1529	percpu_ref_exit(&wq->wq_active);
1530	wq->client_count = 0;
1531}
1532EXPORT_SYMBOL_NS_GPL(idxd_drv_disable_wq, "IDXD");
1533
1534int idxd_device_drv_probe(struct idxd_dev *idxd_dev)
1535{
1536	struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev);
1537	int rc = 0;
1538
1539	/*
1540	 * Device should be in disabled state for the idxd_drv to load. If it's in
1541	 * enabled state, then the device was altered outside of driver's control.
1542	 * If the state is in halted state, then we don't want to proceed.
1543	 */
1544	if (idxd->state != IDXD_DEV_DISABLED) {
1545		idxd->cmd_status = IDXD_SCMD_DEV_ENABLED;
1546		return -ENXIO;
1547	}
1548
1549	/* Device configuration */
1550	rc = idxd_device_config(idxd);
1551	if (rc < 0)
1552		return -ENXIO;
1553
1554	/*
1555	 * System PASID is preserved across device disable/enable cycle, but
1556	 * genconfig register content gets cleared during device reset. We
1557	 * need to re-enable user interrupts for kernel work queue completion
1558	 * IRQ to function.
1559	 */
1560	if (idxd->pasid != IOMMU_PASID_INVALID)
1561		idxd_set_user_intr(idxd, 1);
1562
1563	rc = idxd_device_evl_setup(idxd);
1564	if (rc < 0) {
1565		idxd->cmd_status = IDXD_SCMD_DEV_EVL_ERR;
1566		return rc;
1567	}
1568
1569	/* Start device */
1570	rc = idxd_device_enable(idxd);
1571	if (rc < 0) {
1572		idxd_device_evl_free(idxd);
1573		return rc;
1574	}
1575
1576	/* Setup DMA device without channels */
1577	rc = idxd_register_dma_device(idxd);
1578	if (rc < 0) {
1579		idxd_device_disable(idxd);
1580		idxd_device_evl_free(idxd);
1581		idxd->cmd_status = IDXD_SCMD_DEV_DMA_ERR;
1582		return rc;
1583	}
1584
1585	idxd->cmd_status = 0;
1586	return 0;
1587}
1588
1589void idxd_device_drv_remove(struct idxd_dev *idxd_dev)
1590{
1591	struct device *dev = &idxd_dev->conf_dev;
1592	struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev);
1593	int i;
1594
1595	for (i = 0; i < idxd->max_wqs; i++) {
1596		struct idxd_wq *wq = idxd->wqs[i];
1597		struct device *wq_dev = wq_confdev(wq);
1598
1599		if (wq->state == IDXD_WQ_DISABLED)
1600			continue;
1601		dev_warn(dev, "Active wq %d on disable %s.\n", i, dev_name(wq_dev));
1602		device_release_driver(wq_dev);
1603	}
1604
1605	idxd_unregister_dma_device(idxd);
1606	idxd_device_disable(idxd);
1607	if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1608		idxd_device_reset(idxd);
1609	idxd_device_evl_free(idxd);
1610}
1611
1612static enum idxd_dev_type dev_types[] = {
1613	IDXD_DEV_DSA,
1614	IDXD_DEV_IAX,
1615	IDXD_DEV_NONE,
1616};
1617
1618struct idxd_device_driver idxd_drv = {
1619	.type = dev_types,
1620	.probe = idxd_device_drv_probe,
1621	.remove = idxd_device_drv_remove,
1622	.name = "idxd",
1623};
1624EXPORT_SYMBOL_GPL(idxd_drv);