qdma.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * DMA header for AMD Queue-based DMA Subsystem
  4 *
  5 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
  6 */
  7
  8#ifndef __QDMA_H
  9#define __QDMA_H
 10
 11#include <linux/bitfield.h>
 12#include <linux/dmaengine.h>
 13#include <linux/kernel.h>
 14#include <linux/platform_device.h>
 15#include <linux/regmap.h>
 16
 17#include "../../virt-dma.h"
 18
 19#define DISABLE					0
 20#define ENABLE					1
 21
 22#define QDMA_MIN_IRQ				3
 23#define QDMA_INTR_NAME_MAX_LEN			30
 24#define QDMA_INTR_PREFIX			"amd-qdma"
 25
 26#define QDMA_IDENTIFIER				0x1FD3
 27#define QDMA_DEFAULT_RING_SIZE			(BIT(10) + 1)
 28#define QDMA_DEFAULT_RING_ID			0
 29#define QDMA_POLL_INTRVL_US			10		/* 10us */
 30#define QDMA_POLL_TIMEOUT_US			(500 * 1000)	/* 500ms */
 31#define QDMA_DMAP_REG_STRIDE			16
 32#define QDMA_CTXT_REGMAP_LEN			8		/* 8 regs */
 33#define QDMA_MM_DESC_SIZE			32		/* Bytes */
 34#define QDMA_MM_DESC_LEN_BITS			28
 35#define QDMA_MM_DESC_MAX_LEN			(BIT(QDMA_MM_DESC_LEN_BITS) - 1)
 36#define QDMA_MIN_DMA_ALLOC_SIZE			4096
 37#define QDMA_INTR_RING_SIZE			BIT(13)
 38#define QDMA_INTR_RING_IDX_MASK			GENMASK(9, 0)
 39#define QDMA_INTR_RING_BASE(_addr)		((_addr) >> 12)
 40
 41#define QDMA_IDENTIFIER_REGOFF			0x0
 42#define QDMA_IDENTIFIER_MASK			GENMASK(31, 16)
 43#define QDMA_QUEUE_ARM_BIT			BIT(16)
 44
 45#define qdma_err(qdev, fmt, args...)					\
 46	dev_err(&(qdev)->pdev->dev, fmt, ##args)
 47
 48#define qdma_dbg(qdev, fmt, args...)					\
 49	dev_dbg(&(qdev)->pdev->dev, fmt, ##args)
 50
 51#define qdma_info(qdev, fmt, args...)					\
 52	dev_info(&(qdev)->pdev->dev, fmt, ##args)
 53
 54enum qdma_reg_fields {
 55	QDMA_REGF_IRQ_ENABLE,
 56	QDMA_REGF_WBK_ENABLE,
 57	QDMA_REGF_WBI_CHECK,
 58	QDMA_REGF_IRQ_ARM,
 59	QDMA_REGF_IRQ_VEC,
 60	QDMA_REGF_IRQ_AGG,
 61	QDMA_REGF_WBI_INTVL_ENABLE,
 62	QDMA_REGF_MRKR_DISABLE,
 63	QDMA_REGF_QUEUE_ENABLE,
 64	QDMA_REGF_QUEUE_MODE,
 65	QDMA_REGF_DESC_BASE,
 66	QDMA_REGF_DESC_SIZE,
 67	QDMA_REGF_RING_ID,
 68	QDMA_REGF_CMD_INDX,
 69	QDMA_REGF_CMD_CMD,
 70	QDMA_REGF_CMD_TYPE,
 71	QDMA_REGF_CMD_BUSY,
 72	QDMA_REGF_QUEUE_COUNT,
 73	QDMA_REGF_QUEUE_MAX,
 74	QDMA_REGF_QUEUE_BASE,
 75	QDMA_REGF_FUNCTION_ID,
 76	QDMA_REGF_INTR_AGG_BASE,
 77	QDMA_REGF_INTR_VECTOR,
 78	QDMA_REGF_INTR_SIZE,
 79	QDMA_REGF_INTR_VALID,
 80	QDMA_REGF_INTR_COLOR,
 81	QDMA_REGF_INTR_FUNCTION_ID,
 82	QDMA_REGF_ERR_INT_FUNC,
 83	QDMA_REGF_ERR_INT_VEC,
 84	QDMA_REGF_ERR_INT_ARM,
 85	QDMA_REGF_MAX
 86};
 87
 88enum qdma_regs {
 89	QDMA_REGO_CTXT_DATA,
 90	QDMA_REGO_CTXT_CMD,
 91	QDMA_REGO_CTXT_MASK,
 92	QDMA_REGO_MM_H2C_CTRL,
 93	QDMA_REGO_MM_C2H_CTRL,
 94	QDMA_REGO_QUEUE_COUNT,
 95	QDMA_REGO_RING_SIZE,
 96	QDMA_REGO_H2C_PIDX,
 97	QDMA_REGO_C2H_PIDX,
 98	QDMA_REGO_INTR_CIDX,
 99	QDMA_REGO_FUNC_ID,
100	QDMA_REGO_ERR_INT,
101	QDMA_REGO_ERR_STAT,
102	QDMA_REGO_MAX
103};
104
105struct qdma_reg_field {
106	u16 lsb; /* Least significant bit of field */
107	u16 msb; /* Most significant bit of field */
108};
109
110struct qdma_reg {
111	u32 off;
112	u32 count;
113};
114
115#define QDMA_REGF(_msb, _lsb) {						\
116	.lsb = (_lsb),							\
117	.msb = (_msb),							\
118}
119
120#define QDMA_REGO(_off, _count) {					\
121	.off = (_off),							\
122	.count = (_count),						\
123}
124
125enum qdma_desc_size {
126	QDMA_DESC_SIZE_8B,
127	QDMA_DESC_SIZE_16B,
128	QDMA_DESC_SIZE_32B,
129	QDMA_DESC_SIZE_64B,
130};
131
132enum qdma_queue_op_mode {
133	QDMA_QUEUE_OP_STREAM,
134	QDMA_QUEUE_OP_MM,
135};
136
137enum qdma_ctxt_type {
138	QDMA_CTXT_DESC_SW_C2H,
139	QDMA_CTXT_DESC_SW_H2C,
140	QDMA_CTXT_DESC_HW_C2H,
141	QDMA_CTXT_DESC_HW_H2C,
142	QDMA_CTXT_DESC_CR_C2H,
143	QDMA_CTXT_DESC_CR_H2C,
144	QDMA_CTXT_WRB,
145	QDMA_CTXT_PFTCH,
146	QDMA_CTXT_INTR_COAL,
147	QDMA_CTXT_RSVD,
148	QDMA_CTXT_HOST_PROFILE,
149	QDMA_CTXT_TIMER,
150	QDMA_CTXT_FMAP,
151	QDMA_CTXT_FNC_STS,
152};
153
154enum qdma_ctxt_cmd {
155	QDMA_CTXT_CLEAR,
156	QDMA_CTXT_WRITE,
157	QDMA_CTXT_READ,
158	QDMA_CTXT_INVALIDATE,
159	QDMA_CTXT_MAX
160};
161
162struct qdma_ctxt_sw_desc {
163	u64				desc_base;
164	u16				vec;
165};
166
167struct qdma_ctxt_intr {
168	u64				agg_base;
169	u16				vec;
170	u32				size;
171	bool				valid;
172	bool				color;
173};
174
175struct qdma_ctxt_fmap {
176	u16				qbase;
177	u16				qmax;
178};
179
180struct qdma_device;
181
182struct qdma_mm_desc {
183	__le64			src_addr;
184	__le32			len;
185	__le32			reserved1;
186	__le64			dst_addr;
187	__le64			reserved2;
188} __packed;
189
190struct qdma_mm_vdesc {
191	struct virt_dma_desc		vdesc;
192	struct qdma_queue		*queue;
193	struct scatterlist		*sgl;
194	u64				sg_off;
195	u32				sg_len;
196	u64				dev_addr;
197	u32				pidx;
198	u32				pending_descs;
199	struct dma_slave_config		cfg;
200};
201
202#define QDMA_VDESC_QUEUED(vdesc)	(!(vdesc)->sg_len)
203
204struct qdma_queue {
205	struct qdma_device		*qdev;
206	struct virt_dma_chan		vchan;
207	enum dma_transfer_direction	dir;
208	struct dma_slave_config		cfg;
209	struct qdma_mm_desc		*desc_base;
210	struct qdma_mm_vdesc		*submitted_vdesc;
211	struct qdma_mm_vdesc		*issued_vdesc;
212	dma_addr_t			dma_desc_base;
213	u32				pidx_reg;
214	u32				cidx_reg;
215	u32				ring_size;
216	u32				idx_mask;
217	u16				qid;
218	u32				pidx;
219	u32				cidx;
220};
221
222struct qdma_intr_ring {
223	struct qdma_device		*qdev;
224	__le64				*base;
225	dma_addr_t			dev_base;
226	char				msix_name[QDMA_INTR_NAME_MAX_LEN];
227	u32				msix_vector;
228	u16				msix_id;
229	u32				ring_size;
230	u16				ridx;
231	u16				cidx;
232	u8				color;
233};
234
235#define QDMA_INTR_MASK_PIDX		GENMASK_ULL(15, 0)
236#define QDMA_INTR_MASK_CIDX		GENMASK_ULL(31, 16)
237#define QDMA_INTR_MASK_DESC_COLOR	GENMASK_ULL(32, 32)
238#define QDMA_INTR_MASK_STATE		GENMASK_ULL(34, 33)
239#define QDMA_INTR_MASK_ERROR		GENMASK_ULL(36, 35)
240#define QDMA_INTR_MASK_TYPE		GENMASK_ULL(38, 38)
241#define QDMA_INTR_MASK_QID		GENMASK_ULL(62, 39)
242#define QDMA_INTR_MASK_COLOR		GENMASK_ULL(63, 63)
243
244struct qdma_device {
245	struct platform_device		*pdev;
246	struct dma_device		dma_dev;
247	struct regmap			*regmap;
248	struct mutex			ctxt_lock; /* protect ctxt registers */
249	const struct qdma_reg_field	*rfields;
250	const struct qdma_reg		*roffs;
251	struct qdma_queue		*h2c_queues;
252	struct qdma_queue		*c2h_queues;
253	struct qdma_intr_ring		*qintr_rings;
254	u32				qintr_ring_num;
255	u32				qintr_ring_idx;
256	u32				chan_num;
257	u32				queue_irq_start;
258	u32				queue_irq_num;
259	u32				err_irq_idx;
260	u32				fid;
261};
262
263extern const struct qdma_reg qdma_regos_default[QDMA_REGO_MAX];
264extern const struct qdma_reg_field qdma_regfs_default[QDMA_REGF_MAX];
265
266#endif	/* __QDMA_H */