ae4dma.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * AMD AE4DMA driver
  4 *
  5 * Copyright (c) 2024, Advanced Micro Devices, Inc.
  6 * All Rights Reserved.
  7 *
  8 * Author: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
  9 */
 10#ifndef __AE4DMA_H__
 11#define __AE4DMA_H__
 12
 13#include <linux/device.h>
 14#include <linux/dmaengine.h>
 15#include <linux/dmapool.h>
 16#include <linux/list.h>
 17#include <linux/mutex.h>
 18#include <linux/pci.h>
 19#include <linux/spinlock.h>
 20#include <linux/wait.h>
 21
 22#include "../ptdma/ptdma.h"
 23#include "../../virt-dma.h"
 24
 25#define MAX_AE4_HW_QUEUES		16
 26
 27#define AE4_DESC_COMPLETED		0x03
 28
 29#define AE4_MAX_IDX_OFF			0x08
 30#define AE4_RD_IDX_OFF			0x0c
 31#define AE4_WR_IDX_OFF			0x10
 32#define AE4_INTR_STS_OFF		0x14
 33#define AE4_Q_BASE_L_OFF		0x18
 34#define AE4_Q_BASE_H_OFF		0x1c
 35#define AE4_Q_SZ			0x20
 36
 37#define AE4_DMA_VERSION			4
 38#define CMD_AE4_DESC_DW0_VAL		2
 39
 40#define AE4_TIME_OUT			5000
 41
 42struct ae4_msix {
 43	int msix_count;
 44	struct msix_entry msix_entry[MAX_AE4_HW_QUEUES];
 45};
 46
 47struct ae4_cmd_queue {
 48	struct ae4_device *ae4;
 49	struct pt_cmd_queue cmd_q;
 50	struct list_head cmd;
 51	/* protect command operations */
 52	struct mutex cmd_lock;
 53	struct delayed_work p_work;
 54	struct workqueue_struct *pws;
 55	struct completion cmp;
 56	wait_queue_head_t q_w;
 57	atomic64_t intr_cnt;
 58	atomic64_t done_cnt;
 59	u64 q_cmd_count;
 60	u32 dridx;
 61	u32 tail_wi;
 62	u32 id;
 63};
 64
 65union dwou {
 66	u32 dw0;
 67	struct dword0 {
 68	u8	byte0;
 69	u8	byte1;
 70	u16	timestamp;
 71	} dws;
 72};
 73
 74struct dword1 {
 75	u8	status;
 76	u8	err_code;
 77	u16	desc_id;
 78};
 79
 80struct ae4dma_desc {
 81	union dwou dwouv;
 82	struct dword1 dw1;
 83	u32 length;
 84	u32 rsvd;
 85	u32 src_hi;
 86	u32 src_lo;
 87	u32 dst_hi;
 88	u32 dst_lo;
 89};
 90
 91struct ae4_device {
 92	struct pt_device pt;
 93	struct ae4_msix *ae4_msix;
 94	struct ae4_cmd_queue ae4cmd_q[MAX_AE4_HW_QUEUES];
 95	unsigned int ae4_irq[MAX_AE4_HW_QUEUES];
 96	unsigned int cmd_q_count;
 97};
 98
 99int ae4_core_init(struct ae4_device *ae4);
100void ae4_destroy_work(struct ae4_device *ae4);
101void ae4_check_status_error(struct ae4_cmd_queue *ae4cmd_q, int idx);
102#endif