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trace.h
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linux-6.19.14/drivers/cxl/core/trace.h
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2022 Intel Corporation. All rights reserved. */ 3#undef TRACE_SYSTEM 4#define TRACE_SYSTEM cxl 5 6#if !defined(_CXL_EVENTS_H) || defined(TRACE_HEADER_MULTI_READ) 7#define _CXL_EVENTS_H 8 9#include <linux/tracepoint.h> 10#include <linux/pci.h> 11#include <linux/unaligned.h> 12 13#include <cxl.h> 14#include <cxlmem.h> 15#include "core.h" 16 17#define CXL_RAS_UC_CACHE_DATA_PARITY BIT(0) 18#define CXL_RAS_UC_CACHE_ADDR_PARITY BIT(1) 19#define CXL_RAS_UC_CACHE_BE_PARITY BIT(2) 20#define CXL_RAS_UC_CACHE_DATA_ECC BIT(3) 21#define CXL_RAS_UC_MEM_DATA_PARITY BIT(4) 22#define CXL_RAS_UC_MEM_ADDR_PARITY BIT(5) 23#define CXL_RAS_UC_MEM_BE_PARITY BIT(6) 24#define CXL_RAS_UC_MEM_DATA_ECC BIT(7) 25#define CXL_RAS_UC_REINIT_THRESH BIT(8) 26#define CXL_RAS_UC_RSVD_ENCODE BIT(9) 27#define CXL_RAS_UC_POISON BIT(10) 28#define CXL_RAS_UC_RECV_OVERFLOW BIT(11) 29#define CXL_RAS_UC_INTERNAL_ERR BIT(14) 30#define CXL_RAS_UC_IDE_TX_ERR BIT(15) 31#define CXL_RAS_UC_IDE_RX_ERR BIT(16) 32 33#define show_uc_errs(status) __print_flags(status, " | ", \ 34 { CXL_RAS_UC_CACHE_DATA_PARITY, "Cache Data Parity Error" }, \ 35 { CXL_RAS_UC_CACHE_ADDR_PARITY, "Cache Address Parity Error" }, \ 36 { CXL_RAS_UC_CACHE_BE_PARITY, "Cache Byte Enable Parity Error" }, \ 37 { CXL_RAS_UC_CACHE_DATA_ECC, "Cache Data ECC Error" }, \ 38 { CXL_RAS_UC_MEM_DATA_PARITY, "Memory Data Parity Error" }, \ 39 { CXL_RAS_UC_MEM_ADDR_PARITY, "Memory Address Parity Error" }, \ 40 { CXL_RAS_UC_MEM_BE_PARITY, "Memory Byte Enable Parity Error" }, \ 41 { CXL_RAS_UC_MEM_DATA_ECC, "Memory Data ECC Error" }, \ 42 { CXL_RAS_UC_REINIT_THRESH, "REINIT Threshold Hit" }, \ 43 { CXL_RAS_UC_RSVD_ENCODE, "Received Unrecognized Encoding" }, \ 44 { CXL_RAS_UC_POISON, "Received Poison From Peer" }, \ 45 { CXL_RAS_UC_RECV_OVERFLOW, "Receiver Overflow" }, \ 46 { CXL_RAS_UC_INTERNAL_ERR, "Component Specific Error" }, \ 47 { CXL_RAS_UC_IDE_TX_ERR, "IDE Tx Error" }, \ 48 { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ 49) 50 51TRACE_EVENT(cxl_port_aer_uncorrectable_error, 52 TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl), 53 TP_ARGS(dev, status, fe, hl), 54 TP_STRUCT__entry( 55 __string(device, dev_name(dev)) 56 __string(host, dev_name(dev->parent)) 57 __field(u32, status) 58 __field(u32, first_error) 59 __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) 60 ), 61 TP_fast_assign( 62 __assign_str(device); 63 __assign_str(host); 64 __entry->status = status; 65 __entry->first_error = fe; 66 /* 67 * Embed the 512B headerlog data for user app retrieval and 68 * parsing, but no need to print this in the trace buffer. 69 */ 70 memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); 71 ), 72 TP_printk("device=%s host=%s status: '%s' first_error: '%s'", 73 __get_str(device), __get_str(host), 74 show_uc_errs(__entry->status), 75 show_uc_errs(__entry->first_error) 76 ) 77); 78 79TRACE_EVENT(cxl_aer_uncorrectable_error, 80 TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), 81 TP_ARGS(cxlmd, status, fe, hl), 82 TP_STRUCT__entry( 83 __string(memdev, dev_name(&cxlmd->dev)) 84 __string(host, dev_name(cxlmd->dev.parent)) 85 __field(u64, serial) 86 __field(u32, status) 87 __field(u32, first_error) 88 __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) 89 ), 90 TP_fast_assign( 91 __assign_str(memdev); 92 __assign_str(host); 93 __entry->serial = cxlmd->cxlds->serial; 94 __entry->status = status; 95 __entry->first_error = fe; 96 /* 97 * Embed the 512B headerlog data for user app retrieval and 98 * parsing, but no need to print this in the trace buffer. 99 */ 100 memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); 101 ), 102 TP_printk("memdev=%s host=%s serial=%lld: status: '%s' first_error: '%s'", 103 __get_str(memdev), __get_str(host), __entry->serial, 104 show_uc_errs(__entry->status), 105 show_uc_errs(__entry->first_error) 106 ) 107); 108 109#define CXL_RAS_CE_CACHE_DATA_ECC BIT(0) 110#define CXL_RAS_CE_MEM_DATA_ECC BIT(1) 111#define CXL_RAS_CE_CRC_THRESH BIT(2) 112#define CLX_RAS_CE_RETRY_THRESH BIT(3) 113#define CXL_RAS_CE_CACHE_POISON BIT(4) 114#define CXL_RAS_CE_MEM_POISON BIT(5) 115#define CXL_RAS_CE_PHYS_LAYER_ERR BIT(6) 116 117#define show_ce_errs(status) __print_flags(status, " | ", \ 118 { CXL_RAS_CE_CACHE_DATA_ECC, "Cache Data ECC Error" }, \ 119 { CXL_RAS_CE_MEM_DATA_ECC, "Memory Data ECC Error" }, \ 120 { CXL_RAS_CE_CRC_THRESH, "CRC Threshold Hit" }, \ 121 { CLX_RAS_CE_RETRY_THRESH, "Retry Threshold" }, \ 122 { CXL_RAS_CE_CACHE_POISON, "Received Cache Poison From Peer" }, \ 123 { CXL_RAS_CE_MEM_POISON, "Received Memory Poison From Peer" }, \ 124 { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ 125) 126 127TRACE_EVENT(cxl_port_aer_correctable_error, 128 TP_PROTO(struct device *dev, u32 status), 129 TP_ARGS(dev, status), 130 TP_STRUCT__entry( 131 __string(device, dev_name(dev)) 132 __string(host, dev_name(dev->parent)) 133 __field(u32, status) 134 ), 135 TP_fast_assign( 136 __assign_str(device); 137 __assign_str(host); 138 __entry->status = status; 139 ), 140 TP_printk("device=%s host=%s status='%s'", 141 __get_str(device), __get_str(host), 142 show_ce_errs(__entry->status) 143 ) 144); 145 146TRACE_EVENT(cxl_aer_correctable_error, 147 TP_PROTO(const struct cxl_memdev *cxlmd, u32 status), 148 TP_ARGS(cxlmd, status), 149 TP_STRUCT__entry( 150 __string(memdev, dev_name(&cxlmd->dev)) 151 __string(host, dev_name(cxlmd->dev.parent)) 152 __field(u64, serial) 153 __field(u32, status) 154 ), 155 TP_fast_assign( 156 __assign_str(memdev); 157 __assign_str(host); 158 __entry->serial = cxlmd->cxlds->serial; 159 __entry->status = status; 160 ), 161 TP_printk("memdev=%s host=%s serial=%lld: status: '%s'", 162 __get_str(memdev), __get_str(host), __entry->serial, 163 show_ce_errs(__entry->status) 164 ) 165); 166 167#define cxl_event_log_type_str(type) \ 168 __print_symbolic(type, \ 169 { CXL_EVENT_TYPE_INFO, "Informational" }, \ 170 { CXL_EVENT_TYPE_WARN, "Warning" }, \ 171 { CXL_EVENT_TYPE_FAIL, "Failure" }, \ 172 { CXL_EVENT_TYPE_FATAL, "Fatal" }) 173 174TRACE_EVENT(cxl_overflow, 175 176 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 177 struct cxl_get_event_payload *payload), 178 179 TP_ARGS(cxlmd, log, payload), 180 181 TP_STRUCT__entry( 182 __string(memdev, dev_name(&cxlmd->dev)) 183 __string(host, dev_name(cxlmd->dev.parent)) 184 __field(int, log) 185 __field(u64, serial) 186 __field(u64, first_ts) 187 __field(u64, last_ts) 188 __field(u16, count) 189 ), 190 191 TP_fast_assign( 192 __assign_str(memdev); 193 __assign_str(host); 194 __entry->serial = cxlmd->cxlds->serial; 195 __entry->log = log; 196 __entry->count = le16_to_cpu(payload->overflow_err_count); 197 __entry->first_ts = le64_to_cpu(payload->first_overflow_timestamp); 198 __entry->last_ts = le64_to_cpu(payload->last_overflow_timestamp); 199 ), 200 201 TP_printk("memdev=%s host=%s serial=%lld: log=%s : %u records from %llu to %llu", 202 __get_str(memdev), __get_str(host), __entry->serial, 203 cxl_event_log_type_str(__entry->log), __entry->count, 204 __entry->first_ts, __entry->last_ts) 205 206); 207 208/* 209 * Common Event Record Format 210 * CXL 3.0 section 8.2.9.2.1; Table 8-42 211 */ 212#define CXL_EVENT_RECORD_FLAG_PERMANENT BIT(2) 213#define CXL_EVENT_RECORD_FLAG_MAINT_NEEDED BIT(3) 214#define CXL_EVENT_RECORD_FLAG_PERF_DEGRADED BIT(4) 215#define CXL_EVENT_RECORD_FLAG_HW_REPLACE BIT(5) 216#define CXL_EVENT_RECORD_FLAG_MAINT_OP_SUB_CLASS_VALID BIT(6) 217#define CXL_EVENT_RECORD_FLAG_LD_ID_VALID BIT(7) 218#define CXL_EVENT_RECORD_FLAG_HEAD_ID_VALID BIT(8) 219#define show_hdr_flags(flags) __print_flags(flags, " | ", \ 220 { CXL_EVENT_RECORD_FLAG_PERMANENT, "PERMANENT_CONDITION" }, \ 221 { CXL_EVENT_RECORD_FLAG_MAINT_NEEDED, "MAINTENANCE_NEEDED" }, \ 222 { CXL_EVENT_RECORD_FLAG_PERF_DEGRADED, "PERFORMANCE_DEGRADED" }, \ 223 { CXL_EVENT_RECORD_FLAG_HW_REPLACE, "HARDWARE_REPLACEMENT_NEEDED" }, \ 224 { CXL_EVENT_RECORD_FLAG_MAINT_OP_SUB_CLASS_VALID, "MAINT_OP_SUB_CLASS_VALID" }, \ 225 { CXL_EVENT_RECORD_FLAG_LD_ID_VALID, "LD_ID_VALID" }, \ 226 { CXL_EVENT_RECORD_FLAG_HEAD_ID_VALID, "HEAD_ID_VALID" } \ 227) 228 229/* 230 * Define macros for the common header of each CXL event. 231 * 232 * Tracepoints using these macros must do 3 things: 233 * 234 * 1) Add CXL_EVT_TP_entry to TP_STRUCT__entry 235 * 2) Use CXL_EVT_TP_fast_assign within TP_fast_assign; 236 * pass the dev, log, and CXL event header 237 * NOTE: The uuid must be assigned by the specific trace event 238 * 3) Use CXL_EVT_TP_printk() instead of TP_printk() 239 * 240 * See the generic_event tracepoint as an example. 241 */ 242#define CXL_EVT_TP_entry \ 243 __string(memdev, dev_name(&cxlmd->dev)) \ 244 __string(host, dev_name(cxlmd->dev.parent)) \ 245 __field(int, log) \ 246 __field_struct(uuid_t, hdr_uuid) \ 247 __field(u64, serial) \ 248 __field(u32, hdr_flags) \ 249 __field(u16, hdr_handle) \ 250 __field(u16, hdr_related_handle) \ 251 __field(u64, hdr_timestamp) \ 252 __field(u8, hdr_length) \ 253 __field(u8, hdr_maint_op_class) \ 254 __field(u8, hdr_maint_op_sub_class) \ 255 __field(u16, hdr_ld_id) \ 256 __field(u8, hdr_head_id) 257 258#define CXL_EVT_TP_fast_assign(cxlmd, l, hdr) \ 259 __assign_str(memdev); \ 260 __assign_str(host); \ 261 __entry->log = (l); \ 262 __entry->serial = (cxlmd)->cxlds->serial; \ 263 __entry->hdr_length = (hdr).length; \ 264 __entry->hdr_flags = get_unaligned_le24((hdr).flags); \ 265 __entry->hdr_handle = le16_to_cpu((hdr).handle); \ 266 __entry->hdr_related_handle = le16_to_cpu((hdr).related_handle); \ 267 __entry->hdr_timestamp = le64_to_cpu((hdr).timestamp); \ 268 __entry->hdr_maint_op_class = (hdr).maint_op_class; \ 269 __entry->hdr_maint_op_sub_class = (hdr).maint_op_sub_class; \ 270 __entry->hdr_ld_id = le16_to_cpu((hdr).ld_id); \ 271 __entry->hdr_head_id = (hdr).head_id 272 273#define CXL_EVT_TP_printk(fmt, ...) \ 274 TP_printk("memdev=%s host=%s serial=%lld log=%s : time=%llu uuid=%pUb " \ 275 "len=%d flags='%s' handle=%x related_handle=%x " \ 276 "maint_op_class=%u maint_op_sub_class=%u " \ 277 "ld_id=%x head_id=%x : " fmt, \ 278 __get_str(memdev), __get_str(host), __entry->serial, \ 279 cxl_event_log_type_str(__entry->log), \ 280 __entry->hdr_timestamp, &__entry->hdr_uuid, __entry->hdr_length,\ 281 show_hdr_flags(__entry->hdr_flags), __entry->hdr_handle, \ 282 __entry->hdr_related_handle, __entry->hdr_maint_op_class, \ 283 __entry->hdr_maint_op_sub_class, \ 284 __entry->hdr_ld_id, __entry->hdr_head_id, \ 285 ##__VA_ARGS__) 286 287TRACE_EVENT(cxl_generic_event, 288 289 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 290 const uuid_t *uuid, struct cxl_event_generic *gen_rec), 291 292 TP_ARGS(cxlmd, log, uuid, gen_rec), 293 294 TP_STRUCT__entry( 295 CXL_EVT_TP_entry 296 __array(u8, data, CXL_EVENT_RECORD_DATA_LENGTH) 297 ), 298 299 TP_fast_assign( 300 CXL_EVT_TP_fast_assign(cxlmd, log, gen_rec->hdr); 301 memcpy(&__entry->hdr_uuid, uuid, sizeof(uuid_t)); 302 memcpy(__entry->data, gen_rec->data, CXL_EVENT_RECORD_DATA_LENGTH); 303 ), 304 305 CXL_EVT_TP_printk("%s", 306 __print_hex(__entry->data, CXL_EVENT_RECORD_DATA_LENGTH)) 307); 308 309/* 310 * Physical Address field masks 311 * 312 * General Media Event Record 313 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 314 * 315 * DRAM Event Record 316 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 317 */ 318#define CXL_DPA_FLAGS_MASK GENMASK(1, 0) 319#define CXL_DPA_MASK GENMASK_ULL(63, 6) 320 321#define CXL_DPA_VOLATILE BIT(0) 322#define CXL_DPA_NOT_REPAIRABLE BIT(1) 323#define show_dpa_flags(flags) __print_flags(flags, "|", \ 324 { CXL_DPA_VOLATILE, "VOLATILE" }, \ 325 { CXL_DPA_NOT_REPAIRABLE, "NOT_REPAIRABLE" } \ 326) 327 328/* 329 * Component ID Format 330 * CXL 3.1 section 8.2.9.2.1; Table 8-44 331 */ 332#define CXL_PLDM_COMPONENT_ID_ENTITY_VALID BIT(0) 333#define CXL_PLDM_COMPONENT_ID_RES_VALID BIT(1) 334 335#define show_comp_id_pldm_flags(flags) __print_flags(flags, " | ", \ 336 { CXL_PLDM_COMPONENT_ID_ENTITY_VALID, "PLDM Entity ID" }, \ 337 { CXL_PLDM_COMPONENT_ID_RES_VALID, "Resource ID" } \ 338) 339 340#define show_pldm_entity_id(flags, valid_comp_id, valid_id_format, comp_id) \ 341 (flags & valid_comp_id && flags & valid_id_format) ? \ 342 (comp_id[0] & CXL_PLDM_COMPONENT_ID_ENTITY_VALID) ? \ 343 __print_hex(&comp_id[1], 6) : "0x00" : "0x00" 344 345#define show_pldm_resource_id(flags, valid_comp_id, valid_id_format, comp_id) \ 346 (flags & valid_comp_id && flags & valid_id_format) ? \ 347 (comp_id[0] & CXL_PLDM_COMPONENT_ID_RES_VALID) ? \ 348 __print_hex(&comp_id[7], 4) : "0x00" : "0x00" 349 350/* 351 * General Media Event Record - GMER 352 * CXL rev 3.1 Section 8.2.9.2.1.1; Table 8-45 353 */ 354#define CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT BIT(0) 355#define CXL_GMER_EVT_DESC_THRESHOLD_EVENT BIT(1) 356#define CXL_GMER_EVT_DESC_POISON_LIST_OVERFLOW BIT(2) 357#define show_event_desc_flags(flags) __print_flags(flags, "|", \ 358 { CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT, "UNCORRECTABLE_EVENT" }, \ 359 { CXL_GMER_EVT_DESC_THRESHOLD_EVENT, "THRESHOLD_EVENT" }, \ 360 { CXL_GMER_EVT_DESC_POISON_LIST_OVERFLOW, "POISON_LIST_OVERFLOW" } \ 361) 362 363#define CXL_GMER_MEM_EVT_TYPE_ECC_ERROR 0x00 364#define CXL_GMER_MEM_EVT_TYPE_INV_ADDR 0x01 365#define CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR 0x02 366#define CXL_GMER_MEM_EVT_TYPE_TE_STATE_VIOLATION 0x03 367#define CXL_GMER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR 0x04 368#define CXL_GMER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE 0x05 369#define CXL_GMER_MEM_EVT_TYPE_CKID_VIOLATION 0x06 370#define show_gmer_mem_event_type(type) __print_symbolic(type, \ 371 { CXL_GMER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \ 372 { CXL_GMER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \ 373 { CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" }, \ 374 { CXL_GMER_MEM_EVT_TYPE_TE_STATE_VIOLATION, "TE State Violation" }, \ 375 { CXL_GMER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR, "Scrub Media ECC Error" }, \ 376 { CXL_GMER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE, "Adv Prog CME Counter Expiration" }, \ 377 { CXL_GMER_MEM_EVT_TYPE_CKID_VIOLATION, "CKID Violation" } \ 378) 379 380#define CXL_GMER_TRANS_UNKNOWN 0x00 381#define CXL_GMER_TRANS_HOST_READ 0x01 382#define CXL_GMER_TRANS_HOST_WRITE 0x02 383#define CXL_GMER_TRANS_HOST_SCAN_MEDIA 0x03 384#define CXL_GMER_TRANS_HOST_INJECT_POISON 0x04 385#define CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB 0x05 386#define CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT 0x06 387#define CXL_GMER_TRANS_INTERNAL_MEDIA_ECS 0x07 388#define CXL_GMER_TRANS_MEDIA_INITIALIZATION 0x08 389#define show_trans_type(type) __print_symbolic(type, \ 390 { CXL_GMER_TRANS_UNKNOWN, "Unknown" }, \ 391 { CXL_GMER_TRANS_HOST_READ, "Host Read" }, \ 392 { CXL_GMER_TRANS_HOST_WRITE, "Host Write" }, \ 393 { CXL_GMER_TRANS_HOST_SCAN_MEDIA, "Host Scan Media" }, \ 394 { CXL_GMER_TRANS_HOST_INJECT_POISON, "Host Inject Poison" }, \ 395 { CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB, "Internal Media Scrub" }, \ 396 { CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT, "Internal Media Management" }, \ 397 { CXL_GMER_TRANS_INTERNAL_MEDIA_ECS, "Internal Media Error Check Scrub" }, \ 398 { CXL_GMER_TRANS_MEDIA_INITIALIZATION, "Media Initialization" } \ 399) 400 401#define CXL_GMER_VALID_CHANNEL BIT(0) 402#define CXL_GMER_VALID_RANK BIT(1) 403#define CXL_GMER_VALID_DEVICE BIT(2) 404#define CXL_GMER_VALID_COMPONENT BIT(3) 405#define CXL_GMER_VALID_COMPONENT_ID_FORMAT BIT(4) 406#define show_valid_flags(flags) __print_flags(flags, "|", \ 407 { CXL_GMER_VALID_CHANNEL, "CHANNEL" }, \ 408 { CXL_GMER_VALID_RANK, "RANK" }, \ 409 { CXL_GMER_VALID_DEVICE, "DEVICE" }, \ 410 { CXL_GMER_VALID_COMPONENT, "COMPONENT" }, \ 411 { CXL_GMER_VALID_COMPONENT_ID_FORMAT, "COMPONENT PLDM FORMAT" } \ 412) 413 414#define CXL_GMER_CME_EV_FLAG_CME_MULTIPLE_MEDIA BIT(0) 415#define CXL_GMER_CME_EV_FLAG_THRESHOLD_EXCEEDED BIT(1) 416#define show_cme_threshold_ev_flags(flags) __print_flags(flags, "|", \ 417 { \ 418 CXL_GMER_CME_EV_FLAG_CME_MULTIPLE_MEDIA, \ 419 "Corrected Memory Errors in Multiple Media Components" \ 420 }, { \ 421 CXL_GMER_CME_EV_FLAG_THRESHOLD_EXCEEDED, \ 422 "Exceeded Programmable Threshold" \ 423 } \ 424) 425 426#define CXL_GMER_MEM_EVT_SUB_TYPE_NOT_REPORTED 0x00 427#define CXL_GMER_MEM_EVT_SUB_TYPE_INTERNAL_DATAPATH_ERROR 0x01 428#define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_COMMAND_TRAINING_ERROR 0x02 429#define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CONTROL_TRAINING_ERROR 0x03 430#define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_DATA_TRAINING_ERROR 0x04 431#define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CRC_ERROR 0x05 432#define show_mem_event_sub_type(sub_type) __print_symbolic(sub_type, \ 433 { CXL_GMER_MEM_EVT_SUB_TYPE_NOT_REPORTED, "Not Reported" }, \ 434 { CXL_GMER_MEM_EVT_SUB_TYPE_INTERNAL_DATAPATH_ERROR, "Internal Datapath Error" }, \ 435 { \ 436 CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_COMMAND_TRAINING_ERROR, \ 437 "Media Link Command Training Error" \ 438 }, { \ 439 CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CONTROL_TRAINING_ERROR, \ 440 "Media Link Control Training Error" \ 441 }, { \ 442 CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_DATA_TRAINING_ERROR, \ 443 "Media Link Data Training Error" \ 444 }, { \ 445 CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CRC_ERROR, "Media Link CRC Error" \ 446 } \ 447) 448 449TRACE_EVENT(cxl_general_media, 450 451 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 452 struct cxl_region *cxlr, u64 hpa, u64 hpa_alias0, 453 struct cxl_event_gen_media *rec), 454 455 TP_ARGS(cxlmd, log, cxlr, hpa, hpa_alias0, rec), 456 457 TP_STRUCT__entry( 458 CXL_EVT_TP_entry 459 /* General Media */ 460 __field(u64, dpa) 461 __field(u8, descriptor) 462 __field(u8, type) 463 __field(u8, transaction_type) 464 __field(u8, channel) 465 __field(u32, device) 466 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) 467 /* Following are out of order to pack trace record */ 468 __field(u64, hpa) 469 __field(u64, hpa_alias0) 470 __field_struct(uuid_t, region_uuid) 471 __field(u16, validity_flags) 472 __field(u8, rank) 473 __field(u8, dpa_flags) 474 __field(u32, cme_count) 475 __field(u8, sub_type) 476 __field(u8, cme_threshold_ev_flags) 477 __string(region_name, cxlr ? dev_name(&cxlr->dev) : "") 478 ), 479 480 TP_fast_assign( 481 CXL_EVT_TP_fast_assign(cxlmd, log, rec->media_hdr.hdr); 482 __entry->hdr_uuid = CXL_EVENT_GEN_MEDIA_UUID; 483 484 /* General Media */ 485 __entry->dpa = le64_to_cpu(rec->media_hdr.phys_addr); 486 __entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK; 487 /* Mask after flags have been parsed */ 488 __entry->dpa &= CXL_DPA_MASK; 489 __entry->descriptor = rec->media_hdr.descriptor; 490 __entry->type = rec->media_hdr.type; 491 __entry->sub_type = rec->sub_type; 492 __entry->transaction_type = rec->media_hdr.transaction_type; 493 __entry->channel = rec->media_hdr.channel; 494 __entry->rank = rec->media_hdr.rank; 495 __entry->device = get_unaligned_le24(rec->device); 496 memcpy(__entry->comp_id, &rec->component_id, 497 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 498 __entry->validity_flags = get_unaligned_le16(&rec->media_hdr.validity_flags); 499 __entry->hpa = hpa; 500 __entry->hpa_alias0 = hpa_alias0; 501 if (cxlr) { 502 __assign_str(region_name); 503 uuid_copy(&__entry->region_uuid, &cxlr->params.uuid); 504 } else { 505 __assign_str(region_name); 506 uuid_copy(&__entry->region_uuid, &uuid_null); 507 } 508 __entry->cme_threshold_ev_flags = rec->cme_threshold_ev_flags; 509 if (rec->media_hdr.descriptor & CXL_GMER_EVT_DESC_THRESHOLD_EVENT) 510 __entry->cme_count = get_unaligned_le24(rec->cme_count); 511 else 512 __entry->cme_count = 0; 513 ), 514 515 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' " \ 516 "descriptor='%s' type='%s' sub_type='%s' " \ 517 "transaction_type='%s' channel=%u rank=%u " \ 518 "device=%x validity_flags='%s' " \ 519 "comp_id=%s comp_id_pldm_valid_flags='%s' " \ 520 "pldm_entity_id=%s pldm_resource_id=%s " \ 521 "hpa=%llx hpa_alias0=%llx region=%s region_uuid=%pUb " \ 522 "cme_threshold_ev_flags='%s' cme_count=%u", 523 __entry->dpa, show_dpa_flags(__entry->dpa_flags), 524 show_event_desc_flags(__entry->descriptor), 525 show_gmer_mem_event_type(__entry->type), 526 show_mem_event_sub_type(__entry->sub_type), 527 show_trans_type(__entry->transaction_type), 528 __entry->channel, __entry->rank, __entry->device, 529 show_valid_flags(__entry->validity_flags), 530 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), 531 show_comp_id_pldm_flags(__entry->comp_id[0]), 532 show_pldm_entity_id(__entry->validity_flags, CXL_GMER_VALID_COMPONENT, 533 CXL_GMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 534 show_pldm_resource_id(__entry->validity_flags, CXL_GMER_VALID_COMPONENT, 535 CXL_GMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 536 __entry->hpa, __entry->hpa_alias0, __get_str(region_name), &__entry->region_uuid, 537 show_cme_threshold_ev_flags(__entry->cme_threshold_ev_flags), __entry->cme_count 538 ) 539); 540 541/* 542 * DRAM Event Record - DER 543 * 544 * CXL rev 3.1 section 8.2.9.2.1.2; Table 8-46 545 */ 546/* 547 * DRAM Event Record defines many fields the same as the General Media Event 548 * Record. Reuse those definitions as appropriate. 549 */ 550#define CXL_DER_MEM_EVT_TYPE_ECC_ERROR 0x00 551#define CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR 0x01 552#define CXL_DER_MEM_EVT_TYPE_INV_ADDR 0x02 553#define CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR 0x03 554#define CXL_DER_MEM_EVT_TYPE_TE_STATE_VIOLATION 0x04 555#define CXL_DER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE 0x05 556#define CXL_DER_MEM_EVT_TYPE_CKID_VIOLATION 0x06 557#define show_dram_mem_event_type(type) __print_symbolic(type, \ 558 { CXL_DER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \ 559 { CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR, "Scrub Media ECC Error" }, \ 560 { CXL_DER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \ 561 { CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" }, \ 562 { CXL_DER_MEM_EVT_TYPE_TE_STATE_VIOLATION, "TE State Violation" }, \ 563 { CXL_DER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE, "Adv Prog CME Counter Expiration" }, \ 564 { CXL_DER_MEM_EVT_TYPE_CKID_VIOLATION, "CKID Violation" } \ 565) 566 567#define CXL_DER_VALID_CHANNEL BIT(0) 568#define CXL_DER_VALID_RANK BIT(1) 569#define CXL_DER_VALID_NIBBLE BIT(2) 570#define CXL_DER_VALID_BANK_GROUP BIT(3) 571#define CXL_DER_VALID_BANK BIT(4) 572#define CXL_DER_VALID_ROW BIT(5) 573#define CXL_DER_VALID_COLUMN BIT(6) 574#define CXL_DER_VALID_CORRECTION_MASK BIT(7) 575#define CXL_DER_VALID_COMPONENT BIT(8) 576#define CXL_DER_VALID_COMPONENT_ID_FORMAT BIT(9) 577#define CXL_DER_VALID_SUB_CHANNEL BIT(10) 578#define show_dram_valid_flags(flags) __print_flags(flags, "|", \ 579 { CXL_DER_VALID_CHANNEL, "CHANNEL" }, \ 580 { CXL_DER_VALID_RANK, "RANK" }, \ 581 { CXL_DER_VALID_NIBBLE, "NIBBLE" }, \ 582 { CXL_DER_VALID_BANK_GROUP, "BANK GROUP" }, \ 583 { CXL_DER_VALID_BANK, "BANK" }, \ 584 { CXL_DER_VALID_ROW, "ROW" }, \ 585 { CXL_DER_VALID_COLUMN, "COLUMN" }, \ 586 { CXL_DER_VALID_CORRECTION_MASK, "CORRECTION MASK" }, \ 587 { CXL_DER_VALID_COMPONENT, "COMPONENT" }, \ 588 { CXL_DER_VALID_COMPONENT_ID_FORMAT, "COMPONENT PLDM FORMAT" }, \ 589 { CXL_DER_VALID_SUB_CHANNEL, "SUB CHANNEL" } \ 590) 591 592TRACE_EVENT(cxl_dram, 593 594 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 595 struct cxl_region *cxlr, u64 hpa, u64 hpa_alias0, 596 struct cxl_event_dram *rec), 597 598 TP_ARGS(cxlmd, log, cxlr, hpa, hpa_alias0, rec), 599 600 TP_STRUCT__entry( 601 CXL_EVT_TP_entry 602 /* DRAM */ 603 __field(u64, dpa) 604 __field(u8, descriptor) 605 __field(u8, type) 606 __field(u8, transaction_type) 607 __field(u8, channel) 608 __field(u16, validity_flags) 609 __field(u16, column) /* Out of order to pack trace record */ 610 __field(u32, nibble_mask) 611 __field(u32, row) 612 __array(u8, cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE) 613 __field(u64, hpa) 614 __field(u64, hpa_alias0) 615 __field_struct(uuid_t, region_uuid) 616 __field(u8, rank) /* Out of order to pack trace record */ 617 __field(u8, bank_group) /* Out of order to pack trace record */ 618 __field(u8, bank) /* Out of order to pack trace record */ 619 __field(u8, dpa_flags) /* Out of order to pack trace record */ 620 /* Following are out of order to pack trace record */ 621 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) 622 __field(u32, cvme_count) 623 __field(u8, sub_type) 624 __field(u8, sub_channel) 625 __field(u8, cme_threshold_ev_flags) 626 __string(region_name, cxlr ? dev_name(&cxlr->dev) : "") 627 ), 628 629 TP_fast_assign( 630 CXL_EVT_TP_fast_assign(cxlmd, log, rec->media_hdr.hdr); 631 __entry->hdr_uuid = CXL_EVENT_DRAM_UUID; 632 633 /* DRAM */ 634 __entry->dpa = le64_to_cpu(rec->media_hdr.phys_addr); 635 __entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK; 636 __entry->dpa &= CXL_DPA_MASK; 637 __entry->descriptor = rec->media_hdr.descriptor; 638 __entry->type = rec->media_hdr.type; 639 __entry->sub_type = rec->sub_type; 640 __entry->transaction_type = rec->media_hdr.transaction_type; 641 __entry->validity_flags = get_unaligned_le16(rec->media_hdr.validity_flags); 642 __entry->channel = rec->media_hdr.channel; 643 __entry->rank = rec->media_hdr.rank; 644 __entry->nibble_mask = get_unaligned_le24(rec->nibble_mask); 645 __entry->bank_group = rec->bank_group; 646 __entry->bank = rec->bank; 647 __entry->row = get_unaligned_le24(rec->row); 648 __entry->column = get_unaligned_le16(rec->column); 649 memcpy(__entry->cor_mask, &rec->correction_mask, 650 CXL_EVENT_DER_CORRECTION_MASK_SIZE); 651 __entry->hpa = hpa; 652 __entry->hpa_alias0 = hpa_alias0; 653 if (cxlr) { 654 __assign_str(region_name); 655 uuid_copy(&__entry->region_uuid, &cxlr->params.uuid); 656 } else { 657 __assign_str(region_name); 658 uuid_copy(&__entry->region_uuid, &uuid_null); 659 } 660 memcpy(__entry->comp_id, &rec->component_id, 661 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 662 __entry->sub_channel = rec->sub_channel; 663 __entry->cme_threshold_ev_flags = rec->cme_threshold_ev_flags; 664 if (rec->media_hdr.descriptor & CXL_GMER_EVT_DESC_THRESHOLD_EVENT) 665 __entry->cvme_count = get_unaligned_le24(rec->cvme_count); 666 else 667 __entry->cvme_count = 0; 668 ), 669 670 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' descriptor='%s' type='%s' sub_type='%s' " \ 671 "transaction_type='%s' channel=%u rank=%u nibble_mask=%x " \ 672 "bank_group=%u bank=%u row=%u column=%u cor_mask=%s " \ 673 "validity_flags='%s' " \ 674 "comp_id=%s comp_id_pldm_valid_flags='%s' " \ 675 "pldm_entity_id=%s pldm_resource_id=%s " \ 676 "hpa=%llx hpa_alias0=%llx region=%s region_uuid=%pUb " \ 677 "sub_channel=%u cme_threshold_ev_flags='%s' cvme_count=%u", 678 __entry->dpa, show_dpa_flags(__entry->dpa_flags), 679 show_event_desc_flags(__entry->descriptor), 680 show_dram_mem_event_type(__entry->type), 681 show_mem_event_sub_type(__entry->sub_type), 682 show_trans_type(__entry->transaction_type), 683 __entry->channel, __entry->rank, __entry->nibble_mask, 684 __entry->bank_group, __entry->bank, 685 __entry->row, __entry->column, 686 __print_hex(__entry->cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE), 687 show_dram_valid_flags(__entry->validity_flags), 688 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), 689 show_comp_id_pldm_flags(__entry->comp_id[0]), 690 show_pldm_entity_id(__entry->validity_flags, CXL_DER_VALID_COMPONENT, 691 CXL_DER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 692 show_pldm_resource_id(__entry->validity_flags, CXL_DER_VALID_COMPONENT, 693 CXL_DER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 694 __entry->hpa, __entry->hpa_alias0, __get_str(region_name), &__entry->region_uuid, 695 __entry->sub_channel, show_cme_threshold_ev_flags(__entry->cme_threshold_ev_flags), 696 __entry->cvme_count 697 ) 698); 699 700/* 701 * Memory Module Event Record - MMER 702 * 703 * CXL res 3.1 section 8.2.9.2.1.3; Table 8-47 704 */ 705#define CXL_MMER_HEALTH_STATUS_CHANGE 0x00 706#define CXL_MMER_MEDIA_STATUS_CHANGE 0x01 707#define CXL_MMER_LIFE_USED_CHANGE 0x02 708#define CXL_MMER_TEMP_CHANGE 0x03 709#define CXL_MMER_DATA_PATH_ERROR 0x04 710#define CXL_MMER_LSA_ERROR 0x05 711#define CXL_MMER_UNRECOV_SIDEBAND_BUS_ERROR 0x06 712#define CXL_MMER_MEMORY_MEDIA_FRU_ERROR 0x07 713#define CXL_MMER_POWER_MANAGEMENT_FAULT 0x08 714#define show_dev_evt_type(type) __print_symbolic(type, \ 715 { CXL_MMER_HEALTH_STATUS_CHANGE, "Health Status Change" }, \ 716 { CXL_MMER_MEDIA_STATUS_CHANGE, "Media Status Change" }, \ 717 { CXL_MMER_LIFE_USED_CHANGE, "Life Used Change" }, \ 718 { CXL_MMER_TEMP_CHANGE, "Temperature Change" }, \ 719 { CXL_MMER_DATA_PATH_ERROR, "Data Path Error" }, \ 720 { CXL_MMER_LSA_ERROR, "LSA Error" }, \ 721 { CXL_MMER_UNRECOV_SIDEBAND_BUS_ERROR, "Unrecoverable Internal Sideband Bus Error" }, \ 722 { CXL_MMER_MEMORY_MEDIA_FRU_ERROR, "Memory Media FRU Error" }, \ 723 { CXL_MMER_POWER_MANAGEMENT_FAULT, "Power Management Fault" } \ 724) 725 726/* 727 * Device Health Information - DHI 728 * 729 * CXL res 3.1 section 8.2.9.9.3.1; Table 8-133 730 */ 731#define CXL_DHI_HS_MAINTENANCE_NEEDED BIT(0) 732#define CXL_DHI_HS_PERFORMANCE_DEGRADED BIT(1) 733#define CXL_DHI_HS_HW_REPLACEMENT_NEEDED BIT(2) 734#define CXL_DHI_HS_MEM_CAPACITY_DEGRADED BIT(3) 735#define show_health_status_flags(flags) __print_flags(flags, "|", \ 736 { CXL_DHI_HS_MAINTENANCE_NEEDED, "MAINTENANCE_NEEDED" }, \ 737 { CXL_DHI_HS_PERFORMANCE_DEGRADED, "PERFORMANCE_DEGRADED" }, \ 738 { CXL_DHI_HS_HW_REPLACEMENT_NEEDED, "REPLACEMENT_NEEDED" }, \ 739 { CXL_DHI_HS_MEM_CAPACITY_DEGRADED, "MEM_CAPACITY_DEGRADED" } \ 740) 741 742#define CXL_DHI_MS_NORMAL 0x00 743#define CXL_DHI_MS_NOT_READY 0x01 744#define CXL_DHI_MS_WRITE_PERSISTENCY_LOST 0x02 745#define CXL_DHI_MS_ALL_DATA_LOST 0x03 746#define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_POWER_LOSS 0x04 747#define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_SHUTDOWN 0x05 748#define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_IMMINENT 0x06 749#define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_POWER_LOSS 0x07 750#define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_SHUTDOWN 0x08 751#define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_IMMINENT 0x09 752#define show_media_status(ms) __print_symbolic(ms, \ 753 { CXL_DHI_MS_NORMAL, \ 754 "Normal" }, \ 755 { CXL_DHI_MS_NOT_READY, \ 756 "Not Ready" }, \ 757 { CXL_DHI_MS_WRITE_PERSISTENCY_LOST, \ 758 "Write Persistency Lost" }, \ 759 { CXL_DHI_MS_ALL_DATA_LOST, \ 760 "All Data Lost" }, \ 761 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_POWER_LOSS, \ 762 "Write Persistency Loss in the Event of Power Loss" }, \ 763 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_SHUTDOWN, \ 764 "Write Persistency Loss in Event of Shutdown" }, \ 765 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_IMMINENT, \ 766 "Write Persistency Loss Imminent" }, \ 767 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_POWER_LOSS, \ 768 "All Data Loss in Event of Power Loss" }, \ 769 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_SHUTDOWN, \ 770 "All Data loss in the Event of Shutdown" }, \ 771 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_IMMINENT, \ 772 "All Data Loss Imminent" } \ 773) 774 775#define CXL_DHI_AS_NORMAL 0x0 776#define CXL_DHI_AS_WARNING 0x1 777#define CXL_DHI_AS_CRITICAL 0x2 778#define show_two_bit_status(as) __print_symbolic(as, \ 779 { CXL_DHI_AS_NORMAL, "Normal" }, \ 780 { CXL_DHI_AS_WARNING, "Warning" }, \ 781 { CXL_DHI_AS_CRITICAL, "Critical" } \ 782) 783#define show_one_bit_status(as) __print_symbolic(as, \ 784 { CXL_DHI_AS_NORMAL, "Normal" }, \ 785 { CXL_DHI_AS_WARNING, "Warning" } \ 786) 787 788#define CXL_DHI_AS_LIFE_USED(as) (as & 0x3) 789#define CXL_DHI_AS_DEV_TEMP(as) ((as & 0xC) >> 2) 790#define CXL_DHI_AS_COR_VOL_ERR_CNT(as) ((as & 0x10) >> 4) 791#define CXL_DHI_AS_COR_PER_ERR_CNT(as) ((as & 0x20) >> 5) 792 793#define CXL_MMER_VALID_COMPONENT BIT(0) 794#define CXL_MMER_VALID_COMPONENT_ID_FORMAT BIT(1) 795#define show_mem_module_valid_flags(flags) __print_flags(flags, "|", \ 796 { CXL_MMER_VALID_COMPONENT, "COMPONENT" }, \ 797 { CXL_MMER_VALID_COMPONENT_ID_FORMAT, "COMPONENT PLDM FORMAT" } \ 798) 799#define CXL_MMER_DEV_EVT_SUB_TYPE_NOT_REPORTED 0x00 800#define CXL_MMER_DEV_EVT_SUB_TYPE_INVALID_CONFIG_DATA 0x01 801#define CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_CONFIG_DATA 0x02 802#define CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_MEM_MEDIA_FRU 0x03 803#define show_dev_event_sub_type(sub_type) __print_symbolic(sub_type, \ 804 { CXL_MMER_DEV_EVT_SUB_TYPE_NOT_REPORTED, "Not Reported" }, \ 805 { CXL_MMER_DEV_EVT_SUB_TYPE_INVALID_CONFIG_DATA, "Invalid Config Data" }, \ 806 { CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_CONFIG_DATA, "Unsupported Config Data" }, \ 807 { \ 808 CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_MEM_MEDIA_FRU, \ 809 "Unsupported Memory Media FRU" \ 810 } \ 811) 812 813TRACE_EVENT(cxl_memory_module, 814 815 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 816 struct cxl_event_mem_module *rec), 817 818 TP_ARGS(cxlmd, log, rec), 819 820 TP_STRUCT__entry( 821 CXL_EVT_TP_entry 822 823 /* Memory Module Event */ 824 __field(u8, event_type) 825 826 /* Device Health Info */ 827 __field(u8, health_status) 828 __field(u8, media_status) 829 __field(u8, life_used) 830 __field(u32, dirty_shutdown_cnt) 831 __field(u32, cor_vol_err_cnt) 832 __field(u32, cor_per_err_cnt) 833 __field(s16, device_temp) 834 __field(u8, add_status) 835 __field(u8, event_sub_type) 836 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) 837 __field(u16, validity_flags) 838 ), 839 840 TP_fast_assign( 841 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); 842 __entry->hdr_uuid = CXL_EVENT_MEM_MODULE_UUID; 843 844 /* Memory Module Event */ 845 __entry->event_type = rec->event_type; 846 __entry->event_sub_type = rec->event_sub_type; 847 848 /* Device Health Info */ 849 __entry->health_status = rec->info.health_status; 850 __entry->media_status = rec->info.media_status; 851 __entry->life_used = rec->info.life_used; 852 __entry->dirty_shutdown_cnt = get_unaligned_le32(rec->info.dirty_shutdown_cnt); 853 __entry->cor_vol_err_cnt = get_unaligned_le32(rec->info.cor_vol_err_cnt); 854 __entry->cor_per_err_cnt = get_unaligned_le32(rec->info.cor_per_err_cnt); 855 __entry->device_temp = get_unaligned_le16(rec->info.device_temp); 856 __entry->add_status = rec->info.add_status; 857 __entry->validity_flags = get_unaligned_le16(rec->validity_flags); 858 memcpy(__entry->comp_id, &rec->component_id, 859 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 860 ), 861 862 CXL_EVT_TP_printk("event_type='%s' event_sub_type='%s' health_status='%s' " \ 863 "media_status='%s' as_life_used=%s as_dev_temp=%s as_cor_vol_err_cnt=%s " \ 864 "as_cor_per_err_cnt=%s life_used=%u device_temp=%d " \ 865 "dirty_shutdown_cnt=%u cor_vol_err_cnt=%u cor_per_err_cnt=%u " \ 866 "validity_flags='%s' " \ 867 "comp_id=%s comp_id_pldm_valid_flags='%s' " \ 868 "pldm_entity_id=%s pldm_resource_id=%s", 869 show_dev_evt_type(__entry->event_type), 870 show_dev_event_sub_type(__entry->event_sub_type), 871 show_health_status_flags(__entry->health_status), 872 show_media_status(__entry->media_status), 873 show_two_bit_status(CXL_DHI_AS_LIFE_USED(__entry->add_status)), 874 show_two_bit_status(CXL_DHI_AS_DEV_TEMP(__entry->add_status)), 875 show_one_bit_status(CXL_DHI_AS_COR_VOL_ERR_CNT(__entry->add_status)), 876 show_one_bit_status(CXL_DHI_AS_COR_PER_ERR_CNT(__entry->add_status)), 877 __entry->life_used, __entry->device_temp, 878 __entry->dirty_shutdown_cnt, __entry->cor_vol_err_cnt, 879 __entry->cor_per_err_cnt, 880 show_mem_module_valid_flags(__entry->validity_flags), 881 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), 882 show_comp_id_pldm_flags(__entry->comp_id[0]), 883 show_pldm_entity_id(__entry->validity_flags, CXL_MMER_VALID_COMPONENT, 884 CXL_MMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 885 show_pldm_resource_id(__entry->validity_flags, CXL_MMER_VALID_COMPONENT, 886 CXL_MMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id) 887 ) 888); 889 890/* 891 * Memory Sparing Event Record - MSER 892 * 893 * CXL rev 3.2 section 8.2.10.2.1.4; Table 8-60 894 */ 895#define CXL_MSER_QUERY_RESOURCE_FLAG BIT(0) 896#define CXL_MSER_HARD_SPARING_FLAG BIT(1) 897#define CXL_MSER_DEV_INITED_FLAG BIT(2) 898#define show_mem_sparing_flags(flags) __print_flags(flags, "|", \ 899 { CXL_MSER_QUERY_RESOURCE_FLAG, "Query Resources" }, \ 900 { CXL_MSER_HARD_SPARING_FLAG, "Hard Sparing" }, \ 901 { CXL_MSER_DEV_INITED_FLAG, "Device Initiated Sparing" } \ 902) 903 904#define CXL_MSER_VALID_CHANNEL BIT(0) 905#define CXL_MSER_VALID_RANK BIT(1) 906#define CXL_MSER_VALID_NIBBLE BIT(2) 907#define CXL_MSER_VALID_BANK_GROUP BIT(3) 908#define CXL_MSER_VALID_BANK BIT(4) 909#define CXL_MSER_VALID_ROW BIT(5) 910#define CXL_MSER_VALID_COLUMN BIT(6) 911#define CXL_MSER_VALID_COMPONENT_ID BIT(7) 912#define CXL_MSER_VALID_COMPONENT_ID_FORMAT BIT(8) 913#define CXL_MSER_VALID_SUB_CHANNEL BIT(9) 914#define show_mem_sparing_valid_flags(flags) __print_flags(flags, "|", \ 915 { CXL_MSER_VALID_CHANNEL, "CHANNEL" }, \ 916 { CXL_MSER_VALID_RANK, "RANK" }, \ 917 { CXL_MSER_VALID_NIBBLE, "NIBBLE" }, \ 918 { CXL_MSER_VALID_BANK_GROUP, "BANK GROUP" }, \ 919 { CXL_MSER_VALID_BANK, "BANK" }, \ 920 { CXL_MSER_VALID_ROW, "ROW" }, \ 921 { CXL_MSER_VALID_COLUMN, "COLUMN" }, \ 922 { CXL_MSER_VALID_COMPONENT_ID, "COMPONENT ID" }, \ 923 { CXL_MSER_VALID_COMPONENT_ID_FORMAT, "COMPONENT ID PLDM FORMAT" }, \ 924 { CXL_MSER_VALID_SUB_CHANNEL, "SUB CHANNEL" } \ 925) 926 927TRACE_EVENT(cxl_memory_sparing, 928 929 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 930 struct cxl_event_mem_sparing *rec), 931 932 TP_ARGS(cxlmd, log, rec), 933 934 TP_STRUCT__entry( 935 CXL_EVT_TP_entry 936 937 /* Memory Sparing Event */ 938 __field(u8, flags) 939 __field(u8, result) 940 __field(u16, validity_flags) 941 __field(u16, res_avail) 942 __field(u8, channel) 943 __field(u8, rank) 944 __field(u32, nibble_mask) 945 __field(u8, bank_group) 946 __field(u8, bank) 947 __field(u32, row) 948 __field(u16, column) 949 __field(u8, sub_channel) 950 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) 951 ), 952 953 TP_fast_assign( 954 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); 955 __entry->hdr_uuid = CXL_EVENT_MEM_SPARING_UUID; 956 957 /* Memory Sparing Event */ 958 __entry->flags = rec->flags; 959 __entry->result = rec->result; 960 __entry->validity_flags = le16_to_cpu(rec->validity_flags); 961 __entry->res_avail = le16_to_cpu(rec->res_avail); 962 __entry->channel = rec->channel; 963 __entry->rank = rec->rank; 964 __entry->nibble_mask = get_unaligned_le24(rec->nibble_mask); 965 __entry->bank_group = rec->bank_group; 966 __entry->bank = rec->bank; 967 __entry->row = get_unaligned_le24(rec->row); 968 __entry->column = le16_to_cpu(rec->column); 969 __entry->sub_channel = rec->sub_channel; 970 memcpy(__entry->comp_id, &rec->component_id, 971 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 972 ), 973 974 CXL_EVT_TP_printk("flags='%s' result=%u validity_flags='%s' " \ 975 "spare resource avail=%u channel=%u rank=%u " \ 976 "nibble_mask=%x bank_group=%u bank=%u " \ 977 "row=%u column=%u sub_channel=%u " \ 978 "comp_id=%s comp_id_pldm_valid_flags='%s' " \ 979 "pldm_entity_id=%s pldm_resource_id=%s", 980 show_mem_sparing_flags(__entry->flags), 981 __entry->result, 982 show_mem_sparing_valid_flags(__entry->validity_flags), 983 __entry->res_avail, __entry->channel, __entry->rank, 984 __entry->nibble_mask, __entry->bank_group, __entry->bank, 985 __entry->row, __entry->column, __entry->sub_channel, 986 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), 987 show_comp_id_pldm_flags(__entry->comp_id[0]), 988 show_pldm_entity_id(__entry->validity_flags, CXL_MSER_VALID_COMPONENT_ID, 989 CXL_MSER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 990 show_pldm_resource_id(__entry->validity_flags, CXL_MSER_VALID_COMPONENT_ID, 991 CXL_MSER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id) 992 ) 993); 994 995#define show_poison_trace_type(type) \ 996 __print_symbolic(type, \ 997 { CXL_POISON_TRACE_LIST, "List" }, \ 998 { CXL_POISON_TRACE_INJECT, "Inject" }, \ 999 { CXL_POISON_TRACE_CLEAR, "Clear" }) 1000 1001#define __show_poison_source(source) \ 1002 __print_symbolic(source, \ 1003 { CXL_POISON_SOURCE_UNKNOWN, "Unknown" }, \ 1004 { CXL_POISON_SOURCE_EXTERNAL, "External" }, \ 1005 { CXL_POISON_SOURCE_INTERNAL, "Internal" }, \ 1006 { CXL_POISON_SOURCE_INJECTED, "Injected" }, \ 1007 { CXL_POISON_SOURCE_VENDOR, "Vendor" }) 1008 1009#define show_poison_source(source) \ 1010 (((source > CXL_POISON_SOURCE_INJECTED) && \ 1011 (source != CXL_POISON_SOURCE_VENDOR)) ? "Reserved" \ 1012 : __show_poison_source(source)) 1013 1014#define show_poison_flags(flags) \ 1015 __print_flags(flags, "|", \ 1016 { CXL_POISON_FLAG_MORE, "More" }, \ 1017 { CXL_POISON_FLAG_OVERFLOW, "Overflow" }, \ 1018 { CXL_POISON_FLAG_SCANNING, "Scanning" }) 1019 1020#define __cxl_poison_addr(record) \ 1021 (le64_to_cpu(record->address)) 1022#define cxl_poison_record_dpa(record) \ 1023 (__cxl_poison_addr(record) & CXL_POISON_START_MASK) 1024#define cxl_poison_record_source(record) \ 1025 (__cxl_poison_addr(record) & CXL_POISON_SOURCE_MASK) 1026#define cxl_poison_record_dpa_length(record) \ 1027 (le32_to_cpu(record->length) * CXL_POISON_LEN_MULT) 1028#define cxl_poison_overflow(flags, time) \ 1029 (flags & CXL_POISON_FLAG_OVERFLOW ? le64_to_cpu(time) : 0) 1030 1031TRACE_EVENT(cxl_poison, 1032 1033 TP_PROTO(struct cxl_memdev *cxlmd, struct cxl_region *cxlr, 1034 const struct cxl_poison_record *record, u8 flags, 1035 __le64 overflow_ts, enum cxl_poison_trace_type trace_type), 1036 1037 TP_ARGS(cxlmd, cxlr, record, flags, overflow_ts, trace_type), 1038 1039 TP_STRUCT__entry( 1040 __string(memdev, dev_name(&cxlmd->dev)) 1041 __string(host, dev_name(cxlmd->dev.parent)) 1042 __field(u64, serial) 1043 __field(u8, trace_type) 1044 __string(region, cxlr ? dev_name(&cxlr->dev) : "") 1045 __field(u64, overflow_ts) 1046 __field(u64, hpa) 1047 __field(u64, hpa_alias0) 1048 __field(u64, dpa) 1049 __field(u32, dpa_length) 1050 __array(char, uuid, 16) 1051 __field(u8, source) 1052 __field(u8, flags) 1053 ), 1054 1055 TP_fast_assign( 1056 __assign_str(memdev); 1057 __assign_str(host); 1058 __entry->serial = cxlmd->cxlds->serial; 1059 __entry->overflow_ts = cxl_poison_overflow(flags, overflow_ts); 1060 __entry->dpa = cxl_poison_record_dpa(record); 1061 __entry->dpa_length = cxl_poison_record_dpa_length(record); 1062 __entry->source = cxl_poison_record_source(record); 1063 __entry->trace_type = trace_type; 1064 __entry->flags = flags; 1065 if (cxlr) { 1066 __assign_str(region); 1067 memcpy(__entry->uuid, &cxlr->params.uuid, 16); 1068 __entry->hpa = cxl_dpa_to_hpa(cxlr, cxlmd, 1069 __entry->dpa); 1070 if (__entry->hpa != ULLONG_MAX && cxlr->params.cache_size) 1071 __entry->hpa_alias0 = __entry->hpa - 1072 cxlr->params.cache_size; 1073 else 1074 __entry->hpa_alias0 = ULLONG_MAX; 1075 } else { 1076 __assign_str(region); 1077 memset(__entry->uuid, 0, 16); 1078 __entry->hpa = ULLONG_MAX; 1079 __entry->hpa_alias0 = ULLONG_MAX; 1080 } 1081 ), 1082 1083 TP_printk("memdev=%s host=%s serial=%lld trace_type=%s region=%s " \ 1084 "region_uuid=%pU hpa=0x%llx hpa_alias0=0x%llx dpa=0x%llx " \ 1085 "dpa_length=0x%x source=%s flags=%s overflow_time=%llu", 1086 __get_str(memdev), 1087 __get_str(host), 1088 __entry->serial, 1089 show_poison_trace_type(__entry->trace_type), 1090 __get_str(region), 1091 __entry->uuid, 1092 __entry->hpa, 1093 __entry->hpa_alias0, 1094 __entry->dpa, 1095 __entry->dpa_length, 1096 show_poison_source(__entry->source), 1097 show_poison_flags(__entry->flags), 1098 __entry->overflow_ts 1099 ) 1100); 1101 1102#endif /* _CXL_EVENTS_H */ 1103 1104#define TRACE_INCLUDE_FILE trace 1105#include <trace/define_trace.h>
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