jh7110-cryp.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Cryptographic API.
  4 *
  5 * Support for StarFive hardware cryptographic engine.
  6 * Copyright (c) 2022 StarFive Technology
  7 *
  8 */
  9
 10#include <crypto/engine.h>
 11#include "jh7110-cryp.h"
 12#include <linux/clk.h>
 13#include <linux/completion.h>
 14#include <linux/err.h>
 15#include <linux/interrupt.h>
 16#include <linux/iopoll.h>
 17#include <linux/kernel.h>
 18#include <linux/mod_devicetable.h>
 19#include <linux/module.h>
 20#include <linux/platform_device.h>
 21#include <linux/pm_runtime.h>
 22#include <linux/reset.h>
 23#include <linux/spinlock.h>
 24
 25#define DRIVER_NAME             "jh7110-crypto"
 26
 27struct starfive_dev_list {
 28	struct list_head        dev_list;
 29	spinlock_t              lock; /* protect dev_list */
 30};
 31
 32static struct starfive_dev_list dev_list = {
 33	.dev_list = LIST_HEAD_INIT(dev_list.dev_list),
 34	.lock     = __SPIN_LOCK_UNLOCKED(dev_list.lock),
 35};
 36
 37struct starfive_cryp_dev *starfive_cryp_find_dev(struct starfive_cryp_ctx *ctx)
 38{
 39	struct starfive_cryp_dev *cryp = NULL, *tmp;
 40
 41	spin_lock_bh(&dev_list.lock);
 42	if (!ctx->cryp) {
 43		list_for_each_entry(tmp, &dev_list.dev_list, list) {
 44			cryp = tmp;
 45			break;
 46		}
 47		ctx->cryp = cryp;
 48	} else {
 49		cryp = ctx->cryp;
 50	}
 51
 52	spin_unlock_bh(&dev_list.lock);
 53
 54	return cryp;
 55}
 56
 57static u16 side_chan;
 58module_param(side_chan, ushort, 0);
 59MODULE_PARM_DESC(side_chan, "Enable side channel mitigation for AES module.\n"
 60			    "Enabling this feature will reduce speed performance.\n"
 61			    " 0 - Disabled\n"
 62			    " other - Enabled");
 63
 64static int starfive_dma_init(struct starfive_cryp_dev *cryp)
 65{
 66	dma_cap_mask_t mask;
 67
 68	dma_cap_zero(mask);
 69	dma_cap_set(DMA_SLAVE, mask);
 70
 71	cryp->tx = dma_request_chan(cryp->dev, "tx");
 72	if (IS_ERR(cryp->tx))
 73		return dev_err_probe(cryp->dev, PTR_ERR(cryp->tx),
 74				     "Error requesting tx dma channel.\n");
 75
 76	cryp->rx = dma_request_chan(cryp->dev, "rx");
 77	if (IS_ERR(cryp->rx)) {
 78		dma_release_channel(cryp->tx);
 79		return dev_err_probe(cryp->dev, PTR_ERR(cryp->rx),
 80				     "Error requesting rx dma channel.\n");
 81	}
 82
 83	return 0;
 84}
 85
 86static void starfive_dma_cleanup(struct starfive_cryp_dev *cryp)
 87{
 88	dma_release_channel(cryp->tx);
 89	dma_release_channel(cryp->rx);
 90}
 91
 92static int starfive_cryp_probe(struct platform_device *pdev)
 93{
 94	struct starfive_cryp_dev *cryp;
 95	struct resource *res;
 96	int ret;
 97
 98	cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL);
 99	if (!cryp)
100		return -ENOMEM;
101
102	platform_set_drvdata(pdev, cryp);
103	cryp->dev = &pdev->dev;
104
105	cryp->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
106	if (IS_ERR(cryp->base))
107		return dev_err_probe(&pdev->dev, PTR_ERR(cryp->base),
108				     "Error remapping memory for platform device\n");
109
110	cryp->phys_base = res->start;
111	cryp->dma_maxburst = 32;
112	cryp->side_chan = side_chan;
113
114	cryp->hclk = devm_clk_get(&pdev->dev, "hclk");
115	if (IS_ERR(cryp->hclk))
116		return dev_err_probe(&pdev->dev, PTR_ERR(cryp->hclk),
117				     "Error getting hardware reference clock\n");
118
119	cryp->ahb = devm_clk_get(&pdev->dev, "ahb");
120	if (IS_ERR(cryp->ahb))
121		return dev_err_probe(&pdev->dev, PTR_ERR(cryp->ahb),
122				     "Error getting ahb reference clock\n");
123
124	cryp->rst = devm_reset_control_get_shared(cryp->dev, NULL);
125	if (IS_ERR(cryp->rst))
126		return dev_err_probe(&pdev->dev, PTR_ERR(cryp->rst),
127				     "Error getting hardware reset line\n");
128
129	clk_prepare_enable(cryp->hclk);
130	clk_prepare_enable(cryp->ahb);
131	reset_control_deassert(cryp->rst);
132
133	spin_lock(&dev_list.lock);
134	list_add(&cryp->list, &dev_list.dev_list);
135	spin_unlock(&dev_list.lock);
136
137	ret = starfive_dma_init(cryp);
138	if (ret)
139		goto err_dma_init;
140
141	/* Initialize crypto engine */
142	cryp->engine = crypto_engine_alloc_init(&pdev->dev, 1);
143	if (!cryp->engine) {
144		ret = -ENOMEM;
145		goto err_engine;
146	}
147
148	ret = crypto_engine_start(cryp->engine);
149	if (ret)
150		goto err_engine_start;
151
152	ret = starfive_aes_register_algs();
153	if (ret)
154		goto err_engine_start;
155
156	ret = starfive_hash_register_algs();
157	if (ret)
158		goto err_algs_hash;
159
160	ret = starfive_rsa_register_algs();
161	if (ret)
162		goto err_algs_rsa;
163
164	return 0;
165
166err_algs_rsa:
167	starfive_hash_unregister_algs();
168err_algs_hash:
169	starfive_aes_unregister_algs();
170err_engine_start:
171	crypto_engine_exit(cryp->engine);
172err_engine:
173	starfive_dma_cleanup(cryp);
174err_dma_init:
175	spin_lock(&dev_list.lock);
176	list_del(&cryp->list);
177	spin_unlock(&dev_list.lock);
178
179	clk_disable_unprepare(cryp->hclk);
180	clk_disable_unprepare(cryp->ahb);
181	reset_control_assert(cryp->rst);
182
183	return ret;
184}
185
186static void starfive_cryp_remove(struct platform_device *pdev)
187{
188	struct starfive_cryp_dev *cryp = platform_get_drvdata(pdev);
189
190	starfive_aes_unregister_algs();
191	starfive_hash_unregister_algs();
192	starfive_rsa_unregister_algs();
193
194	crypto_engine_exit(cryp->engine);
195
196	starfive_dma_cleanup(cryp);
197
198	spin_lock(&dev_list.lock);
199	list_del(&cryp->list);
200	spin_unlock(&dev_list.lock);
201
202	clk_disable_unprepare(cryp->hclk);
203	clk_disable_unprepare(cryp->ahb);
204	reset_control_assert(cryp->rst);
205}
206
207static const struct of_device_id starfive_dt_ids[] __maybe_unused = {
208	{ .compatible = "starfive,jh7110-crypto", .data = NULL},
209	{},
210};
211MODULE_DEVICE_TABLE(of, starfive_dt_ids);
212
213static struct platform_driver starfive_cryp_driver = {
214	.probe  = starfive_cryp_probe,
215	.remove = starfive_cryp_remove,
216	.driver = {
217		.name           = DRIVER_NAME,
218		.of_match_table = starfive_dt_ids,
219	},
220};
221
222module_platform_driver(starfive_cryp_driver);
223
224MODULE_LICENSE("GPL");
225MODULE_DESCRIPTION("StarFive JH7110 Cryptographic Module");