omap-sham.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Cryptographic API.
   4 *
   5 * Support for OMAP SHA1/MD5 HW acceleration.
   6 *
   7 * Copyright (c) 2010 Nokia Corporation
   8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   9 * Copyright (c) 2011 Texas Instruments Incorporated
  10 *
  11 * Some ideas are from old omap-sha1-md5.c driver.
  12 */
  13
  14#define pr_fmt(fmt) "%s: " fmt, __func__
  15
  16#include <crypto/engine.h>
  17#include <crypto/hmac.h>
  18#include <crypto/internal/hash.h>
  19#include <crypto/scatterwalk.h>
  20#include <crypto/sha1.h>
  21#include <crypto/sha2.h>
  22#include <linux/err.h>
  23#include <linux/device.h>
  24#include <linux/dma-mapping.h>
  25#include <linux/dmaengine.h>
  26#include <linux/init.h>
  27#include <linux/interrupt.h>
  28#include <linux/io.h>
  29#include <linux/irq.h>
  30#include <linux/kernel.h>
  31#include <linux/module.h>
  32#include <linux/of.h>
  33#include <linux/of_address.h>
  34#include <linux/of_irq.h>
  35#include <linux/platform_device.h>
  36#include <linux/pm_runtime.h>
  37#include <linux/scatterlist.h>
  38#include <linux/slab.h>
  39#include <linux/string.h>
  40#include <linux/workqueue.h>
  41
  42#define MD5_DIGEST_SIZE			16
  43
  44#define SHA_REG_IDIGEST(dd, x)		((dd)->pdata->idigest_ofs + ((x)*0x04))
  45#define SHA_REG_DIN(dd, x)		((dd)->pdata->din_ofs + ((x) * 0x04))
  46#define SHA_REG_DIGCNT(dd)		((dd)->pdata->digcnt_ofs)
  47
  48#define SHA_REG_ODIGEST(dd, x)		((dd)->pdata->odigest_ofs + (x * 0x04))
  49
  50#define SHA_REG_CTRL			0x18
  51#define SHA_REG_CTRL_LENGTH		(0xFFFFFFFF << 5)
  52#define SHA_REG_CTRL_CLOSE_HASH		(1 << 4)
  53#define SHA_REG_CTRL_ALGO_CONST		(1 << 3)
  54#define SHA_REG_CTRL_ALGO		(1 << 2)
  55#define SHA_REG_CTRL_INPUT_READY	(1 << 1)
  56#define SHA_REG_CTRL_OUTPUT_READY	(1 << 0)
  57
  58#define SHA_REG_REV(dd)			((dd)->pdata->rev_ofs)
  59
  60#define SHA_REG_MASK(dd)		((dd)->pdata->mask_ofs)
  61#define SHA_REG_MASK_DMA_EN		(1 << 3)
  62#define SHA_REG_MASK_IT_EN		(1 << 2)
  63#define SHA_REG_MASK_SOFTRESET		(1 << 1)
  64#define SHA_REG_AUTOIDLE		(1 << 0)
  65
  66#define SHA_REG_SYSSTATUS(dd)		((dd)->pdata->sysstatus_ofs)
  67#define SHA_REG_SYSSTATUS_RESETDONE	(1 << 0)
  68
  69#define SHA_REG_MODE(dd)		((dd)->pdata->mode_ofs)
  70#define SHA_REG_MODE_HMAC_OUTER_HASH	(1 << 7)
  71#define SHA_REG_MODE_HMAC_KEY_PROC	(1 << 5)
  72#define SHA_REG_MODE_CLOSE_HASH		(1 << 4)
  73#define SHA_REG_MODE_ALGO_CONSTANT	(1 << 3)
  74
  75#define SHA_REG_MODE_ALGO_MASK		(7 << 0)
  76#define SHA_REG_MODE_ALGO_MD5_128	(0 << 1)
  77#define SHA_REG_MODE_ALGO_SHA1_160	(1 << 1)
  78#define SHA_REG_MODE_ALGO_SHA2_224	(2 << 1)
  79#define SHA_REG_MODE_ALGO_SHA2_256	(3 << 1)
  80#define SHA_REG_MODE_ALGO_SHA2_384	(1 << 0)
  81#define SHA_REG_MODE_ALGO_SHA2_512	(3 << 0)
  82
  83#define SHA_REG_LENGTH(dd)		((dd)->pdata->length_ofs)
  84
  85#define SHA_REG_IRQSTATUS		0x118
  86#define SHA_REG_IRQSTATUS_CTX_RDY	(1 << 3)
  87#define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  88#define SHA_REG_IRQSTATUS_INPUT_RDY	(1 << 1)
  89#define SHA_REG_IRQSTATUS_OUTPUT_RDY	(1 << 0)
  90
  91#define SHA_REG_IRQENA			0x11C
  92#define SHA_REG_IRQENA_CTX_RDY		(1 << 3)
  93#define SHA_REG_IRQENA_PARTHASH_RDY	(1 << 2)
  94#define SHA_REG_IRQENA_INPUT_RDY	(1 << 1)
  95#define SHA_REG_IRQENA_OUTPUT_RDY	(1 << 0)
  96
  97#define DEFAULT_TIMEOUT_INTERVAL	HZ
  98
  99#define DEFAULT_AUTOSUSPEND_DELAY	1000
 100
 101/* mostly device flags */
 102#define FLAGS_FINAL		1
 103#define FLAGS_DMA_ACTIVE	2
 104#define FLAGS_OUTPUT_READY	3
 105#define FLAGS_CPU		5
 106#define FLAGS_DMA_READY		6
 107#define FLAGS_AUTO_XOR		7
 108#define FLAGS_BE32_SHA1		8
 109#define FLAGS_SGS_COPIED	9
 110#define FLAGS_SGS_ALLOCED	10
 111#define FLAGS_HUGE		11
 112
 113/* context flags */
 114#define FLAGS_FINUP		16
 115
 116#define FLAGS_MODE_SHIFT	18
 117#define FLAGS_MODE_MASK		(SHA_REG_MODE_ALGO_MASK	<< FLAGS_MODE_SHIFT)
 118#define FLAGS_MODE_MD5		(SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 119#define FLAGS_MODE_SHA1		(SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 120#define FLAGS_MODE_SHA224	(SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 121#define FLAGS_MODE_SHA256	(SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 122#define FLAGS_MODE_SHA384	(SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 123#define FLAGS_MODE_SHA512	(SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 124
 125#define FLAGS_HMAC		21
 126#define FLAGS_ERROR		22
 127
 128#define OP_UPDATE		1
 129#define OP_FINAL		2
 130
 131#define OMAP_ALIGN_MASK		(sizeof(u32)-1)
 132#define OMAP_ALIGNED		__attribute__((aligned(sizeof(u32))))
 133
 134#define BUFLEN			SHA512_BLOCK_SIZE
 135#define OMAP_SHA_DMA_THRESHOLD	256
 136
 137#define OMAP_SHA_MAX_DMA_LEN	(1024 * 2048)
 138
 139struct omap_sham_dev;
 140
 141struct omap_sham_reqctx {
 142	struct omap_sham_dev	*dd;
 143	unsigned long		flags;
 144	u8			op;
 145
 146	u8			digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 147	size_t			digcnt;
 148	size_t			bufcnt;
 149	size_t			buflen;
 150
 151	/* walk state */
 152	struct scatterlist	*sg;
 153	struct scatterlist	sgl[2];
 154	int			offset;	/* offset in current sg */
 155	int			sg_len;
 156	unsigned int		total;	/* total request */
 157
 158	u8			buffer[] OMAP_ALIGNED;
 159};
 160
 161struct omap_sham_hmac_ctx {
 162	struct crypto_shash	*shash;
 163	u8			ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 164	u8			opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 165};
 166
 167struct omap_sham_ctx {
 168	unsigned long		flags;
 169
 170	/* fallback stuff */
 171	struct crypto_shash	*fallback;
 172
 173	struct omap_sham_hmac_ctx base[];
 174};
 175
 176#define OMAP_SHAM_QUEUE_LENGTH	10
 177
 178struct omap_sham_algs_info {
 179	struct ahash_engine_alg	*algs_list;
 180	unsigned int		size;
 181	unsigned int		registered;
 182};
 183
 184struct omap_sham_pdata {
 185	struct omap_sham_algs_info	*algs_info;
 186	unsigned int	algs_info_size;
 187	unsigned long	flags;
 188	int		digest_size;
 189
 190	void		(*copy_hash)(struct ahash_request *req, int out);
 191	void		(*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 192				      int final, int dma);
 193	void		(*trigger)(struct omap_sham_dev *dd, size_t length);
 194	int		(*poll_irq)(struct omap_sham_dev *dd);
 195	irqreturn_t	(*intr_hdlr)(int irq, void *dev_id);
 196
 197	u32		odigest_ofs;
 198	u32		idigest_ofs;
 199	u32		din_ofs;
 200	u32		digcnt_ofs;
 201	u32		rev_ofs;
 202	u32		mask_ofs;
 203	u32		sysstatus_ofs;
 204	u32		mode_ofs;
 205	u32		length_ofs;
 206
 207	u32		major_mask;
 208	u32		major_shift;
 209	u32		minor_mask;
 210	u32		minor_shift;
 211};
 212
 213struct omap_sham_dev {
 214	struct list_head	list;
 215	unsigned long		phys_base;
 216	struct device		*dev;
 217	void __iomem		*io_base;
 218	int			irq;
 219	int			err;
 220	struct dma_chan		*dma_lch;
 221	struct work_struct	done_task;
 222	u8			polling_mode;
 223	u8			xmit_buf[BUFLEN] OMAP_ALIGNED;
 224
 225	unsigned long		flags;
 226	int			fallback_sz;
 227	struct crypto_queue	queue;
 228	struct ahash_request	*req;
 229	struct crypto_engine	*engine;
 230
 231	const struct omap_sham_pdata	*pdata;
 232};
 233
 234struct omap_sham_drv {
 235	struct list_head	dev_list;
 236	spinlock_t		lock;
 237	unsigned long		flags;
 238};
 239
 240static struct omap_sham_drv sham = {
 241	.dev_list = LIST_HEAD_INIT(sham.dev_list),
 242	.lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 243};
 244
 245static int omap_sham_enqueue(struct ahash_request *req, unsigned int op);
 246static void omap_sham_finish_req(struct ahash_request *req, int err);
 247
 248static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 249{
 250	return __raw_readl(dd->io_base + offset);
 251}
 252
 253static inline void omap_sham_write(struct omap_sham_dev *dd,
 254					u32 offset, u32 value)
 255{
 256	__raw_writel(value, dd->io_base + offset);
 257}
 258
 259static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 260					u32 value, u32 mask)
 261{
 262	u32 val;
 263
 264	val = omap_sham_read(dd, address);
 265	val &= ~mask;
 266	val |= value;
 267	omap_sham_write(dd, address, val);
 268}
 269
 270static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 271{
 272	unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 273
 274	while (!(omap_sham_read(dd, offset) & bit)) {
 275		if (time_is_before_jiffies(timeout))
 276			return -ETIMEDOUT;
 277	}
 278
 279	return 0;
 280}
 281
 282static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 283{
 284	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 285	struct omap_sham_dev *dd = ctx->dd;
 286	u32 *hash = (u32 *)ctx->digest;
 287	int i;
 288
 289	for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 290		if (out)
 291			hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 292		else
 293			omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 294	}
 295}
 296
 297static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 298{
 299	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 300	struct omap_sham_dev *dd = ctx->dd;
 301	int i;
 302
 303	if (ctx->flags & BIT(FLAGS_HMAC)) {
 304		struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 305		struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 306		struct omap_sham_hmac_ctx *bctx = tctx->base;
 307		u32 *opad = (u32 *)bctx->opad;
 308
 309		for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 310			if (out)
 311				opad[i] = omap_sham_read(dd,
 312						SHA_REG_ODIGEST(dd, i));
 313			else
 314				omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 315						opad[i]);
 316		}
 317	}
 318
 319	omap_sham_copy_hash_omap2(req, out);
 320}
 321
 322static void omap_sham_copy_ready_hash(struct ahash_request *req)
 323{
 324	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 325	u32 *in = (u32 *)ctx->digest;
 326	u32 *hash = (u32 *)req->result;
 327	int i, d, big_endian = 0;
 328
 329	if (!hash)
 330		return;
 331
 332	switch (ctx->flags & FLAGS_MODE_MASK) {
 333	case FLAGS_MODE_MD5:
 334		d = MD5_DIGEST_SIZE / sizeof(u32);
 335		break;
 336	case FLAGS_MODE_SHA1:
 337		/* OMAP2 SHA1 is big endian */
 338		if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 339			big_endian = 1;
 340		d = SHA1_DIGEST_SIZE / sizeof(u32);
 341		break;
 342	case FLAGS_MODE_SHA224:
 343		d = SHA224_DIGEST_SIZE / sizeof(u32);
 344		break;
 345	case FLAGS_MODE_SHA256:
 346		d = SHA256_DIGEST_SIZE / sizeof(u32);
 347		break;
 348	case FLAGS_MODE_SHA384:
 349		d = SHA384_DIGEST_SIZE / sizeof(u32);
 350		break;
 351	case FLAGS_MODE_SHA512:
 352		d = SHA512_DIGEST_SIZE / sizeof(u32);
 353		break;
 354	default:
 355		d = 0;
 356	}
 357
 358	if (big_endian)
 359		for (i = 0; i < d; i++)
 360			put_unaligned(be32_to_cpup((__be32 *)in + i), &hash[i]);
 361	else
 362		for (i = 0; i < d; i++)
 363			put_unaligned(le32_to_cpup((__le32 *)in + i), &hash[i]);
 364}
 365
 366static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 367				 int final, int dma)
 368{
 369	struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 370	u32 val = length << 5, mask;
 371
 372	if (likely(ctx->digcnt))
 373		omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 374
 375	omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 376		SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 377		SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 378	/*
 379	 * Setting ALGO_CONST only for the first iteration
 380	 * and CLOSE_HASH only for the last one.
 381	 */
 382	if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 383		val |= SHA_REG_CTRL_ALGO;
 384	if (!ctx->digcnt)
 385		val |= SHA_REG_CTRL_ALGO_CONST;
 386	if (final)
 387		val |= SHA_REG_CTRL_CLOSE_HASH;
 388
 389	mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 390			SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 391
 392	omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 393}
 394
 395static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 396{
 397}
 398
 399static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 400{
 401	return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 402}
 403
 404static int get_block_size(struct omap_sham_reqctx *ctx)
 405{
 406	int d;
 407
 408	switch (ctx->flags & FLAGS_MODE_MASK) {
 409	case FLAGS_MODE_MD5:
 410	case FLAGS_MODE_SHA1:
 411		d = SHA1_BLOCK_SIZE;
 412		break;
 413	case FLAGS_MODE_SHA224:
 414	case FLAGS_MODE_SHA256:
 415		d = SHA256_BLOCK_SIZE;
 416		break;
 417	case FLAGS_MODE_SHA384:
 418	case FLAGS_MODE_SHA512:
 419		d = SHA512_BLOCK_SIZE;
 420		break;
 421	default:
 422		d = 0;
 423	}
 424
 425	return d;
 426}
 427
 428static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 429				    u32 *value, int count)
 430{
 431	for (; count--; value++, offset += 4)
 432		omap_sham_write(dd, offset, *value);
 433}
 434
 435static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 436				 int final, int dma)
 437{
 438	struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 439	u32 val, mask;
 440
 441	if (likely(ctx->digcnt))
 442		omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 443
 444	/*
 445	 * Setting ALGO_CONST only for the first iteration and
 446	 * CLOSE_HASH only for the last one. Note that flags mode bits
 447	 * correspond to algorithm encoding in mode register.
 448	 */
 449	val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 450	if (!ctx->digcnt) {
 451		struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 452		struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 453		struct omap_sham_hmac_ctx *bctx = tctx->base;
 454		int bs, nr_dr;
 455
 456		val |= SHA_REG_MODE_ALGO_CONSTANT;
 457
 458		if (ctx->flags & BIT(FLAGS_HMAC)) {
 459			bs = get_block_size(ctx);
 460			nr_dr = bs / (2 * sizeof(u32));
 461			val |= SHA_REG_MODE_HMAC_KEY_PROC;
 462			omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 463					  (u32 *)bctx->ipad, nr_dr);
 464			omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 465					  (u32 *)bctx->ipad + nr_dr, nr_dr);
 466			ctx->digcnt += bs;
 467		}
 468	}
 469
 470	if (final) {
 471		val |= SHA_REG_MODE_CLOSE_HASH;
 472
 473		if (ctx->flags & BIT(FLAGS_HMAC))
 474			val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 475	}
 476
 477	mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 478	       SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 479	       SHA_REG_MODE_HMAC_KEY_PROC;
 480
 481	dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 482	omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 483	omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 484	omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 485			     SHA_REG_MASK_IT_EN |
 486				     (dma ? SHA_REG_MASK_DMA_EN : 0),
 487			     SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 488}
 489
 490static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 491{
 492	omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 493}
 494
 495static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 496{
 497	return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 498			      SHA_REG_IRQSTATUS_INPUT_RDY);
 499}
 500
 501static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
 502			      int final)
 503{
 504	struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 505	int count, len32, bs32, offset = 0;
 506	const u32 *buffer;
 507	int mlen;
 508	struct sg_mapping_iter mi;
 509
 510	dev_dbg(dd->dev, "xmit_cpu: digcnt: %zd, length: %zd, final: %d\n",
 511						ctx->digcnt, length, final);
 512
 513	dd->pdata->write_ctrl(dd, length, final, 0);
 514	dd->pdata->trigger(dd, length);
 515
 516	/* should be non-zero before next lines to disable clocks later */
 517	ctx->digcnt += length;
 518	ctx->total -= length;
 519
 520	if (final)
 521		set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 522
 523	set_bit(FLAGS_CPU, &dd->flags);
 524
 525	len32 = DIV_ROUND_UP(length, sizeof(u32));
 526	bs32 = get_block_size(ctx) / sizeof(u32);
 527
 528	sg_miter_start(&mi, ctx->sg, ctx->sg_len,
 529		       SG_MITER_FROM_SG | SG_MITER_ATOMIC);
 530
 531	mlen = 0;
 532
 533	while (len32) {
 534		if (dd->pdata->poll_irq(dd))
 535			return -ETIMEDOUT;
 536
 537		for (count = 0; count < min(len32, bs32); count++, offset++) {
 538			if (!mlen) {
 539				sg_miter_next(&mi);
 540				mlen = mi.length;
 541				if (!mlen) {
 542					pr_err("sg miter failure.\n");
 543					return -EINVAL;
 544				}
 545				offset = 0;
 546				buffer = mi.addr;
 547			}
 548			omap_sham_write(dd, SHA_REG_DIN(dd, count),
 549					buffer[offset]);
 550			mlen -= 4;
 551		}
 552		len32 -= min(len32, bs32);
 553	}
 554
 555	sg_miter_stop(&mi);
 556
 557	return -EINPROGRESS;
 558}
 559
 560static void omap_sham_dma_callback(void *param)
 561{
 562	struct omap_sham_dev *dd = param;
 563
 564	set_bit(FLAGS_DMA_READY, &dd->flags);
 565	queue_work(system_bh_wq, &dd->done_task);
 566}
 567
 568static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
 569			      int final)
 570{
 571	struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 572	struct dma_async_tx_descriptor *tx;
 573	struct dma_slave_config cfg;
 574	int ret;
 575
 576	dev_dbg(dd->dev, "xmit_dma: digcnt: %zd, length: %zd, final: %d\n",
 577						ctx->digcnt, length, final);
 578
 579	if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
 580		dev_err(dd->dev, "dma_map_sg error\n");
 581		return -EINVAL;
 582	}
 583
 584	memset(&cfg, 0, sizeof(cfg));
 585
 586	cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 587	cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 588	cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
 589
 590	ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 591	if (ret) {
 592		pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 593		return ret;
 594	}
 595
 596	tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
 597				     DMA_MEM_TO_DEV,
 598				     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 599
 600	if (!tx) {
 601		dev_err(dd->dev, "prep_slave_sg failed\n");
 602		return -EINVAL;
 603	}
 604
 605	tx->callback = omap_sham_dma_callback;
 606	tx->callback_param = dd;
 607
 608	dd->pdata->write_ctrl(dd, length, final, 1);
 609
 610	ctx->digcnt += length;
 611	ctx->total -= length;
 612
 613	if (final)
 614		set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 615
 616	set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 617
 618	dmaengine_submit(tx);
 619	dma_async_issue_pending(dd->dma_lch);
 620
 621	dd->pdata->trigger(dd, length);
 622
 623	return -EINPROGRESS;
 624}
 625
 626static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
 627				   struct scatterlist *sg, int bs, int new_len)
 628{
 629	int n = sg_nents(sg);
 630	struct scatterlist *tmp;
 631	int offset = ctx->offset;
 632
 633	ctx->total = new_len;
 634
 635	if (ctx->bufcnt)
 636		n++;
 637
 638	ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
 639	if (!ctx->sg)
 640		return -ENOMEM;
 641
 642	sg_init_table(ctx->sg, n);
 643
 644	tmp = ctx->sg;
 645
 646	ctx->sg_len = 0;
 647
 648	if (ctx->bufcnt) {
 649		sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
 650		tmp = sg_next(tmp);
 651		ctx->sg_len++;
 652		new_len -= ctx->bufcnt;
 653	}
 654
 655	while (sg && new_len) {
 656		int len = sg->length - offset;
 657
 658		if (len <= 0) {
 659			offset -= sg->length;
 660			sg = sg_next(sg);
 661			continue;
 662		}
 663
 664		if (new_len < len)
 665			len = new_len;
 666
 667		if (len > 0) {
 668			new_len -= len;
 669			sg_set_page(tmp, sg_page(sg), len, sg->offset + offset);
 670			offset = 0;
 671			ctx->offset = 0;
 672			ctx->sg_len++;
 673			if (new_len <= 0)
 674				break;
 675			tmp = sg_next(tmp);
 676		}
 677
 678		sg = sg_next(sg);
 679	}
 680
 681	if (tmp)
 682		sg_mark_end(tmp);
 683
 684	set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
 685
 686	ctx->offset += new_len - ctx->bufcnt;
 687	ctx->bufcnt = 0;
 688
 689	return 0;
 690}
 691
 692static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
 693			      struct scatterlist *sg, int bs,
 694			      unsigned int new_len)
 695{
 696	int pages;
 697	void *buf;
 698
 699	pages = get_order(new_len);
 700
 701	buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
 702	if (!buf) {
 703		pr_err("Couldn't allocate pages for unaligned cases.\n");
 704		return -ENOMEM;
 705	}
 706
 707	if (ctx->bufcnt)
 708		memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
 709
 710	scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
 711				 min(new_len, ctx->total) - ctx->bufcnt, 0);
 712	sg_init_table(ctx->sgl, 1);
 713	sg_set_buf(ctx->sgl, buf, new_len);
 714	ctx->sg = ctx->sgl;
 715	set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
 716	ctx->sg_len = 1;
 717	ctx->offset += new_len - ctx->bufcnt;
 718	ctx->bufcnt = 0;
 719	ctx->total = new_len;
 720
 721	return 0;
 722}
 723
 724static int omap_sham_align_sgs(struct scatterlist *sg,
 725			       int nbytes, int bs, bool final,
 726			       struct omap_sham_reqctx *rctx)
 727{
 728	int n = 0;
 729	bool aligned = true;
 730	bool list_ok = true;
 731	struct scatterlist *sg_tmp = sg;
 732	int new_len;
 733	int offset = rctx->offset;
 734	int bufcnt = rctx->bufcnt;
 735
 736	if (!sg || !sg->length || !nbytes) {
 737		if (bufcnt) {
 738			bufcnt = DIV_ROUND_UP(bufcnt, bs) * bs;
 739			sg_init_table(rctx->sgl, 1);
 740			sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, bufcnt);
 741			rctx->sg = rctx->sgl;
 742			rctx->sg_len = 1;
 743		}
 744
 745		return 0;
 746	}
 747
 748	new_len = nbytes;
 749
 750	if (offset)
 751		list_ok = false;
 752
 753	if (final)
 754		new_len = DIV_ROUND_UP(new_len, bs) * bs;
 755	else
 756		new_len = (new_len - 1) / bs * bs;
 757
 758	if (!new_len)
 759		return 0;
 760
 761	if (nbytes != new_len)
 762		list_ok = false;
 763
 764	while (nbytes > 0 && sg_tmp) {
 765		n++;
 766
 767		if (bufcnt) {
 768			if (!IS_ALIGNED(bufcnt, bs)) {
 769				aligned = false;
 770				break;
 771			}
 772			nbytes -= bufcnt;
 773			bufcnt = 0;
 774			if (!nbytes)
 775				list_ok = false;
 776
 777			continue;
 778		}
 779
 780#ifdef CONFIG_ZONE_DMA
 781		if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
 782			aligned = false;
 783			break;
 784		}
 785#endif
 786
 787		if (offset < sg_tmp->length) {
 788			if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
 789				aligned = false;
 790				break;
 791			}
 792
 793			if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
 794				aligned = false;
 795				break;
 796			}
 797		}
 798
 799		if (offset) {
 800			offset -= sg_tmp->length;
 801			if (offset < 0) {
 802				nbytes += offset;
 803				offset = 0;
 804			}
 805		} else {
 806			nbytes -= sg_tmp->length;
 807		}
 808
 809		sg_tmp = sg_next(sg_tmp);
 810
 811		if (nbytes < 0) {
 812			list_ok = false;
 813			break;
 814		}
 815	}
 816
 817	if (new_len > OMAP_SHA_MAX_DMA_LEN) {
 818		new_len = OMAP_SHA_MAX_DMA_LEN;
 819		aligned = false;
 820	}
 821
 822	if (!aligned)
 823		return omap_sham_copy_sgs(rctx, sg, bs, new_len);
 824	else if (!list_ok)
 825		return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
 826
 827	rctx->total = new_len;
 828	rctx->offset += new_len;
 829	rctx->sg_len = n;
 830	if (rctx->bufcnt) {
 831		sg_init_table(rctx->sgl, 2);
 832		sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
 833		sg_chain(rctx->sgl, 2, sg);
 834		rctx->sg = rctx->sgl;
 835	} else {
 836		rctx->sg = sg;
 837	}
 838
 839	return 0;
 840}
 841
 842static int omap_sham_prepare_request(struct crypto_engine *engine, void *areq)
 843{
 844	struct ahash_request *req = container_of(areq, struct ahash_request,
 845						 base);
 846	struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
 847	int bs;
 848	int ret;
 849	unsigned int nbytes;
 850	bool final = rctx->flags & BIT(FLAGS_FINUP);
 851	bool update = rctx->op == OP_UPDATE;
 852	int hash_later;
 853
 854	bs = get_block_size(rctx);
 855
 856	nbytes = rctx->bufcnt;
 857
 858	if (update)
 859		nbytes += req->nbytes - rctx->offset;
 860
 861	dev_dbg(rctx->dd->dev,
 862		"%s: nbytes=%d, bs=%d, total=%d, offset=%d, bufcnt=%zd\n",
 863		__func__, nbytes, bs, rctx->total, rctx->offset,
 864		rctx->bufcnt);
 865
 866	if (!nbytes)
 867		return 0;
 868
 869	rctx->total = nbytes;
 870
 871	if (update && req->nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
 872		int len = bs - rctx->bufcnt % bs;
 873
 874		if (len > req->nbytes)
 875			len = req->nbytes;
 876		scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
 877					 0, len, 0);
 878		rctx->bufcnt += len;
 879		rctx->offset = len;
 880	}
 881
 882	if (rctx->bufcnt)
 883		memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
 884
 885	ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
 886	if (ret)
 887		return ret;
 888
 889	hash_later = nbytes - rctx->total;
 890	if (hash_later < 0)
 891		hash_later = 0;
 892
 893	if (hash_later && hash_later <= rctx->buflen) {
 894		scatterwalk_map_and_copy(rctx->buffer,
 895					 req->src,
 896					 req->nbytes - hash_later,
 897					 hash_later, 0);
 898
 899		rctx->bufcnt = hash_later;
 900	} else {
 901		rctx->bufcnt = 0;
 902	}
 903
 904	if (hash_later > rctx->buflen)
 905		set_bit(FLAGS_HUGE, &rctx->dd->flags);
 906
 907	rctx->total = min(nbytes, rctx->total);
 908
 909	return 0;
 910}
 911
 912static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 913{
 914	struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 915
 916	dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
 917
 918	clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 919
 920	return 0;
 921}
 922
 923static struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx)
 924{
 925	struct omap_sham_dev *dd;
 926
 927	if (ctx->dd)
 928		return ctx->dd;
 929
 930	spin_lock_bh(&sham.lock);
 931	dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list);
 932	list_move_tail(&dd->list, &sham.dev_list);
 933	ctx->dd = dd;
 934	spin_unlock_bh(&sham.lock);
 935
 936	return dd;
 937}
 938
 939static int omap_sham_init(struct ahash_request *req)
 940{
 941	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 942	struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 943	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 944	struct omap_sham_dev *dd;
 945	int bs = 0;
 946
 947	ctx->dd = NULL;
 948
 949	dd = omap_sham_find_dev(ctx);
 950	if (!dd)
 951		return -ENODEV;
 952
 953	ctx->flags = 0;
 954
 955	dev_dbg(dd->dev, "init: digest size: %d\n",
 956		crypto_ahash_digestsize(tfm));
 957
 958	switch (crypto_ahash_digestsize(tfm)) {
 959	case MD5_DIGEST_SIZE:
 960		ctx->flags |= FLAGS_MODE_MD5;
 961		bs = SHA1_BLOCK_SIZE;
 962		break;
 963	case SHA1_DIGEST_SIZE:
 964		ctx->flags |= FLAGS_MODE_SHA1;
 965		bs = SHA1_BLOCK_SIZE;
 966		break;
 967	case SHA224_DIGEST_SIZE:
 968		ctx->flags |= FLAGS_MODE_SHA224;
 969		bs = SHA224_BLOCK_SIZE;
 970		break;
 971	case SHA256_DIGEST_SIZE:
 972		ctx->flags |= FLAGS_MODE_SHA256;
 973		bs = SHA256_BLOCK_SIZE;
 974		break;
 975	case SHA384_DIGEST_SIZE:
 976		ctx->flags |= FLAGS_MODE_SHA384;
 977		bs = SHA384_BLOCK_SIZE;
 978		break;
 979	case SHA512_DIGEST_SIZE:
 980		ctx->flags |= FLAGS_MODE_SHA512;
 981		bs = SHA512_BLOCK_SIZE;
 982		break;
 983	}
 984
 985	ctx->bufcnt = 0;
 986	ctx->digcnt = 0;
 987	ctx->total = 0;
 988	ctx->offset = 0;
 989	ctx->buflen = BUFLEN;
 990
 991	if (tctx->flags & BIT(FLAGS_HMAC)) {
 992		if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 993			struct omap_sham_hmac_ctx *bctx = tctx->base;
 994
 995			memcpy(ctx->buffer, bctx->ipad, bs);
 996			ctx->bufcnt = bs;
 997		}
 998
 999		ctx->flags |= BIT(FLAGS_HMAC);
1000	}
1001
1002	return 0;
1003
1004}
1005
1006static int omap_sham_update_req(struct omap_sham_dev *dd)
1007{
1008	struct ahash_request *req = dd->req;
1009	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1010	int err;
1011	bool final = (ctx->flags & BIT(FLAGS_FINUP)) &&
1012		!(dd->flags & BIT(FLAGS_HUGE));
1013
1014	dev_dbg(dd->dev, "update_req: total: %u, digcnt: %zd, final: %d",
1015		ctx->total, ctx->digcnt, final);
1016
1017	if (ctx->total < get_block_size(ctx) ||
1018	    ctx->total < dd->fallback_sz)
1019		ctx->flags |= BIT(FLAGS_CPU);
1020
1021	if (ctx->flags & BIT(FLAGS_CPU))
1022		err = omap_sham_xmit_cpu(dd, ctx->total, final);
1023	else
1024		err = omap_sham_xmit_dma(dd, ctx->total, final);
1025
1026	/* wait for dma completion before can take more data */
1027	dev_dbg(dd->dev, "update: err: %d, digcnt: %zd\n", err, ctx->digcnt);
1028
1029	return err;
1030}
1031
1032static int omap_sham_final_req(struct omap_sham_dev *dd)
1033{
1034	struct ahash_request *req = dd->req;
1035	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1036	int err = 0, use_dma = 1;
1037
1038	if (dd->flags & BIT(FLAGS_HUGE))
1039		return 0;
1040
1041	if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1042		/*
1043		 * faster to handle last block with cpu or
1044		 * use cpu when dma is not present.
1045		 */
1046		use_dma = 0;
1047
1048	if (use_dma)
1049		err = omap_sham_xmit_dma(dd, ctx->total, 1);
1050	else
1051		err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1052
1053	ctx->bufcnt = 0;
1054
1055	dev_dbg(dd->dev, "final_req: err: %d\n", err);
1056
1057	return err;
1058}
1059
1060static int omap_sham_hash_one_req(struct crypto_engine *engine, void *areq)
1061{
1062	struct ahash_request *req = container_of(areq, struct ahash_request,
1063						 base);
1064	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1065	struct omap_sham_dev *dd = ctx->dd;
1066	int err;
1067	bool final = (ctx->flags & BIT(FLAGS_FINUP)) &&
1068			!(dd->flags & BIT(FLAGS_HUGE));
1069
1070	dev_dbg(dd->dev, "hash-one: op: %u, total: %u, digcnt: %zd, final: %d",
1071		ctx->op, ctx->total, ctx->digcnt, final);
1072
1073	err = omap_sham_prepare_request(engine, areq);
1074	if (err)
1075		return err;
1076
1077	err = pm_runtime_resume_and_get(dd->dev);
1078	if (err < 0) {
1079		dev_err(dd->dev, "failed to get sync: %d\n", err);
1080		return err;
1081	}
1082
1083	dd->err = 0;
1084	dd->req = req;
1085
1086	if (ctx->digcnt)
1087		dd->pdata->copy_hash(req, 0);
1088
1089	if (ctx->op == OP_UPDATE)
1090		err = omap_sham_update_req(dd);
1091	else if (ctx->op == OP_FINAL)
1092		err = omap_sham_final_req(dd);
1093
1094	if (err != -EINPROGRESS)
1095		omap_sham_finish_req(req, err);
1096
1097	return 0;
1098}
1099
1100static int omap_sham_finish_hmac(struct ahash_request *req)
1101{
1102	struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1103	struct omap_sham_hmac_ctx *bctx = tctx->base;
1104	int bs = crypto_shash_blocksize(bctx->shash);
1105	int ds = crypto_shash_digestsize(bctx->shash);
1106	SHASH_DESC_ON_STACK(shash, bctx->shash);
1107
1108	shash->tfm = bctx->shash;
1109
1110	return crypto_shash_init(shash) ?:
1111	       crypto_shash_update(shash, bctx->opad, bs) ?:
1112	       crypto_shash_finup(shash, req->result, ds, req->result);
1113}
1114
1115static int omap_sham_finish(struct ahash_request *req)
1116{
1117	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1118	struct omap_sham_dev *dd = ctx->dd;
1119	int err = 0;
1120
1121	if (ctx->digcnt) {
1122		omap_sham_copy_ready_hash(req);
1123		if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1124				!test_bit(FLAGS_AUTO_XOR, &dd->flags))
1125			err = omap_sham_finish_hmac(req);
1126	}
1127
1128	dev_dbg(dd->dev, "digcnt: %zd, bufcnt: %zd\n", ctx->digcnt, ctx->bufcnt);
1129
1130	return err;
1131}
1132
1133static void omap_sham_finish_req(struct ahash_request *req, int err)
1134{
1135	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1136	struct omap_sham_dev *dd = ctx->dd;
1137
1138	if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1139		free_pages((unsigned long)sg_virt(ctx->sg),
1140			   get_order(ctx->sg->length));
1141
1142	if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1143		kfree(ctx->sg);
1144
1145	ctx->sg = NULL;
1146
1147	dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED) |
1148		       BIT(FLAGS_CPU) | BIT(FLAGS_DMA_READY) |
1149		       BIT(FLAGS_OUTPUT_READY));
1150
1151	if (!err)
1152		dd->pdata->copy_hash(req, 1);
1153
1154	if (dd->flags & BIT(FLAGS_HUGE)) {
1155		/* Re-enqueue the request */
1156		omap_sham_enqueue(req, ctx->op);
1157		return;
1158	}
1159
1160	if (!err) {
1161		if (test_bit(FLAGS_FINAL, &dd->flags))
1162			err = omap_sham_finish(req);
1163	} else {
1164		ctx->flags |= BIT(FLAGS_ERROR);
1165	}
1166
1167	/* atomic operation is not needed here */
1168	dd->flags &= ~(BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1169			BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1170
1171	pm_runtime_put_autosuspend(dd->dev);
1172
1173	ctx->offset = 0;
1174
1175	crypto_finalize_hash_request(dd->engine, req, err);
1176}
1177
1178static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1179				  struct ahash_request *req)
1180{
1181	return crypto_transfer_hash_request_to_engine(dd->engine, req);
1182}
1183
1184static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1185{
1186	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1187	struct omap_sham_dev *dd = ctx->dd;
1188
1189	ctx->op = op;
1190
1191	return omap_sham_handle_queue(dd, req);
1192}
1193
1194static int omap_sham_update(struct ahash_request *req)
1195{
1196	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1197	struct omap_sham_dev *dd = omap_sham_find_dev(ctx);
1198
1199	if (!req->nbytes)
1200		return 0;
1201
1202	if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1203		scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1204					 0, req->nbytes, 0);
1205		ctx->bufcnt += req->nbytes;
1206		return 0;
1207	}
1208
1209	if (dd->polling_mode)
1210		ctx->flags |= BIT(FLAGS_CPU);
1211
1212	return omap_sham_enqueue(req, OP_UPDATE);
1213}
1214
1215static int omap_sham_final_shash(struct ahash_request *req)
1216{
1217	struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1218	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1219	int offset = 0;
1220
1221	/*
1222	 * If we are running HMAC on limited hardware support, skip
1223	 * the ipad in the beginning of the buffer if we are going for
1224	 * software fallback algorithm.
1225	 */
1226	if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1227	    !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1228		offset = get_block_size(ctx);
1229
1230	return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer + offset,
1231				       ctx->bufcnt - offset, req->result);
1232}
1233
1234static int omap_sham_final(struct ahash_request *req)
1235{
1236	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1237
1238	ctx->flags |= BIT(FLAGS_FINUP);
1239
1240	if (ctx->flags & BIT(FLAGS_ERROR))
1241		return 0; /* uncompleted hash is not needed */
1242
1243	/*
1244	 * OMAP HW accel works only with buffers >= 9.
1245	 * HMAC is always >= 9 because ipad == block size.
1246	 * If buffersize is less than fallback_sz, we use fallback
1247	 * SW encoding, as using DMA + HW in this case doesn't provide
1248	 * any benefit.
1249	 */
1250	if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz)
1251		return omap_sham_final_shash(req);
1252	else if (ctx->bufcnt)
1253		return omap_sham_enqueue(req, OP_FINAL);
1254
1255	/* copy ready hash (+ finalize hmac) */
1256	return omap_sham_finish(req);
1257}
1258
1259static int omap_sham_finup(struct ahash_request *req)
1260{
1261	struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1262	int err1, err2;
1263
1264	ctx->flags |= BIT(FLAGS_FINUP);
1265
1266	err1 = omap_sham_update(req);
1267	if (err1 == -EINPROGRESS || err1 == -EBUSY)
1268		return err1;
1269	/*
1270	 * final() has to be always called to cleanup resources
1271	 * even if udpate() failed, except EINPROGRESS
1272	 */
1273	err2 = omap_sham_final(req);
1274
1275	return err1 ?: err2;
1276}
1277
1278static int omap_sham_digest(struct ahash_request *req)
1279{
1280	return omap_sham_init(req) ?: omap_sham_finup(req);
1281}
1282
1283static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1284		      unsigned int keylen)
1285{
1286	struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1287	struct omap_sham_hmac_ctx *bctx = tctx->base;
1288	int bs = crypto_shash_blocksize(bctx->shash);
1289	int ds = crypto_shash_digestsize(bctx->shash);
1290	int err, i;
1291
1292	err = crypto_shash_setkey(tctx->fallback, key, keylen);
1293	if (err)
1294		return err;
1295
1296	if (keylen > bs) {
1297		err = crypto_shash_tfm_digest(bctx->shash, key, keylen,
1298					      bctx->ipad);
1299		if (err)
1300			return err;
1301		keylen = ds;
1302	} else {
1303		memcpy(bctx->ipad, key, keylen);
1304	}
1305
1306	memset(bctx->ipad + keylen, 0, bs - keylen);
1307
1308	if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) {
1309		memcpy(bctx->opad, bctx->ipad, bs);
1310
1311		for (i = 0; i < bs; i++) {
1312			bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1313			bctx->opad[i] ^= HMAC_OPAD_VALUE;
1314		}
1315	}
1316
1317	return err;
1318}
1319
1320static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1321{
1322	struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1323	const char *alg_name = crypto_tfm_alg_name(tfm);
1324
1325	/* Allocate a fallback and abort if it failed. */
1326	tctx->fallback = crypto_alloc_shash(alg_name, 0,
1327					    CRYPTO_ALG_NEED_FALLBACK);
1328	if (IS_ERR(tctx->fallback)) {
1329		pr_err("omap-sham: fallback driver '%s' "
1330				"could not be loaded.\n", alg_name);
1331		return PTR_ERR(tctx->fallback);
1332	}
1333
1334	crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1335				 sizeof(struct omap_sham_reqctx) + BUFLEN);
1336
1337	if (alg_base) {
1338		struct omap_sham_hmac_ctx *bctx = tctx->base;
1339		tctx->flags |= BIT(FLAGS_HMAC);
1340		bctx->shash = crypto_alloc_shash(alg_base, 0,
1341						CRYPTO_ALG_NEED_FALLBACK);
1342		if (IS_ERR(bctx->shash)) {
1343			pr_err("omap-sham: base driver '%s' "
1344					"could not be loaded.\n", alg_base);
1345			crypto_free_shash(tctx->fallback);
1346			return PTR_ERR(bctx->shash);
1347		}
1348
1349	}
1350
1351	return 0;
1352}
1353
1354static int omap_sham_cra_init(struct crypto_tfm *tfm)
1355{
1356	return omap_sham_cra_init_alg(tfm, NULL);
1357}
1358
1359static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1360{
1361	return omap_sham_cra_init_alg(tfm, "sha1");
1362}
1363
1364static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1365{
1366	return omap_sham_cra_init_alg(tfm, "sha224");
1367}
1368
1369static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1370{
1371	return omap_sham_cra_init_alg(tfm, "sha256");
1372}
1373
1374static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1375{
1376	return omap_sham_cra_init_alg(tfm, "md5");
1377}
1378
1379static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1380{
1381	return omap_sham_cra_init_alg(tfm, "sha384");
1382}
1383
1384static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1385{
1386	return omap_sham_cra_init_alg(tfm, "sha512");
1387}
1388
1389static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1390{
1391	struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1392
1393	crypto_free_shash(tctx->fallback);
1394	tctx->fallback = NULL;
1395
1396	if (tctx->flags & BIT(FLAGS_HMAC)) {
1397		struct omap_sham_hmac_ctx *bctx = tctx->base;
1398		crypto_free_shash(bctx->shash);
1399	}
1400}
1401
1402static int omap_sham_export(struct ahash_request *req, void *out)
1403{
1404	struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1405
1406	memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1407
1408	return 0;
1409}
1410
1411static int omap_sham_import(struct ahash_request *req, const void *in)
1412{
1413	struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1414	const struct omap_sham_reqctx *ctx_in = in;
1415
1416	memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1417
1418	return 0;
1419}
1420
1421static struct ahash_engine_alg algs_sha1_md5[] = {
1422{
1423	.base.init		= omap_sham_init,
1424	.base.update		= omap_sham_update,
1425	.base.final		= omap_sham_final,
1426	.base.finup		= omap_sham_finup,
1427	.base.digest		= omap_sham_digest,
1428	.base.halg.digestsize	= SHA1_DIGEST_SIZE,
1429	.base.halg.base	= {
1430		.cra_name		= "sha1",
1431		.cra_driver_name	= "omap-sha1",
1432		.cra_priority		= 400,
1433		.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
1434						CRYPTO_ALG_ASYNC |
1435						CRYPTO_ALG_NEED_FALLBACK,
1436		.cra_blocksize		= SHA1_BLOCK_SIZE,
1437		.cra_ctxsize		= sizeof(struct omap_sham_ctx),
1438		.cra_module		= THIS_MODULE,
1439		.cra_init		= omap_sham_cra_init,
1440		.cra_exit		= omap_sham_cra_exit,
1441	},
1442	.op.do_one_request = omap_sham_hash_one_req,
1443},
1444{
1445	.base.init		= omap_sham_init,
1446	.base.update		= omap_sham_update,
1447	.base.final		= omap_sham_final,
1448	.base.finup		= omap_sham_finup,
1449	.base.digest		= omap_sham_digest,
1450	.base.halg.digestsize	= MD5_DIGEST_SIZE,
1451	.base.halg.base	= {
1452		.cra_name		= "md5",
1453		.cra_driver_name	= "omap-md5",
1454		.cra_priority		= 400,
1455		.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
1456						CRYPTO_ALG_ASYNC |
1457						CRYPTO_ALG_NEED_FALLBACK,
1458		.cra_blocksize		= SHA1_BLOCK_SIZE,
1459		.cra_ctxsize		= sizeof(struct omap_sham_ctx),
1460		.cra_module		= THIS_MODULE,
1461		.cra_init		= omap_sham_cra_init,
1462		.cra_exit		= omap_sham_cra_exit,
1463	},
1464	.op.do_one_request = omap_sham_hash_one_req,
1465},
1466{
1467	.base.init		= omap_sham_init,
1468	.base.update		= omap_sham_update,
1469	.base.final		= omap_sham_final,
1470	.base.finup		= omap_sham_finup,
1471	.base.digest		= omap_sham_digest,
1472	.base.setkey		= omap_sham_setkey,
1473	.base.halg.digestsize	= SHA1_DIGEST_SIZE,
1474	.base.halg.base	= {
1475		.cra_name		= "hmac(sha1)",
1476		.cra_driver_name	= "omap-hmac-sha1",
1477		.cra_priority		= 400,
1478		.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
1479						CRYPTO_ALG_ASYNC |
1480						CRYPTO_ALG_NEED_FALLBACK,
1481		.cra_blocksize		= SHA1_BLOCK_SIZE,
1482		.cra_ctxsize		= sizeof(struct omap_sham_ctx) +
1483					sizeof(struct omap_sham_hmac_ctx),
1484		.cra_module		= THIS_MODULE,
1485		.cra_init		= omap_sham_cra_sha1_init,
1486		.cra_exit		= omap_sham_cra_exit,
1487	},
1488	.op.do_one_request = omap_sham_hash_one_req,
1489},
1490{
1491	.base.init		= omap_sham_init,
1492	.base.update		= omap_sham_update,
1493	.base.final		= omap_sham_final,
1494	.base.finup		= omap_sham_finup,
1495	.base.digest		= omap_sham_digest,
1496	.base.setkey		= omap_sham_setkey,
1497	.base.halg.digestsize	= MD5_DIGEST_SIZE,
1498	.base.halg.base	= {
1499		.cra_name		= "hmac(md5)",
1500		.cra_driver_name	= "omap-hmac-md5",
1501		.cra_priority		= 400,
1502		.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
1503						CRYPTO_ALG_ASYNC |
1504						CRYPTO_ALG_NEED_FALLBACK,
1505		.cra_blocksize		= SHA1_BLOCK_SIZE,
1506		.cra_ctxsize		= sizeof(struct omap_sham_ctx) +
1507					sizeof(struct omap_sham_hmac_ctx),
1508		.cra_module		= THIS_MODULE,
1509		.cra_init		= omap_sham_cra_md5_init,
1510		.cra_exit		= omap_sham_cra_exit,
1511	},
1512	.op.do_one_request = omap_sham_hash_one_req,
1513}
1514};
1515
1516/* OMAP4 has some algs in addition to what OMAP2 has */
1517static struct ahash_engine_alg algs_sha224_sha256[] = {
1518{
1519	.base.init		= omap_sham_init,
1520	.base.update		= omap_sham_update,
1521	.base.final		= omap_sham_final,
1522	.base.finup		= omap_sham_finup,
1523	.base.digest		= omap_sham_digest,
1524	.base.halg.digestsize	= SHA224_DIGEST_SIZE,
1525	.base.halg.base	= {
1526		.cra_name		= "sha224",
1527		.cra_driver_name	= "omap-sha224",
1528		.cra_priority		= 400,
1529		.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
1530						CRYPTO_ALG_ASYNC |
1531						CRYPTO_ALG_NEED_FALLBACK,
1532		.cra_blocksize		= SHA224_BLOCK_SIZE,
1533		.cra_ctxsize		= sizeof(struct omap_sham_ctx),
1534		.cra_module		= THIS_MODULE,
1535		.cra_init		= omap_sham_cra_init,
1536		.cra_exit		= omap_sham_cra_exit,
1537	},
1538	.op.do_one_request = omap_sham_hash_one_req,
1539},
1540{
1541	.base.init		= omap_sham_init,
1542	.base.update		= omap_sham_update,
1543	.base.final		= omap_sham_final,
1544	.base.finup		= omap_sham_finup,
1545	.base.digest		= omap_sham_digest,
1546	.base.halg.digestsize	= SHA256_DIGEST_SIZE,
1547	.base.halg.base	= {
1548		.cra_name		= "sha256",
1549		.cra_driver_name	= "omap-sha256",
1550		.cra_priority		= 400,
1551		.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
1552						CRYPTO_ALG_ASYNC |
1553						CRYPTO_ALG_NEED_FALLBACK,
1554		.cra_blocksize		= SHA256_BLOCK_SIZE,
1555		.cra_ctxsize		= sizeof(struct omap_sham_ctx),
1556		.cra_module		= THIS_MODULE,
1557		.cra_init		= omap_sham_cra_init,
1558		.cra_exit		= omap_sham_cra_exit,
1559	},
1560	.op.do_one_request = omap_sham_hash_one_req,
1561},
1562{
1563	.base.init		= omap_sham_init,
1564	.base.update		= omap_sham_update,
1565	.base.final		= omap_sham_final,
1566	.base.finup		= omap_sham_finup,
1567	.base.digest		= omap_sham_digest,
1568	.base.setkey		= omap_sham_setkey,
1569	.base.halg.digestsize	= SHA224_DIGEST_SIZE,
1570	.base.halg.base	= {
1571		.cra_name		= "hmac(sha224)",
1572		.cra_driver_name	= "omap-hmac-sha224",
1573		.cra_priority		= 400,
1574		.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
1575						CRYPTO_ALG_ASYNC |
1576						CRYPTO_ALG_NEED_FALLBACK,
1577		.cra_blocksize		= SHA224_BLOCK_SIZE,
1578		.cra_ctxsize		= sizeof(struct omap_sham_ctx) +
1579					sizeof(struct omap_sham_hmac_ctx),
1580		.cra_module		= THIS_MODULE,
1581		.cra_init		= omap_sham_cra_sha224_init,
1582		.cra_exit		= omap_sham_cra_exit,
1583	},
1584	.op.do_one_request = omap_sham_hash_one_req,
1585},
1586{
1587	.base.init		= omap_sham_init,
1588	.base.update		= omap_sham_update,
1589	.base.final		= omap_sham_final,
1590	.base.finup		= omap_sham_finup,
1591	.base.digest		= omap_sham_digest,
1592	.base.setkey		= omap_sham_setkey,
1593	.base.halg.digestsize	= SHA256_DIGEST_SIZE,
1594	.base.halg.base	= {
1595		.cra_name		= "hmac(sha256)",
1596		.cra_driver_name	= "omap-hmac-sha256",
1597		.cra_priority		= 400,
1598		.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
1599						CRYPTO_ALG_ASYNC |
1600						CRYPTO_ALG_NEED_FALLBACK,
1601		.cra_blocksize		= SHA256_BLOCK_SIZE,
1602		.cra_ctxsize		= sizeof(struct omap_sham_ctx) +
1603					sizeof(struct omap_sham_hmac_ctx),
1604		.cra_module		= THIS_MODULE,
1605		.cra_init		= omap_sham_cra_sha256_init,
1606		.cra_exit		= omap_sham_cra_exit,
1607	},
1608	.op.do_one_request = omap_sham_hash_one_req,
1609},
1610};
1611
1612static struct ahash_engine_alg algs_sha384_sha512[] = {
1613{
1614	.base.init		= omap_sham_init,
1615	.base.update		= omap_sham_update,
1616	.base.final		= omap_sham_final,
1617	.base.finup		= omap_sham_finup,
1618	.base.digest		= omap_sham_digest,
1619	.base.halg.digestsize	= SHA384_DIGEST_SIZE,
1620	.base.halg.base	= {
1621		.cra_name		= "sha384",
1622		.cra_driver_name	= "omap-sha384",
1623		.cra_priority		= 400,
1624		.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
1625						CRYPTO_ALG_ASYNC |
1626						CRYPTO_ALG_NEED_FALLBACK,
1627		.cra_blocksize		= SHA384_BLOCK_SIZE,
1628		.cra_ctxsize		= sizeof(struct omap_sham_ctx),
1629		.cra_module		= THIS_MODULE,
1630		.cra_init		= omap_sham_cra_init,
1631		.cra_exit		= omap_sham_cra_exit,
1632	},
1633	.op.do_one_request = omap_sham_hash_one_req,
1634},
1635{
1636	.base.init		= omap_sham_init,
1637	.base.update		= omap_sham_update,
1638	.base.final		= omap_sham_final,
1639	.base.finup		= omap_sham_finup,
1640	.base.digest		= omap_sham_digest,
1641	.base.halg.digestsize	= SHA512_DIGEST_SIZE,
1642	.base.halg.base	= {
1643		.cra_name		= "sha512",
1644		.cra_driver_name	= "omap-sha512",
1645		.cra_priority		= 400,
1646		.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
1647						CRYPTO_ALG_ASYNC |
1648						CRYPTO_ALG_NEED_FALLBACK,
1649		.cra_blocksize		= SHA512_BLOCK_SIZE,
1650		.cra_ctxsize		= sizeof(struct omap_sham_ctx),
1651		.cra_module		= THIS_MODULE,
1652		.cra_init		= omap_sham_cra_init,
1653		.cra_exit		= omap_sham_cra_exit,
1654	},
1655	.op.do_one_request = omap_sham_hash_one_req,
1656},
1657{
1658	.base.init		= omap_sham_init,
1659	.base.update		= omap_sham_update,
1660	.base.final		= omap_sham_final,
1661	.base.finup		= omap_sham_finup,
1662	.base.digest		= omap_sham_digest,
1663	.base.setkey		= omap_sham_setkey,
1664	.base.halg.digestsize	= SHA384_DIGEST_SIZE,
1665	.base.halg.base	= {
1666		.cra_name		= "hmac(sha384)",
1667		.cra_driver_name	= "omap-hmac-sha384",
1668		.cra_priority		= 400,
1669		.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
1670						CRYPTO_ALG_ASYNC |
1671						CRYPTO_ALG_NEED_FALLBACK,
1672		.cra_blocksize		= SHA384_BLOCK_SIZE,
1673		.cra_ctxsize		= sizeof(struct omap_sham_ctx) +
1674					sizeof(struct omap_sham_hmac_ctx),
1675		.cra_module		= THIS_MODULE,
1676		.cra_init		= omap_sham_cra_sha384_init,
1677		.cra_exit		= omap_sham_cra_exit,
1678	},
1679	.op.do_one_request = omap_sham_hash_one_req,
1680},
1681{
1682	.base.init		= omap_sham_init,
1683	.base.update		= omap_sham_update,
1684	.base.final		= omap_sham_final,
1685	.base.finup		= omap_sham_finup,
1686	.base.digest		= omap_sham_digest,
1687	.base.setkey		= omap_sham_setkey,
1688	.base.halg.digestsize	= SHA512_DIGEST_SIZE,
1689	.base.halg.base	= {
1690		.cra_name		= "hmac(sha512)",
1691		.cra_driver_name	= "omap-hmac-sha512",
1692		.cra_priority		= 400,
1693		.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
1694						CRYPTO_ALG_ASYNC |
1695						CRYPTO_ALG_NEED_FALLBACK,
1696		.cra_blocksize		= SHA512_BLOCK_SIZE,
1697		.cra_ctxsize		= sizeof(struct omap_sham_ctx) +
1698					sizeof(struct omap_sham_hmac_ctx),
1699		.cra_module		= THIS_MODULE,
1700		.cra_init		= omap_sham_cra_sha512_init,
1701		.cra_exit		= omap_sham_cra_exit,
1702	},
1703	.op.do_one_request = omap_sham_hash_one_req,
1704},
1705};
1706
1707static void omap_sham_done_task(struct work_struct *t)
1708{
1709	struct omap_sham_dev *dd = from_work(dd, t, done_task);
1710	int err = 0;
1711
1712	dev_dbg(dd->dev, "%s: flags=%lx\n", __func__, dd->flags);
1713
1714	if (test_bit(FLAGS_CPU, &dd->flags)) {
1715		if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1716			goto finish;
1717	} else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1718		if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1719			omap_sham_update_dma_stop(dd);
1720			if (dd->err) {
1721				err = dd->err;
1722				goto finish;
1723			}
1724		}
1725		if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1726			/* hash or semi-hash ready */
1727			clear_bit(FLAGS_DMA_READY, &dd->flags);
1728			goto finish;
1729		}
1730	}
1731
1732	return;
1733
1734finish:
1735	dev_dbg(dd->dev, "update done: err: %d\n", err);
1736	/* finish curent request */
1737	omap_sham_finish_req(dd->req, err);
1738}
1739
1740static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1741{
1742	set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1743	queue_work(system_bh_wq, &dd->done_task);
1744
1745	return IRQ_HANDLED;
1746}
1747
1748static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1749{
1750	struct omap_sham_dev *dd = dev_id;
1751
1752	if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1753		/* final -> allow device to go to power-saving mode */
1754		omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1755
1756	omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1757				 SHA_REG_CTRL_OUTPUT_READY);
1758	omap_sham_read(dd, SHA_REG_CTRL);
1759
1760	return omap_sham_irq_common(dd);
1761}
1762
1763static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1764{
1765	struct omap_sham_dev *dd = dev_id;
1766
1767	omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1768
1769	return omap_sham_irq_common(dd);
1770}
1771
1772static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1773	{
1774		.algs_list	= algs_sha1_md5,
1775		.size		= ARRAY_SIZE(algs_sha1_md5),
1776	},
1777};
1778
1779static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1780	.algs_info	= omap_sham_algs_info_omap2,
1781	.algs_info_size	= ARRAY_SIZE(omap_sham_algs_info_omap2),
1782	.flags		= BIT(FLAGS_BE32_SHA1),
1783	.digest_size	= SHA1_DIGEST_SIZE,
1784	.copy_hash	= omap_sham_copy_hash_omap2,
1785	.write_ctrl	= omap_sham_write_ctrl_omap2,
1786	.trigger	= omap_sham_trigger_omap2,
1787	.poll_irq	= omap_sham_poll_irq_omap2,
1788	.intr_hdlr	= omap_sham_irq_omap2,
1789	.idigest_ofs	= 0x00,
1790	.din_ofs	= 0x1c,
1791	.digcnt_ofs	= 0x14,
1792	.rev_ofs	= 0x5c,
1793	.mask_ofs	= 0x60,
1794	.sysstatus_ofs	= 0x64,
1795	.major_mask	= 0xf0,
1796	.major_shift	= 4,
1797	.minor_mask	= 0x0f,
1798	.minor_shift	= 0,
1799};
1800
1801#ifdef CONFIG_OF
1802static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1803	{
1804		.algs_list	= algs_sha1_md5,
1805		.size		= ARRAY_SIZE(algs_sha1_md5),
1806	},
1807	{
1808		.algs_list	= algs_sha224_sha256,
1809		.size		= ARRAY_SIZE(algs_sha224_sha256),
1810	},
1811};
1812
1813static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1814	.algs_info	= omap_sham_algs_info_omap4,
1815	.algs_info_size	= ARRAY_SIZE(omap_sham_algs_info_omap4),
1816	.flags		= BIT(FLAGS_AUTO_XOR),
1817	.digest_size	= SHA256_DIGEST_SIZE,
1818	.copy_hash	= omap_sham_copy_hash_omap4,
1819	.write_ctrl	= omap_sham_write_ctrl_omap4,
1820	.trigger	= omap_sham_trigger_omap4,
1821	.poll_irq	= omap_sham_poll_irq_omap4,
1822	.intr_hdlr	= omap_sham_irq_omap4,
1823	.idigest_ofs	= 0x020,
1824	.odigest_ofs	= 0x0,
1825	.din_ofs	= 0x080,
1826	.digcnt_ofs	= 0x040,
1827	.rev_ofs	= 0x100,
1828	.mask_ofs	= 0x110,
1829	.sysstatus_ofs	= 0x114,
1830	.mode_ofs	= 0x44,
1831	.length_ofs	= 0x48,
1832	.major_mask	= 0x0700,
1833	.major_shift	= 8,
1834	.minor_mask	= 0x003f,
1835	.minor_shift	= 0,
1836};
1837
1838static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1839	{
1840		.algs_list	= algs_sha1_md5,
1841		.size		= ARRAY_SIZE(algs_sha1_md5),
1842	},
1843	{
1844		.algs_list	= algs_sha224_sha256,
1845		.size		= ARRAY_SIZE(algs_sha224_sha256),
1846	},
1847	{
1848		.algs_list	= algs_sha384_sha512,
1849		.size		= ARRAY_SIZE(algs_sha384_sha512),
1850	},
1851};
1852
1853static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1854	.algs_info	= omap_sham_algs_info_omap5,
1855	.algs_info_size	= ARRAY_SIZE(omap_sham_algs_info_omap5),
1856	.flags		= BIT(FLAGS_AUTO_XOR),
1857	.digest_size	= SHA512_DIGEST_SIZE,
1858	.copy_hash	= omap_sham_copy_hash_omap4,
1859	.write_ctrl	= omap_sham_write_ctrl_omap4,
1860	.trigger	= omap_sham_trigger_omap4,
1861	.poll_irq	= omap_sham_poll_irq_omap4,
1862	.intr_hdlr	= omap_sham_irq_omap4,
1863	.idigest_ofs	= 0x240,
1864	.odigest_ofs	= 0x200,
1865	.din_ofs	= 0x080,
1866	.digcnt_ofs	= 0x280,
1867	.rev_ofs	= 0x100,
1868	.mask_ofs	= 0x110,
1869	.sysstatus_ofs	= 0x114,
1870	.mode_ofs	= 0x284,
1871	.length_ofs	= 0x288,
1872	.major_mask	= 0x0700,
1873	.major_shift	= 8,
1874	.minor_mask	= 0x003f,
1875	.minor_shift	= 0,
1876};
1877
1878static const struct of_device_id omap_sham_of_match[] = {
1879	{
1880		.compatible	= "ti,omap2-sham",
1881		.data		= &omap_sham_pdata_omap2,
1882	},
1883	{
1884		.compatible	= "ti,omap3-sham",
1885		.data		= &omap_sham_pdata_omap2,
1886	},
1887	{
1888		.compatible	= "ti,omap4-sham",
1889		.data		= &omap_sham_pdata_omap4,
1890	},
1891	{
1892		.compatible	= "ti,omap5-sham",
1893		.data		= &omap_sham_pdata_omap5,
1894	},
1895	{},
1896};
1897MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1898
1899static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1900		struct device *dev, struct resource *res)
1901{
1902	struct device_node *node = dev->of_node;
1903	int err = 0;
1904
1905	dd->pdata = of_device_get_match_data(dev);
1906	if (!dd->pdata) {
1907		dev_err(dev, "no compatible OF match\n");
1908		err = -EINVAL;
1909		goto err;
1910	}
1911
1912	err = of_address_to_resource(node, 0, res);
1913	if (err < 0) {
1914		dev_err(dev, "can't translate OF node address\n");
1915		err = -EINVAL;
1916		goto err;
1917	}
1918
1919	dd->irq = irq_of_parse_and_map(node, 0);
1920	if (!dd->irq) {
1921		dev_err(dev, "can't translate OF irq value\n");
1922		err = -EINVAL;
1923		goto err;
1924	}
1925
1926err:
1927	return err;
1928}
1929#else
1930static const struct of_device_id omap_sham_of_match[] = {
1931	{},
1932};
1933
1934static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1935		struct device *dev, struct resource *res)
1936{
1937	return -EINVAL;
1938}
1939#endif
1940
1941static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1942		struct platform_device *pdev, struct resource *res)
1943{
1944	struct device *dev = &pdev->dev;
1945	struct resource *r;
1946	int err = 0;
1947
1948	/* Get the base address */
1949	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1950	if (!r) {
1951		dev_err(dev, "no MEM resource info\n");
1952		err = -ENODEV;
1953		goto err;
1954	}
1955	memcpy(res, r, sizeof(*res));
1956
1957	/* Get the IRQ */
1958	dd->irq = platform_get_irq(pdev, 0);
1959	if (dd->irq < 0) {
1960		err = dd->irq;
1961		goto err;
1962	}
1963
1964	/* Only OMAP2/3 can be non-DT */
1965	dd->pdata = &omap_sham_pdata_omap2;
1966
1967err:
1968	return err;
1969}
1970
1971static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
1972			     char *buf)
1973{
1974	struct omap_sham_dev *dd = dev_get_drvdata(dev);
1975
1976	return sprintf(buf, "%d\n", dd->fallback_sz);
1977}
1978
1979static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
1980			      const char *buf, size_t size)
1981{
1982	struct omap_sham_dev *dd = dev_get_drvdata(dev);
1983	ssize_t status;
1984	long value;
1985
1986	status = kstrtol(buf, 0, &value);
1987	if (status)
1988		return status;
1989
1990	/* HW accelerator only works with buffers > 9 */
1991	if (value < 9) {
1992		dev_err(dev, "minimum fallback size 9\n");
1993		return -EINVAL;
1994	}
1995
1996	dd->fallback_sz = value;
1997
1998	return size;
1999}
2000
2001static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
2002			      char *buf)
2003{
2004	struct omap_sham_dev *dd = dev_get_drvdata(dev);
2005
2006	return sprintf(buf, "%d\n", dd->queue.max_qlen);
2007}
2008
2009static ssize_t queue_len_store(struct device *dev,
2010			       struct device_attribute *attr, const char *buf,
2011			       size_t size)
2012{
2013	struct omap_sham_dev *dd = dev_get_drvdata(dev);
2014	ssize_t status;
2015	long value;
2016
2017	status = kstrtol(buf, 0, &value);
2018	if (status)
2019		return status;
2020
2021	if (value < 1)
2022		return -EINVAL;
2023
2024	/*
2025	 * Changing the queue size in fly is safe, if size becomes smaller
2026	 * than current size, it will just not accept new entries until
2027	 * it has shrank enough.
2028	 */
2029	dd->queue.max_qlen = value;
2030
2031	return size;
2032}
2033
2034static DEVICE_ATTR_RW(queue_len);
2035static DEVICE_ATTR_RW(fallback);
2036
2037static struct attribute *omap_sham_attrs[] = {
2038	&dev_attr_queue_len.attr,
2039	&dev_attr_fallback.attr,
2040	NULL,
2041};
2042ATTRIBUTE_GROUPS(omap_sham);
2043
2044static int omap_sham_probe(struct platform_device *pdev)
2045{
2046	struct omap_sham_dev *dd;
2047	struct device *dev = &pdev->dev;
2048	struct resource res;
2049	dma_cap_mask_t mask;
2050	int err, i, j;
2051	u32 rev;
2052
2053	dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2054	if (dd == NULL) {
2055		dev_err(dev, "unable to alloc data struct.\n");
2056		err = -ENOMEM;
2057		goto data_err;
2058	}
2059	dd->dev = dev;
2060	platform_set_drvdata(pdev, dd);
2061
2062	INIT_LIST_HEAD(&dd->list);
2063	INIT_WORK(&dd->done_task, omap_sham_done_task);
2064	crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2065
2066	err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2067			       omap_sham_get_res_pdev(dd, pdev, &res);
2068	if (err)
2069		goto data_err;
2070
2071	dd->io_base = devm_ioremap_resource(dev, &res);
2072	if (IS_ERR(dd->io_base)) {
2073		err = PTR_ERR(dd->io_base);
2074		goto data_err;
2075	}
2076	dd->phys_base = res.start;
2077
2078	err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2079			       IRQF_TRIGGER_NONE, dev_name(dev), dd);
2080	if (err) {
2081		dev_err(dev, "unable to request irq %d, err = %d\n",
2082			dd->irq, err);
2083		goto data_err;
2084	}
2085
2086	dma_cap_zero(mask);
2087	dma_cap_set(DMA_SLAVE, mask);
2088
2089	dd->dma_lch = dma_request_chan(dev, "rx");
2090	if (IS_ERR(dd->dma_lch)) {
2091		err = PTR_ERR(dd->dma_lch);
2092		if (err == -EPROBE_DEFER)
2093			goto data_err;
2094
2095		dd->polling_mode = 1;
2096		dev_dbg(dev, "using polling mode instead of dma\n");
2097	}
2098
2099	dd->flags |= dd->pdata->flags;
2100	sham.flags |= dd->pdata->flags;
2101
2102	pm_runtime_use_autosuspend(dev);
2103	pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2104
2105	dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD;
2106
2107	pm_runtime_enable(dev);
2108
2109	err = pm_runtime_resume_and_get(dev);
2110	if (err < 0) {
2111		dev_err(dev, "failed to get sync: %d\n", err);
2112		goto err_pm;
2113	}
2114
2115	rev = omap_sham_read(dd, SHA_REG_REV(dd));
2116	pm_runtime_put_sync(&pdev->dev);
2117
2118	dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2119		(rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2120		(rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2121
2122	spin_lock_bh(&sham.lock);
2123	list_add_tail(&dd->list, &sham.dev_list);
2124	spin_unlock_bh(&sham.lock);
2125
2126	dd->engine = crypto_engine_alloc_init(dev, 1);
2127	if (!dd->engine) {
2128		err = -ENOMEM;
2129		goto err_engine;
2130	}
2131
2132	err = crypto_engine_start(dd->engine);
2133	if (err)
2134		goto err_engine_start;
2135
2136	for (i = 0; i < dd->pdata->algs_info_size; i++) {
2137		if (dd->pdata->algs_info[i].registered)
2138			break;
2139
2140		for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2141			struct ahash_engine_alg *ealg;
2142			struct ahash_alg *alg;
2143
2144			ealg = &dd->pdata->algs_info[i].algs_list[j];
2145			alg = &ealg->base;
2146			alg->export = omap_sham_export;
2147			alg->import = omap_sham_import;
2148			alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2149					      BUFLEN;
2150			err = crypto_engine_register_ahash(ealg);
2151			if (err)
2152				goto err_algs;
2153
2154			dd->pdata->algs_info[i].registered++;
2155		}
2156	}
2157
2158	return 0;
2159
2160err_algs:
2161	for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2162		for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2163			crypto_engine_unregister_ahash(
2164					&dd->pdata->algs_info[i].algs_list[j]);
2165err_engine_start:
2166	crypto_engine_exit(dd->engine);
2167err_engine:
2168	spin_lock_bh(&sham.lock);
2169	list_del(&dd->list);
2170	spin_unlock_bh(&sham.lock);
2171err_pm:
2172	pm_runtime_dont_use_autosuspend(dev);
2173	pm_runtime_disable(dev);
2174	if (!dd->polling_mode)
2175		dma_release_channel(dd->dma_lch);
2176data_err:
2177	dev_err(dev, "initialization failed.\n");
2178
2179	return err;
2180}
2181
2182static void omap_sham_remove(struct platform_device *pdev)
2183{
2184	struct omap_sham_dev *dd;
2185	int i, j;
2186
2187	dd = platform_get_drvdata(pdev);
2188
2189	spin_lock_bh(&sham.lock);
2190	list_del(&dd->list);
2191	spin_unlock_bh(&sham.lock);
2192	for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2193		for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
2194			crypto_engine_unregister_ahash(
2195					&dd->pdata->algs_info[i].algs_list[j]);
2196			dd->pdata->algs_info[i].registered--;
2197		}
2198	cancel_work_sync(&dd->done_task);
2199	pm_runtime_dont_use_autosuspend(&pdev->dev);
2200	pm_runtime_disable(&pdev->dev);
2201
2202	if (!dd->polling_mode)
2203		dma_release_channel(dd->dma_lch);
2204}
2205
2206static struct platform_driver omap_sham_driver = {
2207	.probe	= omap_sham_probe,
2208	.remove = omap_sham_remove,
2209	.driver	= {
2210		.name	= "omap-sham",
2211		.of_match_table	= omap_sham_of_match,
2212		.dev_groups = omap_sham_groups,
2213	},
2214};
2215
2216module_platform_driver(omap_sham_driver);
2217
2218MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2219MODULE_LICENSE("GPL v2");
2220MODULE_AUTHOR("Dmitry Kasatkin");
2221MODULE_ALIAS("platform:omap-sham");