omap-des.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Support for OMAP DES and Triple DES HW acceleration.
   4 *
   5 * Copyright (c) 2013 Texas Instruments Incorporated
   6 * Author: Joel Fernandes <joelf@ti.com>
   7 */
   8
   9#define pr_fmt(fmt) "%s: " fmt, __func__
  10
  11#ifdef DEBUG
  12#define prn(num) printk(#num "=%d\n", num)
  13#define prx(num) printk(#num "=%x\n", num)
  14#else
  15#define prn(num) do { } while (0)
  16#define prx(num)  do { } while (0)
  17#endif
  18
  19#include <crypto/engine.h>
  20#include <crypto/internal/des.h>
  21#include <crypto/internal/skcipher.h>
  22#include <linux/dma-mapping.h>
  23#include <linux/dmaengine.h>
  24#include <linux/err.h>
  25#include <linux/init.h>
  26#include <linux/interrupt.h>
  27#include <linux/io.h>
  28#include <linux/kernel.h>
  29#include <linux/module.h>
  30#include <linux/of.h>
  31#include <linux/platform_device.h>
  32#include <linux/pm_runtime.h>
  33#include <linux/scatterlist.h>
  34#include <linux/string.h>
  35#include <linux/workqueue.h>
  36
  37#include "omap-crypto.h"
  38
  39#define DST_MAXBURST			2
  40
  41#define DES_BLOCK_WORDS		(DES_BLOCK_SIZE >> 2)
  42
  43#define DES_REG_KEY(dd, x)		((dd)->pdata->key_ofs - \
  44						((x ^ 0x01) * 0x04))
  45
  46#define DES_REG_IV(dd, x)		((dd)->pdata->iv_ofs + ((x) * 0x04))
  47
  48#define DES_REG_CTRL(dd)		((dd)->pdata->ctrl_ofs)
  49#define DES_REG_CTRL_CBC		BIT(4)
  50#define DES_REG_CTRL_TDES		BIT(3)
  51#define DES_REG_CTRL_DIRECTION		BIT(2)
  52#define DES_REG_CTRL_INPUT_READY	BIT(1)
  53#define DES_REG_CTRL_OUTPUT_READY	BIT(0)
  54
  55#define DES_REG_DATA_N(dd, x)		((dd)->pdata->data_ofs + ((x) * 0x04))
  56
  57#define DES_REG_REV(dd)			((dd)->pdata->rev_ofs)
  58
  59#define DES_REG_MASK(dd)		((dd)->pdata->mask_ofs)
  60
  61#define DES_REG_LENGTH_N(x)		(0x24 + ((x) * 0x04))
  62
  63#define DES_REG_IRQ_STATUS(dd)         ((dd)->pdata->irq_status_ofs)
  64#define DES_REG_IRQ_ENABLE(dd)         ((dd)->pdata->irq_enable_ofs)
  65#define DES_REG_IRQ_DATA_IN            BIT(1)
  66#define DES_REG_IRQ_DATA_OUT           BIT(2)
  67
  68#define FLAGS_MODE_MASK		0x000f
  69#define FLAGS_ENCRYPT		BIT(0)
  70#define FLAGS_CBC		BIT(1)
  71#define FLAGS_INIT		BIT(4)
  72#define FLAGS_BUSY		BIT(6)
  73
  74#define DEFAULT_AUTOSUSPEND_DELAY	1000
  75
  76#define FLAGS_IN_DATA_ST_SHIFT	8
  77#define FLAGS_OUT_DATA_ST_SHIFT	10
  78
  79struct omap_des_ctx {
  80	struct omap_des_dev *dd;
  81
  82	int		keylen;
  83	__le32		key[(3 * DES_KEY_SIZE) / sizeof(u32)];
  84	unsigned long	flags;
  85};
  86
  87struct omap_des_reqctx {
  88	unsigned long mode;
  89};
  90
  91#define OMAP_DES_QUEUE_LENGTH	1
  92#define OMAP_DES_CACHE_SIZE	0
  93
  94struct omap_des_algs_info {
  95	struct skcipher_engine_alg	*algs_list;
  96	unsigned int			size;
  97	unsigned int			registered;
  98};
  99
 100struct omap_des_pdata {
 101	struct omap_des_algs_info	*algs_info;
 102	unsigned int	algs_info_size;
 103
 104	void		(*trigger)(struct omap_des_dev *dd, int length);
 105
 106	u32		key_ofs;
 107	u32		iv_ofs;
 108	u32		ctrl_ofs;
 109	u32		data_ofs;
 110	u32		rev_ofs;
 111	u32		mask_ofs;
 112	u32             irq_enable_ofs;
 113	u32             irq_status_ofs;
 114
 115	u32		dma_enable_in;
 116	u32		dma_enable_out;
 117	u32		dma_start;
 118
 119	u32		major_mask;
 120	u32		major_shift;
 121	u32		minor_mask;
 122	u32		minor_shift;
 123};
 124
 125struct omap_des_dev {
 126	struct list_head	list;
 127	unsigned long		phys_base;
 128	void __iomem		*io_base;
 129	struct omap_des_ctx	*ctx;
 130	struct device		*dev;
 131	unsigned long		flags;
 132	int			err;
 133
 134	struct work_struct	done_task;
 135
 136	struct skcipher_request	*req;
 137	struct crypto_engine		*engine;
 138	/*
 139	 * total is used by PIO mode for book keeping so introduce
 140	 * variable total_save as need it to calc page_order
 141	 */
 142	size_t                          total;
 143	size_t                          total_save;
 144
 145	struct scatterlist		*in_sg;
 146	struct scatterlist		*out_sg;
 147
 148	/* Buffers for copying for unaligned cases */
 149	struct scatterlist		in_sgl;
 150	struct scatterlist		out_sgl;
 151	struct scatterlist		*orig_out;
 152
 153	unsigned int		in_sg_offset;
 154	unsigned int		out_sg_offset;
 155	struct dma_chan		*dma_lch_in;
 156	struct dma_chan		*dma_lch_out;
 157	int			in_sg_len;
 158	int			out_sg_len;
 159	int			pio_only;
 160	const struct omap_des_pdata	*pdata;
 161};
 162
 163/* keep registered devices data here */
 164static LIST_HEAD(dev_list);
 165static DEFINE_SPINLOCK(list_lock);
 166
 167#ifdef DEBUG
 168#define omap_des_read(dd, offset)                               \
 169	({                                                              \
 170	 int _read_ret;                                          \
 171	 _read_ret = __raw_readl(dd->io_base + offset);          \
 172	 pr_err("omap_des_read(" #offset "=%#x)= %#x\n",       \
 173		 offset, _read_ret);                            \
 174	 _read_ret;                                              \
 175	 })
 176#else
 177static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
 178{
 179	return __raw_readl(dd->io_base + offset);
 180}
 181#endif
 182
 183#ifdef DEBUG
 184#define omap_des_write(dd, offset, value)                               \
 185	do {                                                            \
 186		pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
 187				offset, value);                                \
 188		__raw_writel(value, dd->io_base + offset);              \
 189	} while (0)
 190#else
 191static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
 192		u32 value)
 193{
 194	__raw_writel(value, dd->io_base + offset);
 195}
 196#endif
 197
 198static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
 199					u32 value, u32 mask)
 200{
 201	u32 val;
 202
 203	val = omap_des_read(dd, offset);
 204	val &= ~mask;
 205	val |= value;
 206	omap_des_write(dd, offset, val);
 207}
 208
 209static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
 210					u32 *value, int count)
 211{
 212	for (; count--; value++, offset += 4)
 213		omap_des_write(dd, offset, *value);
 214}
 215
 216static int omap_des_hw_init(struct omap_des_dev *dd)
 217{
 218	int err;
 219
 220	/*
 221	 * clocks are enabled when request starts and disabled when finished.
 222	 * It may be long delays between requests.
 223	 * Device might go to off mode to save power.
 224	 */
 225	err = pm_runtime_resume_and_get(dd->dev);
 226	if (err < 0) {
 227		dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
 228		return err;
 229	}
 230
 231	if (!(dd->flags & FLAGS_INIT)) {
 232		dd->flags |= FLAGS_INIT;
 233		dd->err = 0;
 234	}
 235
 236	return 0;
 237}
 238
 239static int omap_des_write_ctrl(struct omap_des_dev *dd)
 240{
 241	unsigned int key32;
 242	int i, err;
 243	u32 val = 0, mask = 0;
 244
 245	err = omap_des_hw_init(dd);
 246	if (err)
 247		return err;
 248
 249	key32 = dd->ctx->keylen / sizeof(u32);
 250
 251	/* it seems a key should always be set even if it has not changed */
 252	for (i = 0; i < key32; i++) {
 253		omap_des_write(dd, DES_REG_KEY(dd, i),
 254			       __le32_to_cpu(dd->ctx->key[i]));
 255	}
 256
 257	if ((dd->flags & FLAGS_CBC) && dd->req->iv)
 258		omap_des_write_n(dd, DES_REG_IV(dd, 0), (void *)dd->req->iv, 2);
 259
 260	if (dd->flags & FLAGS_CBC)
 261		val |= DES_REG_CTRL_CBC;
 262	if (dd->flags & FLAGS_ENCRYPT)
 263		val |= DES_REG_CTRL_DIRECTION;
 264	if (key32 == 6)
 265		val |= DES_REG_CTRL_TDES;
 266
 267	mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
 268
 269	omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
 270
 271	return 0;
 272}
 273
 274static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
 275{
 276	u32 mask, val;
 277
 278	omap_des_write(dd, DES_REG_LENGTH_N(0), length);
 279
 280	val = dd->pdata->dma_start;
 281
 282	if (dd->dma_lch_out != NULL)
 283		val |= dd->pdata->dma_enable_out;
 284	if (dd->dma_lch_in != NULL)
 285		val |= dd->pdata->dma_enable_in;
 286
 287	mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 288	       dd->pdata->dma_start;
 289
 290	omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
 291}
 292
 293static void omap_des_dma_stop(struct omap_des_dev *dd)
 294{
 295	u32 mask;
 296
 297	mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 298	       dd->pdata->dma_start;
 299
 300	omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
 301}
 302
 303static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
 304{
 305	struct omap_des_dev *dd = NULL, *tmp;
 306
 307	spin_lock_bh(&list_lock);
 308	if (!ctx->dd) {
 309		list_for_each_entry(tmp, &dev_list, list) {
 310			/* FIXME: take fist available des core */
 311			dd = tmp;
 312			break;
 313		}
 314		ctx->dd = dd;
 315	} else {
 316		/* already found before */
 317		dd = ctx->dd;
 318	}
 319	spin_unlock_bh(&list_lock);
 320
 321	return dd;
 322}
 323
 324static void omap_des_dma_out_callback(void *data)
 325{
 326	struct omap_des_dev *dd = data;
 327
 328	/* dma_lch_out - completed */
 329	queue_work(system_bh_wq, &dd->done_task);
 330}
 331
 332static int omap_des_dma_init(struct omap_des_dev *dd)
 333{
 334	int err;
 335
 336	dd->dma_lch_out = NULL;
 337	dd->dma_lch_in = NULL;
 338
 339	dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
 340	if (IS_ERR(dd->dma_lch_in)) {
 341		dev_err(dd->dev, "Unable to request in DMA channel\n");
 342		return PTR_ERR(dd->dma_lch_in);
 343	}
 344
 345	dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
 346	if (IS_ERR(dd->dma_lch_out)) {
 347		dev_err(dd->dev, "Unable to request out DMA channel\n");
 348		err = PTR_ERR(dd->dma_lch_out);
 349		goto err_dma_out;
 350	}
 351
 352	return 0;
 353
 354err_dma_out:
 355	dma_release_channel(dd->dma_lch_in);
 356
 357	return err;
 358}
 359
 360static void omap_des_dma_cleanup(struct omap_des_dev *dd)
 361{
 362	if (dd->pio_only)
 363		return;
 364
 365	dma_release_channel(dd->dma_lch_out);
 366	dma_release_channel(dd->dma_lch_in);
 367}
 368
 369static int omap_des_crypt_dma(struct crypto_tfm *tfm,
 370		struct scatterlist *in_sg, struct scatterlist *out_sg,
 371		int in_sg_len, int out_sg_len)
 372{
 373	struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
 374	struct omap_des_dev *dd = ctx->dd;
 375	struct dma_async_tx_descriptor *tx_in, *tx_out;
 376	struct dma_slave_config cfg;
 377	int ret;
 378
 379	if (dd->pio_only) {
 380		dd->in_sg_offset = 0;
 381		dd->out_sg_offset = 0;
 382
 383		/* Enable DATAIN interrupt and let it take
 384		   care of the rest */
 385		omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
 386		return 0;
 387	}
 388
 389	dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
 390
 391	memset(&cfg, 0, sizeof(cfg));
 392
 393	cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
 394	cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
 395	cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 396	cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 397	cfg.src_maxburst = DST_MAXBURST;
 398	cfg.dst_maxburst = DST_MAXBURST;
 399
 400	/* IN */
 401	ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
 402	if (ret) {
 403		dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
 404			ret);
 405		return ret;
 406	}
 407
 408	tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
 409					DMA_MEM_TO_DEV,
 410					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 411	if (!tx_in) {
 412		dev_err(dd->dev, "IN prep_slave_sg() failed\n");
 413		return -EINVAL;
 414	}
 415
 416	/* No callback necessary */
 417	tx_in->callback_param = dd;
 418
 419	/* OUT */
 420	ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
 421	if (ret) {
 422		dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
 423			ret);
 424		return ret;
 425	}
 426
 427	tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
 428					DMA_DEV_TO_MEM,
 429					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 430	if (!tx_out) {
 431		dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
 432		return -EINVAL;
 433	}
 434
 435	tx_out->callback = omap_des_dma_out_callback;
 436	tx_out->callback_param = dd;
 437
 438	dmaengine_submit(tx_in);
 439	dmaengine_submit(tx_out);
 440
 441	dma_async_issue_pending(dd->dma_lch_in);
 442	dma_async_issue_pending(dd->dma_lch_out);
 443
 444	/* start DMA */
 445	dd->pdata->trigger(dd, dd->total);
 446
 447	return 0;
 448}
 449
 450static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
 451{
 452	struct crypto_tfm *tfm = crypto_skcipher_tfm(
 453					crypto_skcipher_reqtfm(dd->req));
 454	int err;
 455
 456	pr_debug("total: %zd\n", dd->total);
 457
 458	if (!dd->pio_only) {
 459		err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
 460				 DMA_TO_DEVICE);
 461		if (!err) {
 462			dev_err(dd->dev, "dma_map_sg() error\n");
 463			return -EINVAL;
 464		}
 465
 466		err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 467				 DMA_FROM_DEVICE);
 468		if (!err) {
 469			dev_err(dd->dev, "dma_map_sg() error\n");
 470			return -EINVAL;
 471		}
 472	}
 473
 474	err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
 475				 dd->out_sg_len);
 476	if (err && !dd->pio_only) {
 477		dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 478		dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 479			     DMA_FROM_DEVICE);
 480	}
 481
 482	return err;
 483}
 484
 485static void omap_des_finish_req(struct omap_des_dev *dd, int err)
 486{
 487	struct skcipher_request *req = dd->req;
 488
 489	pr_debug("err: %d\n", err);
 490
 491	crypto_finalize_skcipher_request(dd->engine, req, err);
 492
 493	pm_runtime_put_autosuspend(dd->dev);
 494}
 495
 496static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
 497{
 498	pr_debug("total: %zd\n", dd->total);
 499
 500	omap_des_dma_stop(dd);
 501
 502	dmaengine_terminate_all(dd->dma_lch_in);
 503	dmaengine_terminate_all(dd->dma_lch_out);
 504
 505	return 0;
 506}
 507
 508static int omap_des_handle_queue(struct omap_des_dev *dd,
 509				 struct skcipher_request *req)
 510{
 511	if (req)
 512		return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
 513
 514	return 0;
 515}
 516
 517static int omap_des_prepare_req(struct skcipher_request *req,
 518				struct omap_des_dev *dd)
 519{
 520	struct omap_des_ctx *ctx = crypto_skcipher_ctx(
 521			crypto_skcipher_reqtfm(req));
 522	struct omap_des_reqctx *rctx;
 523	int ret;
 524	u16 flags;
 525
 526	/* assign new request to device */
 527	dd->req = req;
 528	dd->total = req->cryptlen;
 529	dd->total_save = req->cryptlen;
 530	dd->in_sg = req->src;
 531	dd->out_sg = req->dst;
 532	dd->orig_out = req->dst;
 533
 534	flags = OMAP_CRYPTO_COPY_DATA;
 535	if (req->src == req->dst)
 536		flags |= OMAP_CRYPTO_FORCE_COPY;
 537
 538	ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE,
 539				   &dd->in_sgl, flags,
 540				   FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
 541	if (ret)
 542		return ret;
 543
 544	ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE,
 545				   &dd->out_sgl, 0,
 546				   FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
 547	if (ret)
 548		return ret;
 549
 550	dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
 551	if (dd->in_sg_len < 0)
 552		return dd->in_sg_len;
 553
 554	dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
 555	if (dd->out_sg_len < 0)
 556		return dd->out_sg_len;
 557
 558	rctx = skcipher_request_ctx(req);
 559	ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
 560	rctx->mode &= FLAGS_MODE_MASK;
 561	dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
 562
 563	dd->ctx = ctx;
 564	ctx->dd = dd;
 565
 566	return omap_des_write_ctrl(dd);
 567}
 568
 569static int omap_des_crypt_req(struct crypto_engine *engine,
 570			      void *areq)
 571{
 572	struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
 573	struct omap_des_ctx *ctx = crypto_skcipher_ctx(
 574			crypto_skcipher_reqtfm(req));
 575	struct omap_des_dev *dd = omap_des_find_dev(ctx);
 576
 577	if (!dd)
 578		return -ENODEV;
 579
 580	return omap_des_prepare_req(req, dd) ?:
 581	       omap_des_crypt_dma_start(dd);
 582}
 583
 584static void omap_des_done_task(struct work_struct *t)
 585{
 586	struct omap_des_dev *dd = from_work(dd, t, done_task);
 587	int i;
 588
 589	pr_debug("enter done_task\n");
 590
 591	if (!dd->pio_only) {
 592		dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
 593				       DMA_FROM_DEVICE);
 594		dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 595		dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 596			     DMA_FROM_DEVICE);
 597		omap_des_crypt_dma_stop(dd);
 598	}
 599
 600	omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save,
 601			    FLAGS_IN_DATA_ST_SHIFT, dd->flags);
 602
 603	omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
 604			    FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
 605
 606	if ((dd->flags & FLAGS_CBC) && dd->req->iv)
 607		for (i = 0; i < 2; i++)
 608			((u32 *)dd->req->iv)[i] =
 609				omap_des_read(dd, DES_REG_IV(dd, i));
 610
 611	omap_des_finish_req(dd, 0);
 612
 613	pr_debug("exit\n");
 614}
 615
 616static int omap_des_crypt(struct skcipher_request *req, unsigned long mode)
 617{
 618	struct omap_des_ctx *ctx = crypto_skcipher_ctx(
 619			crypto_skcipher_reqtfm(req));
 620	struct omap_des_reqctx *rctx = skcipher_request_ctx(req);
 621	struct omap_des_dev *dd;
 622
 623	pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
 624		 !!(mode & FLAGS_ENCRYPT),
 625		 !!(mode & FLAGS_CBC));
 626
 627	if (!req->cryptlen)
 628		return 0;
 629
 630	if (!IS_ALIGNED(req->cryptlen, DES_BLOCK_SIZE))
 631		return -EINVAL;
 632
 633	dd = omap_des_find_dev(ctx);
 634	if (!dd)
 635		return -ENODEV;
 636
 637	rctx->mode = mode;
 638
 639	return omap_des_handle_queue(dd, req);
 640}
 641
 642/* ********************** ALG API ************************************ */
 643
 644static int omap_des_setkey(struct crypto_skcipher *cipher, const u8 *key,
 645			   unsigned int keylen)
 646{
 647	struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
 648	int err;
 649
 650	pr_debug("enter, keylen: %d\n", keylen);
 651
 652	err = verify_skcipher_des_key(cipher, key);
 653	if (err)
 654		return err;
 655
 656	memcpy(ctx->key, key, keylen);
 657	ctx->keylen = keylen;
 658
 659	return 0;
 660}
 661
 662static int omap_des3_setkey(struct crypto_skcipher *cipher, const u8 *key,
 663			    unsigned int keylen)
 664{
 665	struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
 666	int err;
 667
 668	pr_debug("enter, keylen: %d\n", keylen);
 669
 670	err = verify_skcipher_des3_key(cipher, key);
 671	if (err)
 672		return err;
 673
 674	memcpy(ctx->key, key, keylen);
 675	ctx->keylen = keylen;
 676
 677	return 0;
 678}
 679
 680static int omap_des_ecb_encrypt(struct skcipher_request *req)
 681{
 682	return omap_des_crypt(req, FLAGS_ENCRYPT);
 683}
 684
 685static int omap_des_ecb_decrypt(struct skcipher_request *req)
 686{
 687	return omap_des_crypt(req, 0);
 688}
 689
 690static int omap_des_cbc_encrypt(struct skcipher_request *req)
 691{
 692	return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
 693}
 694
 695static int omap_des_cbc_decrypt(struct skcipher_request *req)
 696{
 697	return omap_des_crypt(req, FLAGS_CBC);
 698}
 699
 700static int omap_des_init_tfm(struct crypto_skcipher *tfm)
 701{
 702	pr_debug("enter\n");
 703
 704	crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_des_reqctx));
 705
 706	return 0;
 707}
 708
 709/* ********************** ALGS ************************************ */
 710
 711static struct skcipher_engine_alg algs_ecb_cbc[] = {
 712{
 713	.base = {
 714		.base.cra_name		= "ecb(des)",
 715		.base.cra_driver_name	= "ecb-des-omap",
 716		.base.cra_priority	= 300,
 717		.base.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
 718					  CRYPTO_ALG_ASYNC,
 719		.base.cra_blocksize	= DES_BLOCK_SIZE,
 720		.base.cra_ctxsize	= sizeof(struct omap_des_ctx),
 721		.base.cra_module	= THIS_MODULE,
 722
 723		.min_keysize		= DES_KEY_SIZE,
 724		.max_keysize		= DES_KEY_SIZE,
 725		.setkey			= omap_des_setkey,
 726		.encrypt		= omap_des_ecb_encrypt,
 727		.decrypt		= omap_des_ecb_decrypt,
 728		.init			= omap_des_init_tfm,
 729	},
 730	.op.do_one_request = omap_des_crypt_req,
 731},
 732{
 733	.base = {
 734		.base.cra_name		= "cbc(des)",
 735		.base.cra_driver_name	= "cbc-des-omap",
 736		.base.cra_priority	= 300,
 737		.base.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
 738					  CRYPTO_ALG_ASYNC,
 739		.base.cra_blocksize	= DES_BLOCK_SIZE,
 740		.base.cra_ctxsize	= sizeof(struct omap_des_ctx),
 741		.base.cra_module	= THIS_MODULE,
 742
 743		.min_keysize		= DES_KEY_SIZE,
 744		.max_keysize		= DES_KEY_SIZE,
 745		.ivsize			= DES_BLOCK_SIZE,
 746		.setkey			= omap_des_setkey,
 747		.encrypt		= omap_des_cbc_encrypt,
 748		.decrypt		= omap_des_cbc_decrypt,
 749		.init			= omap_des_init_tfm,
 750	},
 751	.op.do_one_request = omap_des_crypt_req,
 752},
 753{
 754	.base = {
 755		.base.cra_name		= "ecb(des3_ede)",
 756		.base.cra_driver_name	= "ecb-des3-omap",
 757		.base.cra_priority	= 300,
 758		.base.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
 759					  CRYPTO_ALG_ASYNC,
 760		.base.cra_blocksize	= DES3_EDE_BLOCK_SIZE,
 761		.base.cra_ctxsize	= sizeof(struct omap_des_ctx),
 762		.base.cra_module	= THIS_MODULE,
 763
 764		.min_keysize		= DES3_EDE_KEY_SIZE,
 765		.max_keysize		= DES3_EDE_KEY_SIZE,
 766		.setkey			= omap_des3_setkey,
 767		.encrypt		= omap_des_ecb_encrypt,
 768		.decrypt		= omap_des_ecb_decrypt,
 769		.init			= omap_des_init_tfm,
 770	},
 771	.op.do_one_request = omap_des_crypt_req,
 772},
 773{
 774	.base = {
 775		.base.cra_name		= "cbc(des3_ede)",
 776		.base.cra_driver_name	= "cbc-des3-omap",
 777		.base.cra_priority	= 300,
 778		.base.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |
 779					  CRYPTO_ALG_ASYNC,
 780		.base.cra_blocksize	= DES3_EDE_BLOCK_SIZE,
 781		.base.cra_ctxsize	= sizeof(struct omap_des_ctx),
 782		.base.cra_module	= THIS_MODULE,
 783
 784		.min_keysize		= DES3_EDE_KEY_SIZE,
 785		.max_keysize		= DES3_EDE_KEY_SIZE,
 786		.ivsize			= DES3_EDE_BLOCK_SIZE,
 787		.setkey			= omap_des3_setkey,
 788		.encrypt		= omap_des_cbc_encrypt,
 789		.decrypt		= omap_des_cbc_decrypt,
 790		.init			= omap_des_init_tfm,
 791	},
 792	.op.do_one_request = omap_des_crypt_req,
 793}
 794};
 795
 796static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
 797	{
 798		.algs_list	= algs_ecb_cbc,
 799		.size		= ARRAY_SIZE(algs_ecb_cbc),
 800	},
 801};
 802
 803#ifdef CONFIG_OF
 804static const struct omap_des_pdata omap_des_pdata_omap4 = {
 805	.algs_info	= omap_des_algs_info_ecb_cbc,
 806	.algs_info_size	= ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
 807	.trigger	= omap_des_dma_trigger_omap4,
 808	.key_ofs	= 0x14,
 809	.iv_ofs		= 0x18,
 810	.ctrl_ofs	= 0x20,
 811	.data_ofs	= 0x28,
 812	.rev_ofs	= 0x30,
 813	.mask_ofs	= 0x34,
 814	.irq_status_ofs = 0x3c,
 815	.irq_enable_ofs = 0x40,
 816	.dma_enable_in	= BIT(5),
 817	.dma_enable_out	= BIT(6),
 818	.major_mask	= 0x0700,
 819	.major_shift	= 8,
 820	.minor_mask	= 0x003f,
 821	.minor_shift	= 0,
 822};
 823
 824static irqreturn_t omap_des_irq(int irq, void *dev_id)
 825{
 826	struct omap_des_dev *dd = dev_id;
 827	u32 status, i;
 828	u32 *src, *dst;
 829
 830	status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
 831	if (status & DES_REG_IRQ_DATA_IN) {
 832		omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
 833
 834		BUG_ON(!dd->in_sg);
 835
 836		BUG_ON(dd->in_sg_offset > dd->in_sg->length);
 837
 838		src = sg_virt(dd->in_sg) + dd->in_sg_offset;
 839
 840		for (i = 0; i < DES_BLOCK_WORDS; i++) {
 841			omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
 842			dd->in_sg_offset += 4;
 843			if (dd->in_sg_offset == dd->in_sg->length) {
 844				dd->in_sg = sg_next(dd->in_sg);
 845				if (dd->in_sg) {
 846					dd->in_sg_offset = 0;
 847					src = sg_virt(dd->in_sg);
 848				}
 849			} else {
 850				src++;
 851			}
 852		}
 853
 854		/* Clear IRQ status */
 855		status &= ~DES_REG_IRQ_DATA_IN;
 856		omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
 857
 858		/* Enable DATA_OUT interrupt */
 859		omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
 860
 861	} else if (status & DES_REG_IRQ_DATA_OUT) {
 862		omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
 863
 864		BUG_ON(!dd->out_sg);
 865
 866		BUG_ON(dd->out_sg_offset > dd->out_sg->length);
 867
 868		dst = sg_virt(dd->out_sg) + dd->out_sg_offset;
 869
 870		for (i = 0; i < DES_BLOCK_WORDS; i++) {
 871			*dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
 872			dd->out_sg_offset += 4;
 873			if (dd->out_sg_offset == dd->out_sg->length) {
 874				dd->out_sg = sg_next(dd->out_sg);
 875				if (dd->out_sg) {
 876					dd->out_sg_offset = 0;
 877					dst = sg_virt(dd->out_sg);
 878				}
 879			} else {
 880				dst++;
 881			}
 882		}
 883
 884		BUG_ON(dd->total < DES_BLOCK_SIZE);
 885
 886		dd->total -= DES_BLOCK_SIZE;
 887
 888		/* Clear IRQ status */
 889		status &= ~DES_REG_IRQ_DATA_OUT;
 890		omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
 891
 892		if (!dd->total)
 893			/* All bytes read! */
 894			queue_work(system_bh_wq, &dd->done_task);
 895		else
 896			/* Enable DATA_IN interrupt for next block */
 897			omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
 898	}
 899
 900	return IRQ_HANDLED;
 901}
 902
 903static const struct of_device_id omap_des_of_match[] = {
 904	{
 905		.compatible	= "ti,omap4-des",
 906		.data		= &omap_des_pdata_omap4,
 907	},
 908	{},
 909};
 910MODULE_DEVICE_TABLE(of, omap_des_of_match);
 911
 912static int omap_des_get_of(struct omap_des_dev *dd,
 913		struct platform_device *pdev)
 914{
 915
 916	dd->pdata = of_device_get_match_data(&pdev->dev);
 917	if (!dd->pdata) {
 918		dev_err(&pdev->dev, "no compatible OF match\n");
 919		return -EINVAL;
 920	}
 921
 922	return 0;
 923}
 924#else
 925static int omap_des_get_of(struct omap_des_dev *dd,
 926		struct device *dev)
 927{
 928	return -EINVAL;
 929}
 930#endif
 931
 932static int omap_des_get_pdev(struct omap_des_dev *dd,
 933		struct platform_device *pdev)
 934{
 935	/* non-DT devices get pdata from pdev */
 936	dd->pdata = pdev->dev.platform_data;
 937
 938	return 0;
 939}
 940
 941static int omap_des_probe(struct platform_device *pdev)
 942{
 943	struct device *dev = &pdev->dev;
 944	struct omap_des_dev *dd;
 945	struct skcipher_engine_alg *algp;
 946	struct resource *res;
 947	int err = -ENOMEM, i, j, irq = -1;
 948	u32 reg;
 949
 950	dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
 951	if (dd == NULL) {
 952		dev_err(dev, "unable to alloc data struct.\n");
 953		goto err_data;
 954	}
 955	dd->dev = dev;
 956	platform_set_drvdata(pdev, dd);
 957
 958	err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
 959			       omap_des_get_pdev(dd, pdev);
 960	if (err)
 961		goto err_res;
 962
 963	dd->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 964	if (IS_ERR(dd->io_base)) {
 965		err = PTR_ERR(dd->io_base);
 966		goto err_res;
 967	}
 968	dd->phys_base = res->start;
 969
 970	pm_runtime_use_autosuspend(dev);
 971	pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
 972
 973	pm_runtime_enable(dev);
 974	err = pm_runtime_resume_and_get(dev);
 975	if (err < 0) {
 976		dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
 977		goto err_get;
 978	}
 979
 980	omap_des_dma_stop(dd);
 981
 982	reg = omap_des_read(dd, DES_REG_REV(dd));
 983
 984	pm_runtime_put_sync(dev);
 985
 986	dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
 987		 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
 988		 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
 989
 990	INIT_WORK(&dd->done_task, omap_des_done_task);
 991
 992	err = omap_des_dma_init(dd);
 993	if (err == -EPROBE_DEFER) {
 994		goto err_irq;
 995	} else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
 996		dd->pio_only = 1;
 997
 998		irq = platform_get_irq(pdev, 0);
 999		if (irq < 0) {
1000			err = irq;
1001			goto err_irq;
1002		}
1003
1004		err = devm_request_irq(dev, irq, omap_des_irq, 0,
1005				dev_name(dev), dd);
1006		if (err) {
1007			dev_err(dev, "Unable to grab omap-des IRQ\n");
1008			goto err_irq;
1009		}
1010	}
1011
1012
1013	INIT_LIST_HEAD(&dd->list);
1014	spin_lock_bh(&list_lock);
1015	list_add_tail(&dd->list, &dev_list);
1016	spin_unlock_bh(&list_lock);
1017
1018	/* Initialize des crypto engine */
1019	dd->engine = crypto_engine_alloc_init(dev, 1);
1020	if (!dd->engine) {
1021		err = -ENOMEM;
1022		goto err_engine;
1023	}
1024
1025	err = crypto_engine_start(dd->engine);
1026	if (err)
1027		goto err_engine;
1028
1029	for (i = 0; i < dd->pdata->algs_info_size; i++) {
1030		for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1031			algp = &dd->pdata->algs_info[i].algs_list[j];
1032
1033			pr_debug("reg alg: %s\n", algp->base.base.cra_name);
1034
1035			err = crypto_engine_register_skcipher(algp);
1036			if (err)
1037				goto err_algs;
1038
1039			dd->pdata->algs_info[i].registered++;
1040		}
1041	}
1042
1043	return 0;
1044
1045err_algs:
1046	for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1047		for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1048			crypto_engine_unregister_skcipher(
1049					&dd->pdata->algs_info[i].algs_list[j]);
1050
1051err_engine:
1052	if (dd->engine)
1053		crypto_engine_exit(dd->engine);
1054
1055	omap_des_dma_cleanup(dd);
1056err_irq:
1057	cancel_work_sync(&dd->done_task);
1058err_get:
1059	pm_runtime_disable(dev);
1060err_res:
1061	dd = NULL;
1062err_data:
1063	dev_err(dev, "initialization failed.\n");
1064	return err;
1065}
1066
1067static void omap_des_remove(struct platform_device *pdev)
1068{
1069	struct omap_des_dev *dd = platform_get_drvdata(pdev);
1070	int i, j;
1071
1072	spin_lock_bh(&list_lock);
1073	list_del(&dd->list);
1074	spin_unlock_bh(&list_lock);
1075
1076	for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1077		for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1078			crypto_engine_unregister_skcipher(
1079					&dd->pdata->algs_info[i].algs_list[j]);
1080
1081	cancel_work_sync(&dd->done_task);
1082	omap_des_dma_cleanup(dd);
1083	pm_runtime_disable(dd->dev);
1084}
1085
1086#ifdef CONFIG_PM_SLEEP
1087static int omap_des_suspend(struct device *dev)
1088{
1089	pm_runtime_put_sync(dev);
1090	return 0;
1091}
1092
1093static int omap_des_resume(struct device *dev)
1094{
1095	int err;
1096
1097	err = pm_runtime_resume_and_get(dev);
1098	if (err < 0) {
1099		dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
1100		return err;
1101	}
1102	return 0;
1103}
1104#endif
1105
1106static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
1107
1108static struct platform_driver omap_des_driver = {
1109	.probe	= omap_des_probe,
1110	.remove = omap_des_remove,
1111	.driver	= {
1112		.name	= "omap-des",
1113		.pm	= &omap_des_pm_ops,
1114		.of_match_table	= of_match_ptr(omap_des_of_match),
1115	},
1116};
1117
1118module_platform_driver(omap_des_driver);
1119
1120MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1121MODULE_LICENSE("GPL v2");
1122MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");