icp_qat_hw_51_comp_defs.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Copyright(c) 2025 Intel Corporation */
  3#ifndef ICP_QAT_HW_51_COMP_DEFS_H_
  4#define ICP_QAT_HW_51_COMP_DEFS_H_
  5
  6#include <linux/bits.h>
  7
  8#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_BITPOS	28
  9#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_MASK		GENMASK(1, 0)
 10enum icp_qat_hw_comp_51_som_control {
 11	ICP_QAT_HW_COMP_51_SOM_CONTROL_NORMAL_MODE = 0x0,
 12	ICP_QAT_HW_COMP_51_SOM_CONTROL_DICTIONARY_MODE = 0x1,
 13	ICP_QAT_HW_COMP_51_SOM_CONTROL_INPUT_CRC = 0x2,
 14	ICP_QAT_HW_COMP_51_SOM_CONTROL_RESERVED_MODE = 0x3,
 15};
 16
 17#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_DEFAULT_VAL \
 18	ICP_QAT_HW_COMP_51_SOM_CONTROL_NORMAL_MODE
 19#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS	27
 20#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK		GENMASK(0, 0)
 21enum icp_qat_hw_comp_51_skip_hash_rd_control {
 22	ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_NO_SKIP = 0x0,
 23	ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_SKIP_HASH_READS = 0x1,
 24};
 25
 26#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_DEFAULT_VAL \
 27	ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_NO_SKIP
 28#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_BITPOS	25
 29#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_MASK	GENMASK(0, 0)
 30enum icp_qat_hw_comp_51_bypass_compression {
 31	ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_DISABLED = 0x0,
 32	ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_ENABLED = 0x1,
 33};
 34
 35#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_DEFAULT_VAL \
 36	ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_DISABLED
 37#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_BITPOS	22
 38#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_MASK	GENMASK(0, 0)
 39enum icp_qat_hw_comp_51_dmm_algorithm {
 40	ICP_QAT_HW_COMP_51_DMM_ALGORITHM_EDMM_ENABLED = 0x0,
 41	ICP_QAT_HW_COMP_51_DMM_ALGORITHM_ZSTD_DMM_LITE = 0x1,
 42};
 43
 44#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_DEFAULT_VAL \
 45	ICP_QAT_HW_COMP_51_DMM_ALGORITHM_EDMM_ENABLED
 46#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_BITPOS	21
 47#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_MASK	GENMASK(0, 0)
 48enum icp_qat_hw_comp_51_token_fusion_internal_only {
 49	ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_ENABLED = 0x0,
 50	ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_DISABLED = 0x1,
 51};
 52
 53#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_DEFAULT_VAL \
 54	ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_ENABLED
 55#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_BITPOS	19
 56#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_MASK		GENMASK(1, 0)
 57enum icp_qat_hw_comp_51_bms {
 58	ICP_QAT_HW_COMP_51_BMS_BMS_64KB = 0x0,
 59	ICP_QAT_HW_COMP_51_BMS_BMS_256KB = 0x1,
 60	ICP_QAT_HW_COMP_51_BMS_BMS_1MB = 0x2,
 61	ICP_QAT_HW_COMP_51_BMS_BMS_4MB = 0x3,
 62};
 63
 64#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_DEFAULT_VAL \
 65	ICP_QAT_HW_COMP_51_BMS_BMS_64KB
 66#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS	18
 67#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK		GENMASK(0, 0)
 68enum icp_qat_hw_comp_51_scb_mode_reset_mask {
 69	ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_DO_NOT_RESET_HB_HT = 0x0,
 70	ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_RESET_HB_HT = 0x1,
 71};
 72
 73#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_DEFAULT_VAL \
 74	ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_DO_NOT_RESET_HB_HT
 75#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_BITPOS	2
 76#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_MASK	GENMASK(0, 0)
 77enum icp_qat_hw_comp_51_zstd_frame_gen_dec_en {
 78	ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_DISABLE = 0x0,
 79	ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE = 0x1,
 80};
 81
 82#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_DEFAULT_VAL \
 83	ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE
 84#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_BITPOS	1
 85#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_MASK		GENMASK(0, 0)
 86enum icp_qat_hw_comp_51_cnv_disable {
 87	ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_ENABLED = 0x0,
 88	ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_DISABLED = 0x1,
 89};
 90
 91#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_DEFAULT_VAL \
 92	ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_ENABLED
 93#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ASB_DISABLE_BITPOS	0
 94#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ASB_DISABLE_MASK		GENMASK(0, 0)
 95enum icp_qat_hw_comp_51_asb_disable {
 96	ICP_QAT_HW_COMP_51_ASB_DISABLE_ASB_ENABLED = 0x0,
 97	ICP_QAT_HW_COMP_51_ASB_DISABLE_ASB_DISABLED = 0x1,
 98};
 99
100#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ASB_DISABLE_DEFAULT_VAL \
101	ICP_QAT_HW_COMP_51_ASB_DISABLE_ASB_ENABLED
102#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_BITPOS	21
103#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_MASK	GENMASK(0, 0)
104enum icp_qat_hw_comp_51_spec_decoder_internal_only {
105	ICP_QAT_HW_COMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL = 0x0,
106	ICP_QAT_HW_COMP_51_SPEC_DECODER_INTERNAL_ONLY_DISABLED = 0x1,
107};
108
109#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_DEFAULT_VAL \
110	ICP_QAT_HW_COMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL
111#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_BITPOS	20
112#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_MASK	GENMASK(0, 0)
113enum icp_qat_hw_comp_51_mini_xcam_internal_only {
114	ICP_QAT_HW_COMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL = 0x0,
115	ICP_QAT_HW_COMP_51_MINI_XCAM_INTERNAL_ONLY_DISABLED = 0x1,
116};
117
118#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_DEFAULT_VAL \
119	ICP_QAT_HW_COMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL
120#define ICP_QAT_HW_COMP_51_CONFIG_CSR_REP_OFF_ENC_INTERNAL_ONLY_BITPOS	19
121#define ICP_QAT_HW_COMP_51_CONFIG_CSR_REP_OFF_ENC_INTERNAL_ONLY_MASK	GENMASK(0, 0)
122enum icp_qat_hw_comp_51_rep_off_enc_internal_only {
123	ICP_QAT_HW_COMP_51_REP_OFF_ENC_INTERNAL_ONLY_ENABLED = 0x0,
124	ICP_QAT_HW_COMP_51_REP_OFF_ENC_INTERNAL_ONLY_DISABLED = 0x1,
125};
126
127#define ICP_QAT_HW_COMP_51_CONFIG_CSR_REP_OFF_ENC_INTERNAL_ONLY_DEFAULT_VAL \
128	ICP_QAT_HW_COMP_51_REP_OFF_ENC_INTERNAL_ONLY_ENABLED
129#define ICP_QAT_HW_COMP_51_CONFIG_CSR_PROG_BLOCK_DROP_INTERNAL_ONLY_BITPOS	18
130#define ICP_QAT_HW_COMP_51_CONFIG_CSR_PROG_BLOCK_DROP_INTERNAL_ONLY_MASK	GENMASK(0, 0)
131enum icp_qat_hw_comp_51_prog_block_drop_internal_only {
132	ICP_QAT_HW_COMP_51_PROG_BLOCK_DROP_INTERNAL_ONLY_DISABLE = 0x0,
133	ICP_QAT_HW_COMP_51_PROG_BLOCK_DROP_INTERNAL_ONLY_ENABLE = 0x1,
134};
135
136#define ICP_QAT_HW_COMP_51_CONFIG_CSR_PROG_BLOCK_DROP_INTERNAL_ONLY_DEFAULT_VAL \
137	ICP_QAT_HW_COMP_51_PROG_BLOCK_DROP_INTERNAL_ONLY_DISABLE
138#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_BITPOS	17
139#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_MASK	GENMASK(0, 0)
140enum icp_qat_hw_comp_51_skip_hash_override_internal_only {
141	ICP_QAT_HW_COMP_51_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_DETERMINE_HASH_PARAMS = 0x0,
142	ICP_QAT_HW_COMP_51_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_OVERRIDE_HASH_PARAMS = 0x1,
143};
144
145#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_DEFAULT_VAL \
146	ICP_QAT_HW_COMP_51_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_DETERMINE_HASH_PARAMS
147#define ICP_QAT_HW_COMP_51_CONFIG_CSR_HBS_BITPOS	14
148#define ICP_QAT_HW_COMP_51_CONFIG_CSR_HBS_MASK		GENMASK(2, 0)
149enum icp_qat_hw_comp_51_hbs {
150	ICP_QAT_HW_COMP_51_HBS_32KB = 0x0,
151	ICP_QAT_HW_COMP_51_HBS_64KB = 0x1,
152};
153
154#define ICP_QAT_HW_COMP_51_CONFIG_CSR_HBS_DEFAULT_VAL \
155	ICP_QAT_HW_COMP_51_HBS_32KB
156#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_BITPOS	13
157#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_MASK		GENMASK(0, 0)
158enum icp_qat_hw_comp_51_abd {
159	ICP_QAT_HW_COMP_51_ABD_ABD_ENABLED = 0x0,
160	ICP_QAT_HW_COMP_51_ABD_ABD_DISABLED = 0x1,
161};
162
163#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_DEFAULT_VAL \
164	ICP_QAT_HW_COMP_51_ABD_ABD_ENABLED
165#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_BITPOS	12
166#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_MASK	GENMASK(0, 0)
167enum icp_qat_hw_comp_51_lllbd_ctrl {
168	ICP_QAT_HW_COMP_51_LLLBD_CTRL_LLLBD_ENABLED = 0x0,
169	ICP_QAT_HW_COMP_51_LLLBD_CTRL_LLLBD_DISABLED = 0x1,
170};
171
172#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_DEFAULT_VAL \
173	ICP_QAT_HW_COMP_51_LLLBD_CTRL_LLLBD_ENABLED
174#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_BITPOS	8
175#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_MASK		GENMASK(3, 0)
176enum icp_qat_hw_comp_51_search_depth {
177	ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_1 = 0x1,
178	ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_6 = 0x3,
179	ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_9 = 0x4,
180	ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_10 = 0x4,
181};
182
183#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_DEFAULT_VAL \
184	ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_1
185#define ICP_QAT_HW_COMP_51_CONFIG_CSR_FORMAT_BITPOS	5
186#define ICP_QAT_HW_COMP_51_CONFIG_CSR_FORMAT_MASK	GENMASK(2, 0)
187enum icp_qat_hw_comp_51_format {
188	ICP_QAT_HW_COMP_51_FORMAT_ILZ77 = 0x1,
189	ICP_QAT_HW_COMP_51_FORMAT_LZ4 = 0x2,
190	ICP_QAT_HW_COMP_51_FORMAT_LZ4s = 0x3,
191	ICP_QAT_HW_COMP_51_FORMAT_ZSTD = 0x4,
192};
193
194#define ICP_QAT_HW_COMP_51_CONFIG_CSR_FORMAT_DEFAULT_VAL \
195	ICP_QAT_HW_COMP_51_FORMAT_ILZ77
196#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS	4
197#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_MASK	GENMASK(0, 0)
198enum icp_qat_hw_comp_51_min_match_control {
199	ICP_QAT_HW_COMP_51_MIN_MATCH_CONTROL_MATCH_3B = 0x0,
200	ICP_QAT_HW_COMP_51_MIN_MATCH_CONTROL_MATCH_4B = 0x1,
201};
202
203#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL \
204	ICP_QAT_HW_COMP_51_MIN_MATCH_CONTROL_MATCH_3B
205#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS	3
206#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_COLLISION_MASK		GENMASK(0, 0)
207enum icp_qat_hw_comp_51_skip_hash_collision {
208	ICP_QAT_HW_COMP_51_SKIP_HASH_COLLISION_ALLOW = 0x0,
209	ICP_QAT_HW_COMP_51_SKIP_HASH_COLLISION_DONT_ALLOW = 0x1,
210};
211
212#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_COLLISION_DEFAULT_VAL \
213	ICP_QAT_HW_COMP_51_SKIP_HASH_COLLISION_ALLOW
214#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS	2
215#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_UPDATE_MASK	GENMASK(0, 0)
216enum icp_qat_hw_comp_51_skip_hash_update {
217	ICP_QAT_HW_COMP_51_SKIP_HASH_UPDATE_ALLOW = 0x0,
218	ICP_QAT_HW_COMP_51_SKIP_HASH_UPDATE_DONT_ALLOW = 0x1,
219};
220
221#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_UPDATE_DEFAULT_VAL \
222	ICP_QAT_HW_COMP_51_SKIP_HASH_UPDATE_ALLOW
223#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYTE_SKIP_BITPOS	1
224#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYTE_SKIP_MASK	GENMASK(0, 0)
225enum icp_qat_hw_comp_51_byte_skip {
226	ICP_QAT_HW_COMP_51_BYTE_SKIP_3BYTE_TOKEN = 0x0,
227	ICP_QAT_HW_COMP_51_BYTE_SKIP_3BYTE_LITERAL = 0x1,
228};
229
230#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYTE_SKIP_DEFAULT_VAL \
231	ICP_QAT_HW_COMP_51_BYTE_SKIP_3BYTE_TOKEN
232#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_BITPOS	0
233#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK	GENMASK(0, 0)
234enum icp_qat_hw_comp_51_lz4_block_checksum {
235	ICP_QAT_HW_COMP_51_LZ4_BLOCK_CHECKSUM_ABSENT = 0x0,
236	ICP_QAT_HW_COMP_51_LZ4_BLOCK_CHECKSUM_PRESENT = 0x1,
237};
238
239#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_DEFAULT_VAL \
240	ICP_QAT_HW_COMP_51_LZ4_BLOCK_CHECKSUM_ABSENT
241#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_DISCARD_DATA_BITPOS	26
242#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_DISCARD_DATA_MASK	GENMASK(0, 0)
243enum icp_qat_hw_decomp_51_discard_data {
244	ICP_QAT_HW_DECOMP_51_DISCARD_DATA_DISABLED = 0x0,
245	ICP_QAT_HW_DECOMP_51_DISCARD_DATA_ENABLED = 0x1,
246};
247
248#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_DISCARD_DATA_DEFAULT_VAL \
249	ICP_QAT_HW_DECOMP_51_DISCARD_DATA_DISABLED
250#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_BITPOS	19
251#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_MASK	GENMASK(1, 0)
252enum icp_qat_hw_decomp_51_bms {
253	ICP_QAT_HW_DECOMP_51_BMS_BMS_64KB = 0x0,
254	ICP_QAT_HW_DECOMP_51_BMS_BMS_256KB = 0x1,
255	ICP_QAT_HW_DECOMP_51_BMS_BMS_1MB = 0x2,
256	ICP_QAT_HW_DECOMP_51_BMS_BMS_4MB = 0x3,
257};
258
259#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_DEFAULT_VAL \
260	ICP_QAT_HW_DECOMP_51_BMS_BMS_64KB
261#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_BITPOS	2
262#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_MASK	GENMASK(0, 0)
263enum icp_qat_hw_decomp_51_zstd_frame_gen_dec_en {
264	ICP_QAT_HW_DECOMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_DISABLE = 0x0,
265	ICP_QAT_HW_DECOMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE = 0x1,
266};
267
268#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_DEFAULT_VAL \
269	ICP_QAT_HW_DECOMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE
270#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_BITPOS	21
271#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_MASK		GENMASK(0, 0)
272enum icp_qat_hw_decomp_51_spec_decoder_internal_only {
273	ICP_QAT_HW_DECOMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL = 0x0,
274	ICP_QAT_HW_DECOMP_51_SPEC_DECODER_INTERNAL_ONLY_DISABLED = 0x1,
275};
276
277#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_DEFAULT_VAL \
278	ICP_QAT_HW_DECOMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL
279#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_BITPOS	20
280#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_MASK	GENMASK(0, 0)
281enum icp_qat_hw_decomp_51_mini_xcam_internal_only {
282	ICP_QAT_HW_DECOMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL = 0x0,
283	ICP_QAT_HW_DECOMP_51_MINI_XCAM_INTERNAL_ONLY_DISABLED = 0x1,
284};
285
286#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_DEFAULT_VAL \
287	ICP_QAT_HW_DECOMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL
288#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_HBS_BITPOS	14
289#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_HBS_MASK	GENMASK(2, 0)
290enum icp_qat_hw_decomp_51_hbs {
291	ICP_QAT_HW_DECOMP_51_HBS_32KB = 0x0,
292	ICP_QAT_HW_DECOMP_51_HBS_64KB = 0x1,
293};
294
295#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_HBS_DEFAULT_VAL \
296	ICP_QAT_HW_DECOMP_51_HBS_32KB
297#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_FORMAT_BITPOS	5
298#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_FORMAT_MASK	GENMASK(2, 0)
299enum icp_qat_hw_decomp_51_format {
300	ICP_QAT_HW_DECOMP_51_FORMAT_ILZ77 = 0x1,
301	ICP_QAT_HW_DECOMP_51_FORMAT_LZ4 = 0x2,
302	ICP_QAT_HW_DECOMP_51_FORMAT_RESERVED = 0x3,
303	ICP_QAT_HW_DECOMP_51_FORMAT_ZSTD = 0x4,
304};
305
306#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_FORMAT_DEFAULT_VAL \
307	ICP_QAT_HW_DECOMP_51_FORMAT_ILZ77
308#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_BITPOS	0
309#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK		GENMASK(0, 0)
310enum icp_qat_hw_decomp_51_lz4_block_checksum {
311	ICP_QAT_HW_DECOMP_51_LZ4_BLOCK_CHECKSUM_ABSENT = 0x0,
312	ICP_QAT_HW_DECOMP_51_LZ4_BLOCK_CHECKSUM_PRESENT = 0x1,
313};
314
315#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_DEFAULT_VAL \
316	ICP_QAT_HW_DECOMP_51_LZ4_BLOCK_CHECKSUM_ABSENT
317
318#endif /* ICP_QAT_HW_51_COMP_DEFS_H_ */